^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // wm831x-dcdc.c -- DC-DC buck converter driver for the WM831x series
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2009 Wolfson Microelectronics PLC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/wm831x/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/wm831x/regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/mfd/wm831x/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WM831X_BUCKV_MAX_SELECTOR 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WM831X_BUCKP_MAX_SELECTOR 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WM831X_DCDC_MODE_FAST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WM831X_DCDC_MODE_NORMAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WM831X_DCDC_MODE_IDLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WM831X_DCDC_MODE_STANDBY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define WM831X_DCDC_MAX_NAME 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Register offsets in control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define WM831X_DCDC_CONTROL_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define WM831X_DCDC_CONTROL_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define WM831X_DCDC_ON_CONFIG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define WM831X_DCDC_SLEEP_CONTROL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define WM831X_DCDC_DVS_CONTROL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct wm831x_dcdc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) char name[WM831X_DCDC_MAX_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) char supply_name[WM831X_DCDC_MAX_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) struct wm831x *wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct regulator_dev *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct gpio_desc *dvs_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int dvs_gpio_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int on_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) int dvs_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static unsigned int wm831x_dcdc_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val = wm831x_reg_read(wm831x, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) val = (val & WM831X_DC1_ON_MODE_MASK) >> WM831X_DC1_ON_MODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) case WM831X_DCDC_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) case WM831X_DCDC_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case WM831X_DCDC_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) case WM831X_DCDC_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int wm831x_dcdc_set_mode_int(struct wm831x *wm831x, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) val = WM831X_DCDC_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) val = WM831X_DCDC_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) val = WM831X_DCDC_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) val = WM831X_DCDC_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return wm831x_set_bits(wm831x, reg, WM831X_DC1_ON_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) val << WM831X_DC1_ON_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int wm831x_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int wm831x_dcdc_set_suspend_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return wm831x_dcdc_set_mode_int(wm831x, reg, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static int wm831x_dcdc_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* First, check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (ret & (1 << rdev_get_id(rdev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) rdev_get_id(rdev) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return REGULATOR_STATUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* DCDC1 and DCDC2 can additionally detect high voltage/current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (rdev_get_id(rdev) < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret & (WM831X_DC1_OV_STS << rdev_get_id(rdev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_dbg(wm831x->dev, "DCDC%d over voltage\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) rdev_get_id(rdev) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) return REGULATOR_STATUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (ret & (WM831X_DC1_HC_STS << rdev_get_id(rdev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) dev_dbg(wm831x->dev, "DCDC%d over current\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) rdev_get_id(rdev) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return REGULATOR_STATUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Is the regulator on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (!(ret & (1 << rdev_get_id(rdev))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* TODO: When we handle hardware control modes so we can report the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * current mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return REGULATOR_STATUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static irqreturn_t wm831x_dcdc_uv_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct wm831x_dcdc *dcdc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regulator_notifier_call_chain(dcdc->regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) REGULATOR_EVENT_UNDER_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static irqreturn_t wm831x_dcdc_oc_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct wm831x_dcdc *dcdc = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) regulator_notifier_call_chain(dcdc->regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) REGULATOR_EVENT_OVER_CURRENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * BUCKV specifics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const struct linear_range wm831x_buckv_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) REGULATOR_LINEAR_RANGE(600000, 0, 0x7, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) REGULATOR_LINEAR_RANGE(600000, 0x8, 0x68, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static int wm831x_buckv_set_dvs(struct regulator_dev *rdev, int state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (state == dcdc->dvs_gpio_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dcdc->dvs_gpio_state = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) gpiod_set_value(dcdc->dvs_gpiod, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Should wait for DVS state change to be asserted if we have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * a GPIO for it, for now assume the device is configured
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * for the fastest possible transition.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int wm831x_buckv_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int on_reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int dvs_reg = dcdc->base + WM831X_DCDC_DVS_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* If this value is already set then do a GPIO update if we can */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (dcdc->dvs_gpiod && dcdc->on_vsel == vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) return wm831x_buckv_set_dvs(rdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (dcdc->dvs_gpiod && dcdc->dvs_vsel == vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return wm831x_buckv_set_dvs(rdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Always set the ON status to the minimum voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = wm831x_set_bits(wm831x, on_reg, WM831X_DC1_ON_VSEL_MASK, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dcdc->on_vsel = vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (!dcdc->dvs_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Kick the voltage transition now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ret = wm831x_buckv_set_dvs(rdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * If this VSEL is higher than the last one we've seen then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * remember it as the DVS VSEL. This is optimised for CPUfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * usage where we want to get to the highest voltage very
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * quickly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (vsel > dcdc->dvs_vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) ret = wm831x_set_bits(wm831x, dvs_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) WM831X_DC1_DVS_VSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dcdc->dvs_vsel = vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev_warn(wm831x->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "Failed to set DCDC DVS VSEL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static int wm831x_buckv_set_suspend_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) int vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) vsel = regulator_map_voltage_linear_range(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (vsel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return wm831x_set_bits(wm831x, reg, WM831X_DC1_SLP_VSEL_MASK, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int wm831x_buckv_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (dcdc->dvs_gpiod && dcdc->dvs_gpio_state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return dcdc->dvs_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return dcdc->on_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Current limit options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const unsigned int wm831x_dcdc_ilim[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 125000, 250000, 375000, 500000, 625000, 750000, 875000, 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static const struct regulator_ops wm831x_buckv_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .set_voltage_sel = wm831x_buckv_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .get_voltage_sel = wm831x_buckv_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .set_suspend_voltage = wm831x_buckv_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .set_current_limit = regulator_set_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .get_current_limit = regulator_get_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .get_status = wm831x_dcdc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .get_mode = wm831x_dcdc_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .set_mode = wm831x_dcdc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Set up DVS control. We just log errors since we can still run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * (with reduced performance) if we fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void wm831x_buckv_dvs_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct wm831x_dcdc *dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct wm831x_buckv_pdata *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u16 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* gpiolib won't let us read the GPIO status so pick the higher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * of the two existing voltages so we take it as platform data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dcdc->dvs_gpio_state = pdata->dvs_init_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dcdc->dvs_gpiod = devm_gpiod_get(&pdev->dev, "dvs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dcdc->dvs_gpio_state ? GPIOD_OUT_HIGH : GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (IS_ERR(dcdc->dvs_gpiod)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dev_err(wm831x->dev, "Failed to get %s DVS GPIO: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dcdc->name, PTR_ERR(dcdc->dvs_gpiod));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) switch (pdata->dvs_control_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ctrl = 2 << WM831X_DC1_DVS_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ctrl = 3 << WM831X_DC1_DVS_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_err(wm831x->dev, "Invalid DVS control source %d for %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) pdata->dvs_control_src, dcdc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* If DVS_VSEL is set to the minimum value then raise it to ON_VSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * to make bootstrapping a bit smoother.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!dcdc->dvs_vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = wm831x_set_bits(wm831x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dcdc->base + WM831X_DCDC_DVS_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) WM831X_DC1_DVS_VSEL_MASK, dcdc->on_vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dcdc->dvs_vsel = dcdc->on_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_warn(wm831x->dev, "Failed to set DVS_VSEL: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ret = wm831x_set_bits(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) WM831X_DC1_DVS_SRC_MASK, ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev_err(wm831x->dev, "Failed to set %s DVS source: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dcdc->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int wm831x_buckv_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct wm831x_dcdc *dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (pdata && pdata->wm831x_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) id = (pdata->wm831x_num * 10) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) id = pdev->id - id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!dcdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) dcdc->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) res = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(&pdev->dev, "No REG resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dcdc->base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dcdc->desc.name = dcdc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) snprintf(dcdc->supply_name, sizeof(dcdc->supply_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "DC%dVDD", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dcdc->desc.supply_name = dcdc->supply_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dcdc->desc.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dcdc->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dcdc->desc.n_voltages = WM831X_BUCKV_MAX_SELECTOR + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dcdc->desc.linear_ranges = wm831x_buckv_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dcdc->desc.n_linear_ranges = ARRAY_SIZE(wm831x_buckv_ranges);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dcdc->desc.ops = &wm831x_buckv_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) dcdc->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dcdc->desc.enable_mask = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dcdc->desc.csel_reg = dcdc->base + WM831X_DCDC_CONTROL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dcdc->desc.csel_mask = WM831X_DC1_HC_THR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dcdc->desc.n_current_limits = ARRAY_SIZE(wm831x_dcdc_ilim);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dcdc->desc.curr_table = wm831x_dcdc_ilim;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_ON_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dev_err(wm831x->dev, "Failed to read ON VSEL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dcdc->on_vsel = ret & WM831X_DC1_ON_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = wm831x_reg_read(wm831x, dcdc->base + WM831X_DCDC_DVS_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(wm831x->dev, "Failed to read DVS VSEL: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dcdc->dvs_vsel = ret & WM831X_DC1_DVS_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (pdata && pdata->dcdc[id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) wm831x_buckv_dvs_init(pdev, dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) pdata->dcdc[id]->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) config.init_data = pdata->dcdc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) config.driver_data = dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (IS_ERR(dcdc->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = PTR_ERR(dcdc->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) wm831x_dcdc_uv_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dcdc->name, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "HC"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) wm831x_dcdc_oc_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) dcdc->name, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) dev_err(&pdev->dev, "Failed to request HC IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) platform_set_drvdata(pdev, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct platform_driver wm831x_buckv_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .probe = wm831x_buckv_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = "wm831x-buckv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) * BUCKP specifics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) static int wm831x_buckp_set_suspend_voltage(struct regulator_dev *rdev, int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u16 reg = dcdc->base + WM831X_DCDC_SLEEP_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) sel = regulator_map_voltage_linear(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return wm831x_set_bits(wm831x, reg, WM831X_DC3_ON_VSEL_MASK, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const struct regulator_ops wm831x_buckp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .set_suspend_voltage = wm831x_buckp_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .get_status = wm831x_dcdc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .get_mode = wm831x_dcdc_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .set_mode = wm831x_dcdc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .set_suspend_mode = wm831x_dcdc_set_suspend_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int wm831x_buckp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct wm831x_dcdc *dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (pdata && pdata->wm831x_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) id = (pdata->wm831x_num * 10) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) id = pdev->id - id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!dcdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dcdc->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) res = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev_err(&pdev->dev, "No REG resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dcdc->base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dcdc->desc.name = dcdc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) snprintf(dcdc->supply_name, sizeof(dcdc->supply_name),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "DC%dVDD", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dcdc->desc.supply_name = dcdc->supply_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dcdc->desc.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) dcdc->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) dcdc->desc.n_voltages = WM831X_BUCKP_MAX_SELECTOR + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dcdc->desc.ops = &wm831x_buckp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dcdc->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dcdc->desc.vsel_reg = dcdc->base + WM831X_DCDC_ON_CONFIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dcdc->desc.vsel_mask = WM831X_DC3_ON_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dcdc->desc.enable_mask = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dcdc->desc.min_uV = 850000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dcdc->desc.uV_step = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) config.init_data = pdata->dcdc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) config.driver_data = dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (IS_ERR(dcdc->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = PTR_ERR(dcdc->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) wm831x_dcdc_uv_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dcdc->name, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) platform_set_drvdata(pdev, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) static struct platform_driver wm831x_buckp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .probe = wm831x_buckp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .name = "wm831x-buckp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) * DCDC boost convertors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int wm831x_boostp_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct wm831x_dcdc *dcdc = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct wm831x *wm831x = dcdc->wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* First, check for errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret = wm831x_reg_read(wm831x, WM831X_DCDC_UV_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (ret & (1 << rdev_get_id(rdev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_dbg(wm831x->dev, "DCDC%d under voltage\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) rdev_get_id(rdev) + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return REGULATOR_STATUS_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* Is the regulator on? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = wm831x_reg_read(wm831x, WM831X_DCDC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ret & (1 << rdev_get_id(rdev)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return REGULATOR_STATUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static const struct regulator_ops wm831x_boostp_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .get_status = wm831x_boostp_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int wm831x_boostp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int id = pdev->id % ARRAY_SIZE(pdata->dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct wm831x_dcdc *dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_dbg(&pdev->dev, "Probing DCDC%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (pdata == NULL || pdata->dcdc[id] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!dcdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dcdc->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) res = platform_get_resource(pdev, IORESOURCE_REG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (res == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_err(&pdev->dev, "No REG resource\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) dcdc->base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) snprintf(dcdc->name, sizeof(dcdc->name), "DCDC%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dcdc->desc.name = dcdc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dcdc->desc.id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dcdc->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) dcdc->desc.ops = &wm831x_boostp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dcdc->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dcdc->desc.enable_mask = 1 << id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) config.init_data = pdata->dcdc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) config.driver_data = dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (IS_ERR(dcdc->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) ret = PTR_ERR(dcdc->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dev_err(wm831x->dev, "Failed to register DCDC%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) irq = wm831x_irq(wm831x, platform_get_irq_byname(pdev, "UV"));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) wm831x_dcdc_uv_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) IRQF_TRIGGER_RISING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dcdc->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dev_err(&pdev->dev, "Failed to request UV IRQ %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) platform_set_drvdata(pdev, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct platform_driver wm831x_boostp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .probe = wm831x_boostp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = "wm831x-boostp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * External Power Enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * These aren't actually DCDCs but look like them in hardware so share
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define WM831X_EPE_BASE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct regulator_ops wm831x_epe_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .get_status = wm831x_dcdc_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int wm831x_epe_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct wm831x *wm831x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct wm831x_pdata *pdata = dev_get_platdata(wm831x->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int id = pdev->id % ARRAY_SIZE(pdata->epe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct wm831x_dcdc *dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) dev_dbg(&pdev->dev, "Probing EPE%d\n", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dcdc = devm_kzalloc(&pdev->dev, sizeof(struct wm831x_dcdc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!dcdc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dcdc->wm831x = wm831x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* For current parts this is correct; probably need to revisit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * in future.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) snprintf(dcdc->name, sizeof(dcdc->name), "EPE%d", id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dcdc->desc.name = dcdc->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dcdc->desc.id = id + WM831X_EPE_BASE; /* Offset in DCDC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dcdc->desc.ops = &wm831x_epe_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dcdc->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dcdc->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dcdc->desc.enable_reg = WM831X_DCDC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dcdc->desc.enable_mask = 1 << dcdc->desc.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) config.init_data = pdata->epe[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) config.driver_data = dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) config.regmap = wm831x->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dcdc->regulator = devm_regulator_register(&pdev->dev, &dcdc->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (IS_ERR(dcdc->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = PTR_ERR(dcdc->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev_err(wm831x->dev, "Failed to register EPE%d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) platform_set_drvdata(pdev, dcdc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static struct platform_driver wm831x_epe_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .probe = wm831x_epe_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .name = "wm831x-epe",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) &wm831x_buckv_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) &wm831x_buckp_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) &wm831x_boostp_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) &wm831x_epe_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static int __init wm831x_dcdc_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) subsys_initcall(wm831x_dcdc_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static void __exit wm831x_dcdc_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) module_exit(wm831x_dcdc_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MODULE_AUTHOR("Mark Brown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) MODULE_DESCRIPTION("WM831x DC-DC convertor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) MODULE_ALIAS("platform:wm831x-buckv");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) MODULE_ALIAS("platform:wm831x-buckp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) MODULE_ALIAS("platform:wm831x-boostp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) MODULE_ALIAS("platform:wm831x-epe");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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