Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Author: Shunqing Chen <csq@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define WL2868C_DEVICE_D1		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define WL2868C_DEVICE_D2		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define WL2868C_DISCHARGE_RESISTORS	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define WL2868C_LDO1_VOUT		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define WL2868C_LDO2_VOUT		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define WL2868C_LDO3_VOUT		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define WL2868C_LDO4_VOUT		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define WL2868C_LDO5_VOUT		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define WL2868C_LDO6_VOUT		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define WL2868C_LDO7_VOUT		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define WL2868C_LDO1_LDO2_SEQ		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define WL2868C_LDO3_LDO4_SEQ		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define WL2868C_LDO5_LDO6_SEQ		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define WL2868C_LDO7_SEQ		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define WL2868C_LDO_EN			0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define WL2868C_SEQ_STATUS		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define WL2868C_LDO1_STATUS		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define WL2868C_LDO1_OCP_CTL		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define WL2868C_LDO2_STATUS		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define WL2868C_LDO2_OCP_CTL		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define WL2868C_LDO3_STATUS		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define WL2868C_LDO3_OCP_CTL		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define WL2868C_LDO4_STATUS		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define WL2868C_LDO4_OCP_CTL		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define WL2868C_LDO5_STATUS		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define WL2868C_LDO5_OCP_CTL		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define WL2868C_LDO6_STATUS		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define WL2868C_LDO6_OCP_CTL		0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define WL2868C_LDO7_STATUS		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define WL2868C_LDO7_OCP_CTL		0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define WL2868C_REPROGRAMMABLE_I2C_ADDR	0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define RESERVED_1			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define INT_LATCHED_CLR			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define INT_EN_SET			0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define INT_LATCHED_STS			0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define INT_PENDING_STS			0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define UVLO_CTL			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define RESERVED_2			0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define WL2868C_VSEL_MASK		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) enum wl2868c_regulators {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	WL2868C_REGULATOR_LDO1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	WL2868C_REGULATOR_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	WL2868C_REGULATOR_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	WL2868C_REGULATOR_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	WL2868C_REGULATOR_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	WL2868C_REGULATOR_LDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	WL2868C_REGULATOR_LDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	WL2868C_MAX_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) struct wl2868c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int min_dropout_uv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int ldo_vout[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int ldo_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) static const struct regulator_ops wl2868c_reg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.list_voltage		= regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.map_voltage		= regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	.enable			= regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.disable		= regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.is_enabled		= regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define WL2868C_DESC(_id, _match, _supply, _min, _max, _step, _vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	_vmask, _ereg, _emask, _enval, _disval)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.name		= (_match),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.supply_name	= (_supply),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.of_match	= of_match_ptr(_match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.regulators_node = of_match_ptr("regulators"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.type		= REGULATOR_VOLTAGE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.id		= (_id),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.n_voltages	= (((_max) - (_min)) / (_step) + 1),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.owner		= THIS_MODULE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.min_uV		= (_min) * 1000,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.uV_step	= (_step) * 1000,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.vsel_reg	= (_vreg),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.vsel_mask	= (_vmask),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.enable_reg	= (_ereg),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.enable_mask	= (_emask),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.enable_val     = (_enval),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.disable_val     = (_disval),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.ops		= &wl2868c_reg_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const struct regulator_desc wl2868c_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	WL2868C_DESC(WL2868C_REGULATOR_LDO1, "WL_LDO1", "ldo1", 496, 2536, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		     WL2868C_LDO1_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(0), BIT(0), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	WL2868C_DESC(WL2868C_REGULATOR_LDO2, "WL_LDO2", "ldo2", 496, 2536, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		     WL2868C_LDO2_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(1), BIT(1), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	WL2868C_DESC(WL2868C_REGULATOR_LDO3, "WL_LDO3", "ldo3", 1504, 3544, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		     WL2868C_LDO3_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(2), BIT(2), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	WL2868C_DESC(WL2868C_REGULATOR_LDO4, "WL_LDO4", "ldo4", 1504, 3544, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		     WL2868C_LDO4_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(3), BIT(3), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	WL2868C_DESC(WL2868C_REGULATOR_LDO5, "WL_LDO5", "ldo5", 1504, 3544, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		     WL2868C_LDO5_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(4), BIT(4), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	WL2868C_DESC(WL2868C_REGULATOR_LDO6, "WL_LDO6", "ldo6", 1504, 3544, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		     WL2868C_LDO6_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(5), BIT(5), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	WL2868C_DESC(WL2868C_REGULATOR_LDO7, "WL_LDO7", "ldo7", 1504, 3544, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		     WL2868C_LDO7_VOUT, WL2868C_VSEL_MASK, WL2868C_LDO_EN, BIT(6), BIT(6), 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct regmap_range wl2868c_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	regmap_reg_range(WL2868C_DISCHARGE_RESISTORS, WL2868C_SEQ_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	regmap_reg_range(WL2868C_LDO1_OCP_CTL, WL2868C_LDO1_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	regmap_reg_range(WL2868C_LDO2_OCP_CTL, WL2868C_LDO2_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	regmap_reg_range(WL2868C_LDO3_OCP_CTL, WL2868C_LDO3_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	regmap_reg_range(WL2868C_LDO4_OCP_CTL, WL2868C_LDO4_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	regmap_reg_range(WL2868C_LDO5_OCP_CTL, WL2868C_LDO5_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	regmap_reg_range(WL2868C_LDO6_OCP_CTL, WL2868C_LDO6_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	regmap_reg_range(WL2868C_LDO7_OCP_CTL, WL2868C_REPROGRAMMABLE_I2C_ADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	regmap_reg_range(INT_LATCHED_CLR, INT_LATCHED_CLR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	regmap_reg_range(INT_EN_SET, INT_EN_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	regmap_reg_range(UVLO_CTL, UVLO_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct regmap_range wl2868c_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	regmap_reg_range(WL2868C_DEVICE_D1, RESERVED_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct regmap_range wl2868c_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	regmap_reg_range(WL2868C_DISCHARGE_RESISTORS, WL2868C_SEQ_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	regmap_reg_range(WL2868C_LDO1_OCP_CTL, WL2868C_LDO1_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	regmap_reg_range(WL2868C_LDO2_OCP_CTL, WL2868C_LDO2_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	regmap_reg_range(WL2868C_LDO3_OCP_CTL, WL2868C_LDO3_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	regmap_reg_range(WL2868C_LDO4_OCP_CTL, WL2868C_LDO4_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	regmap_reg_range(WL2868C_LDO5_OCP_CTL, WL2868C_LDO5_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	regmap_reg_range(WL2868C_LDO6_OCP_CTL, WL2868C_LDO6_OCP_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	regmap_reg_range(WL2868C_LDO7_OCP_CTL, WL2868C_REPROGRAMMABLE_I2C_ADDR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	regmap_reg_range(INT_LATCHED_CLR, INT_LATCHED_CLR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	regmap_reg_range(INT_EN_SET, INT_EN_SET),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	regmap_reg_range(UVLO_CTL, UVLO_CTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct regmap_access_table wl2868c_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.yes_ranges   = wl2868c_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.n_yes_ranges = ARRAY_SIZE(wl2868c_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct regmap_access_table wl2868c_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.yes_ranges   = wl2868c_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	.n_yes_ranges = ARRAY_SIZE(wl2868c_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct regmap_access_table wl2868c_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.yes_ranges   = wl2868c_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.n_yes_ranges = ARRAY_SIZE(wl2868c_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct regmap_config wl2868c_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.max_register = RESERVED_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.wr_table = &wl2868c_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.rd_table = &wl2868c_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.volatile_table = &wl2868c_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void wl2868c_reset(struct wl2868c *wl2868c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	gpiod_set_value_cansleep(wl2868c->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	gpiod_set_value_cansleep(wl2868c->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	gpiod_set_value_cansleep(wl2868c->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	usleep_range(10000, 11000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static int wl2868c_i2c_probe(struct i2c_client *client, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	const struct regulator_desc *regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	struct wl2868c *wl2868c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	wl2868c = devm_kzalloc(dev, sizeof(struct wl2868c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	if (!wl2868c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	wl2868c->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	if (IS_ERR(wl2868c->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		ret = PTR_ERR(wl2868c->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		dev_err(dev, "failed to request reset GPIO: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	wl2868c_reset(wl2868c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	i2c_set_clientdata(client, wl2868c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	wl2868c->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	wl2868c->regmap = devm_regmap_init_i2c(client, &wl2868c_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	if (IS_ERR(wl2868c->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		ret = PTR_ERR(wl2868c->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(dev, "Failed to allocate register map: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	config.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	config.regmap = wl2868c->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	regulators = wl2868c_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	/* Instantiate the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	for (i = 0; i < WL2868C_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		rdev = devm_regulator_register(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 					       &regulators[i], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 			dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 				"failed to register %d regulator\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static void wl2868c_regulator_shutdown(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	struct wl2868c *wl2868c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (system_state == SYSTEM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		regmap_write(wl2868c->regmap, WL2868C_LDO_EN, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int __maybe_unused wl2868c_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	struct wl2868c *wl2868c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	regmap_read(wl2868c->regmap, WL2868C_LDO_EN, &wl2868c->ldo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	for (i = 0; i < ARRAY_SIZE(wl2868c->ldo_vout); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		regmap_read(wl2868c->regmap, WL2868C_LDO1_VOUT + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 			    &wl2868c->ldo_vout[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int __maybe_unused wl2868c_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct wl2868c *wl2868c = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	wl2868c_reset(wl2868c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	for (i = 0; i < ARRAY_SIZE(wl2868c->ldo_vout); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		regmap_write(wl2868c->regmap, WL2868C_LDO1_VOUT + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			     wl2868c->ldo_vout[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	regmap_write(wl2868c->regmap, WL2868C_LDO_EN, wl2868c->ldo_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static SIMPLE_DEV_PM_OPS(wl2868c_pm_ops, wl2868c_suspend, wl2868c_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static const struct i2c_device_id wl2868c_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	{ "wl2868c", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MODULE_DEVICE_TABLE(i2c, wl2868c_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static const struct of_device_id wl2868c_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{ .compatible = "willsemi,wl2868c" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MODULE_DEVICE_TABLE(of, wl2868c_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static struct i2c_driver wl2868c_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.name = "wl2868c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.of_match_table = of_match_ptr(wl2868c_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.pm = &wl2868c_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.id_table = wl2868c_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.probe	= wl2868c_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.shutdown = wl2868c_regulator_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) module_i2c_driver(wl2868c_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) MODULE_DESCRIPTION("WL2868C regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) MODULE_AUTHOR("Shunqing Chen <csq@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MODULE_LICENSE("GPL");