^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Split TWL6030 logic from twl-regulator.c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2008 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2016 Nicolae Rosia <nicolae.rosia@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) struct twlreg_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* start of regulator's PM_RECEIVER control register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* twl resource ID, for resource control state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* used by regulator core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* chip specific features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) unsigned long features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* data passed from board for external get/set voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* LDO control registers ... offset is from the base of its register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * The first three registers of all power resource banks help hardware to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * manage the various resource groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Common offset in TWL4030/6030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define VREG_GRP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* TWL6030 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VREG_TRANS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VREG_STATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define VREG_VOLTAGE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define VREG_VOLTAGE_SMPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* TWL6030 Misc register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VREG_BC_ALL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VREG_BC_REF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VREG_BC_PROC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VREG_BC_CLK_RST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* TWL6030 LDO register values for VREG_VOLTAGE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TWL6030_VREG_VOLTAGE_WR_S BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* TWL6030 LDO register values for CFG_STATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TWL6030_CFG_STATE_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TWL6030_CFG_STATE_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TWL6030_CFG_STATE_OFF2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TWL6030_CFG_STATE_SLEEP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TWL6030_CFG_STATE_GRP_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TWL6030_CFG_STATE_APP_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TWL6030_CFG_STATE_APP_MASK (0x03 << TWL6030_CFG_STATE_APP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TWL6030_CFG_STATE_APP(v) (((v) & TWL6030_CFG_STATE_APP_MASK) >>\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) TWL6030_CFG_STATE_APP_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Flags for SMPS Voltage reading and LDO reading*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SMPS_OFFSET_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SMPS_EXTENDED_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TWL_6030_WARM_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* twl6032 SMPS EPROM values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TWL6030_SMPS_OFFSET 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TWL6030_SMPS_MULT 0xB3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SMPS_MULTOFFSET_SMPS4 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SMPS_MULTOFFSET_VIO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SMPS_MULTOFFSET_SMPS3 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) status = twl_i2c_read_u8(slave_subgp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) &value, info->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return (status < 0) ? status : value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return twl_i2c_write_u8(slave_subgp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) value, info->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* generic power resource operations, which work on all regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int twlreg_grp(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) VREG_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * Enable/disable regulators by joining/leaving the P1 (processor) group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * We assume nobody else is updating the DEV_GRP registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* definition for 6030 family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define P2_GRP_6030 BIT(1) /* "peripherals" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define P1_GRP_6030 BIT(0) /* CPU/Linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static int twl6030reg_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int grp = 0, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) grp = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) if (grp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) grp &= P1_GRP_6030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) grp = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) val = TWL6030_CFG_STATE_APP(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return grp && (val == TWL6030_CFG_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PB_I2C_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PB_I2C_BWEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int twl6030reg_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int grp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) grp = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (grp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) grp << TWL6030_CFG_STATE_GRP_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) TWL6030_CFG_STATE_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int twl6030reg_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int grp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) grp = P1_GRP_6030 | P2_GRP_6030 | P3_GRP_6030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* For 6030, set the off state for all grps enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (grp) << TWL6030_CFG_STATE_GRP_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) TWL6030_CFG_STATE_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int twl6030reg_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) val = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (TWL6030_CFG_STATE_APP(val)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case TWL6030_CFG_STATE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return REGULATOR_STATUS_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case TWL6030_CFG_STATE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return REGULATOR_STATUS_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case TWL6030_CFG_STATE_OFF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) case TWL6030_CFG_STATE_OFF2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) static int twl6030reg_set_mode(struct regulator_dev *rdev, unsigned mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) int grp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (!(twl_class_is_6030() && (info->features & TWL6032_SUBCLASS)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) grp = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (grp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Compose the state register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val = grp << TWL6030_CFG_STATE_GRP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* We can only set the mode through state machine commands... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) val |= TWL6030_CFG_STATE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val |= TWL6030_CFG_STATE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_STATE, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int twl6030coresmps_set_voltage(struct regulator_dev *rdev, int min_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int max_uV, unsigned *selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int twl6030coresmps_get_voltage(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct regulator_ops twl6030coresmps_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .set_voltage = twl6030coresmps_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .get_voltage = twl6030coresmps_get_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) twl6030ldo_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if (info->flags & TWL_6030_WARM_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) selector |= TWL6030_VREG_VOLTAGE_WR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int twl6030ldo_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (info->flags & TWL_6030_WARM_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) vsel &= ~TWL6030_VREG_VOLTAGE_WR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct regulator_ops twl6030ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .set_voltage_sel = twl6030ldo_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .get_voltage_sel = twl6030ldo_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .enable = twl6030reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .disable = twl6030reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .is_enabled = twl6030reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .set_mode = twl6030reg_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .get_status = twl6030reg_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static const struct regulator_ops twl6030fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .enable = twl6030reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .disable = twl6030reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .is_enabled = twl6030reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .set_mode = twl6030reg_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .get_status = twl6030reg_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * SMPS status and control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int twl6030smps_list_voltage(struct regulator_dev *rdev, unsigned index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int voltage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (info->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case SMPS_OFFSET_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) voltage = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) voltage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) case 58:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) voltage = 1350 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) case 59:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) voltage = 1500 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case 60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) voltage = 1800 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) case 61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) voltage = 1900 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case 62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) voltage = 2100 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) voltage += (600000 + (12500 * (index - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case SMPS_EXTENDED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) voltage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case 58:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) voltage = 2084 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) case 59:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) voltage = 2315 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case 60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) voltage = 2778 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case 61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) voltage = 2932 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) case 62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) voltage = 3241 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) voltage = (1852000 + (38600 * (index - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case SMPS_OFFSET_EN | SMPS_EXTENDED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) voltage = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case 58:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) voltage = 4167 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) case 59:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) voltage = 2315 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case 60:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) voltage = 2778 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) case 61:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) voltage = 2932 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case 62:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) voltage = 3241 * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) voltage = (2161000 + (38600 * (index - 1)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return voltage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int twl6030smps_map_voltage(struct regulator_dev *rdev, int min_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int vsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) switch (info->flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (min_uV == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) vsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else if ((min_uV >= 600000) && (min_uV <= 1300000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) vsel = DIV_ROUND_UP(min_uV - 600000, 12500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) vsel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Values 1..57 for vsel are linear and can be calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * values 58..62 are non linear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) else if ((min_uV > 1900000) && (min_uV <= 2100000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) vsel = 62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) else if ((min_uV > 1800000) && (min_uV <= 1900000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) vsel = 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) else if ((min_uV > 1500000) && (min_uV <= 1800000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) vsel = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) else if ((min_uV > 1350000) && (min_uV <= 1500000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) vsel = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) else if ((min_uV > 1300000) && (min_uV <= 1350000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) vsel = 58;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) case SMPS_OFFSET_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (min_uV == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) vsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) else if ((min_uV >= 700000) && (min_uV <= 1420000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) vsel = DIV_ROUND_UP(min_uV - 700000, 12500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) vsel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Values 1..57 for vsel are linear and can be calculated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * values 58..62 are non linear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else if ((min_uV > 1900000) && (min_uV <= 2100000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) vsel = 62;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) else if ((min_uV > 1800000) && (min_uV <= 1900000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) vsel = 61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) else if ((min_uV > 1500000) && (min_uV <= 1800000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) vsel = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) else if ((min_uV > 1350000) && (min_uV <= 1500000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) vsel = 59;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case SMPS_EXTENDED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (min_uV == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) vsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) } else if ((min_uV >= 1852000) && (max_uV <= 4013600)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) vsel = DIV_ROUND_UP(min_uV - 1852000, 38600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) vsel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) case SMPS_OFFSET_EN|SMPS_EXTENDED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (min_uV == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) vsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else if ((min_uV >= 2161000) && (min_uV <= 4321000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) vsel = DIV_ROUND_UP(min_uV - 2161000, 38600);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) vsel++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int twl6030smps_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE_SMPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int twl6030smps_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE_SMPS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const struct regulator_ops twlsmps_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .list_voltage = twl6030smps_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .map_voltage = twl6030smps_map_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .set_voltage_sel = twl6030smps_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .get_voltage_sel = twl6030smps_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .enable = twl6030reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .disable = twl6030reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .is_enabled = twl6030reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .set_mode = twl6030reg_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .get_status = twl6030reg_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct linear_range twl6030ldo_linear_range[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) REGULATOR_LINEAR_RANGE(0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) REGULATOR_LINEAR_RANGE(1000000, 1, 24, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) REGULATOR_LINEAR_RANGE(2750000, 31, 31, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define TWL6030_ADJUSTABLE_SMPS(label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static const struct twlreg_info TWL6030_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .id = TWL6030_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .ops = &twl6030coresmps_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define TWL6030_ADJUSTABLE_LDO(label, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static const struct twlreg_info TWL6030_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .id = TWL6030_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .n_voltages = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .linear_ranges = twl6030ldo_linear_range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .n_linear_ranges = ARRAY_SIZE(twl6030ldo_linear_range), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .ops = &twl6030ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define TWL6032_ADJUSTABLE_LDO(label, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct twlreg_info TWL6032_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .id = TWL6032_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .n_voltages = 32, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .linear_ranges = twl6030ldo_linear_range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .n_linear_ranges = ARRAY_SIZE(twl6030ldo_linear_range), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .ops = &twl6030ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define TWL6030_FIXED_LDO(label, offset, mVolts, turnon_delay) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct twlreg_info TWLFIXED_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .id = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .id = TWL6030##_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ops = &twl6030fixed_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .min_uV = mVolts * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .enable_time = turnon_delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .of_map_mode = NULL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define TWL6032_ADJUSTABLE_SMPS(label, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static const struct twlreg_info TWLSMPS_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .id = TWL6032_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .n_voltages = 63, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .ops = &twlsmps_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* VUSBCP is managed *only* by the USB subchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* 6030 REG with base as PMC Slave Misc : 0x0030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Turnon-delay and remap configuration values for 6030 are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) verified since the specification is not public */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) TWL6030_ADJUSTABLE_SMPS(VDD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) TWL6030_ADJUSTABLE_SMPS(VDD2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) TWL6030_ADJUSTABLE_SMPS(VDD3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) TWL6030_ADJUSTABLE_LDO(VAUX1_6030, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) TWL6030_ADJUSTABLE_LDO(VAUX2_6030, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) TWL6030_ADJUSTABLE_LDO(VAUX3_6030, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) TWL6030_ADJUSTABLE_LDO(VMMC, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) TWL6030_ADJUSTABLE_LDO(VPP, 0x6c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) TWL6030_ADJUSTABLE_LDO(VUSIM, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* 6025 are renamed compared to 6030 versions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) TWL6032_ADJUSTABLE_LDO(LDO2, 0x54);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) TWL6032_ADJUSTABLE_LDO(LDO4, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) TWL6032_ADJUSTABLE_LDO(LDO3, 0x5c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) TWL6032_ADJUSTABLE_LDO(LDO5, 0x68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) TWL6032_ADJUSTABLE_LDO(LDO1, 0x6c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) TWL6032_ADJUSTABLE_LDO(LDO7, 0x74);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) TWL6032_ADJUSTABLE_LDO(LDO6, 0x60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) TWL6032_ADJUSTABLE_LDO(LDOLN, 0x64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) TWL6032_ADJUSTABLE_LDO(LDOUSB, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) TWL6030_FIXED_LDO(VANA, 0x50, 2100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) TWL6030_FIXED_LDO(VCXIO, 0x60, 1800, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) TWL6030_FIXED_LDO(VDAC, 0x64, 1800, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) TWL6030_FIXED_LDO(VUSB, 0x70, 3300, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) TWL6030_FIXED_LDO(V1V8, 0x16, 1800, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) TWL6030_FIXED_LDO(V2V1, 0x1c, 2100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) TWL6032_ADJUSTABLE_SMPS(SMPS3, 0x34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) TWL6032_ADJUSTABLE_SMPS(SMPS4, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) TWL6032_ADJUSTABLE_SMPS(VIO, 0x16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static u8 twl_get_smps_offset(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) TWL6030_SMPS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static u8 twl_get_smps_mult(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) twl_i2c_read_u8(TWL_MODULE_PM_RECEIVER, &value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) TWL6030_SMPS_MULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define TWL_OF_MATCH(comp, family, label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .compatible = comp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .data = &family##_INFO_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define TWL6030_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6030, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define TWL6032_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6032, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define TWLFIXED_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLFIXED, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TWLSMPS_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLSMPS, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static const struct of_device_id twl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) TWL6030_OF_MATCH("ti,twl6030-vdd1", VDD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) TWL6030_OF_MATCH("ti,twl6030-vdd2", VDD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) TWL6030_OF_MATCH("ti,twl6030-vdd3", VDD3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) TWL6030_OF_MATCH("ti,twl6030-vaux1", VAUX1_6030),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) TWL6030_OF_MATCH("ti,twl6030-vaux2", VAUX2_6030),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) TWL6030_OF_MATCH("ti,twl6030-vaux3", VAUX3_6030),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) TWL6030_OF_MATCH("ti,twl6030-vmmc", VMMC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) TWL6030_OF_MATCH("ti,twl6030-vpp", VPP),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) TWL6030_OF_MATCH("ti,twl6030-vusim", VUSIM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) TWL6032_OF_MATCH("ti,twl6032-ldo2", LDO2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) TWL6032_OF_MATCH("ti,twl6032-ldo4", LDO4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) TWL6032_OF_MATCH("ti,twl6032-ldo3", LDO3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) TWL6032_OF_MATCH("ti,twl6032-ldo5", LDO5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) TWL6032_OF_MATCH("ti,twl6032-ldo1", LDO1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) TWL6032_OF_MATCH("ti,twl6032-ldo7", LDO7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) TWL6032_OF_MATCH("ti,twl6032-ldo6", LDO6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) TWL6032_OF_MATCH("ti,twl6032-ldoln", LDOLN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) TWL6032_OF_MATCH("ti,twl6032-ldousb", LDOUSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) TWLFIXED_OF_MATCH("ti,twl6030-vana", VANA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) TWLFIXED_OF_MATCH("ti,twl6030-vcxio", VCXIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) TWLFIXED_OF_MATCH("ti,twl6030-vdac", VDAC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) TWLFIXED_OF_MATCH("ti,twl6030-vusb", VUSB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) TWLFIXED_OF_MATCH("ti,twl6030-v1v8", V1V8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) TWLFIXED_OF_MATCH("ti,twl6030-v2v1", V2V1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) TWLSMPS_OF_MATCH("ti,twl6032-smps3", SMPS3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) TWLSMPS_OF_MATCH("ti,twl6032-smps4", SMPS4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) TWLSMPS_OF_MATCH("ti,twl6032-vio", VIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) MODULE_DEVICE_TABLE(of, twl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int twlreg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct twlreg_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) const struct twlreg_info *template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct regulator_init_data *initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct regulation_constraints *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) template = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) id = template->desc.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) initdata = of_get_regulator_init_data(&pdev->dev, np, &template->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (!initdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) info = devm_kmemdup(&pdev->dev, template, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /* Constrain board-specific capabilities according to what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) * this driver and the chip itself can actually do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) c = &initdata->constraints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) c->valid_modes_mask &= REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) c->valid_ops_mask &= REGULATOR_CHANGE_VOLTAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) | REGULATOR_CHANGE_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) | REGULATOR_CHANGE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case TWL6032_REG_SMPS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (twl_get_smps_mult() & SMPS_MULTOFFSET_SMPS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) info->flags |= SMPS_EXTENDED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (twl_get_smps_offset() & SMPS_MULTOFFSET_SMPS3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) info->flags |= SMPS_OFFSET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case TWL6032_REG_SMPS4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (twl_get_smps_mult() & SMPS_MULTOFFSET_SMPS4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) info->flags |= SMPS_EXTENDED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (twl_get_smps_offset() & SMPS_MULTOFFSET_SMPS4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) info->flags |= SMPS_OFFSET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) case TWL6032_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (twl_get_smps_mult() & SMPS_MULTOFFSET_VIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) info->flags |= SMPS_EXTENDED_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (twl_get_smps_offset() & SMPS_MULTOFFSET_VIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) info->flags |= SMPS_OFFSET_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (of_get_property(np, "ti,retain-on-reset", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) info->flags |= TWL_6030_WARM_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) config.init_data = initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) config.driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) config.of_node = np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) dev_err(&pdev->dev, "can't register %s, %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) info->desc.name, PTR_ERR(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) platform_set_drvdata(pdev, rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* NOTE: many regulators support short-circuit IRQs (presentable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * as REGULATOR_OVER_CURRENT notifications?) configured via:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * - SC_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * - SC_DETECT2 (vusb, vdac, vio, vdd1/2, vpll2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * - IT_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_ALIAS("platform:twl6030_reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static struct platform_driver twlreg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .probe = twlreg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* NOTE: short name, to work around driver model truncation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * "twl_regulator.12" (and friends) to "twl_regulator.1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .name = "twl6030_reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .of_match_table = of_match_ptr(twl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static int __init twlreg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) return platform_driver_register(&twlreg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) subsys_initcall(twlreg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static void __exit twlreg_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) platform_driver_unregister(&twlreg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) module_exit(twlreg_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) MODULE_DESCRIPTION("TWL6030 regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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