^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * twl-regulator.c -- support regulators in twl4030/twl6030 family chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2008 David Brownell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/twl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The TWL4030/TW5030/TPS659x0 family chips include power management, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * USB OTG transceiver, an RTC, ADC, PWM, and lots more. Some versions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * include an audio codec, battery charger, and more voltage regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * These chips are often used in OMAP-based systems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * This driver implements software-based resource control for various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * voltage regulators. This is usually augmented with state machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * based control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct twlreg_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* start of regulator's PM_RECEIVER control register bank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* twl resource ID, for resource control state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* voltage in mV = table[VSEL]; table_len must be a power-of-two */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u8 table_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) const u16 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* State REMAP default configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u8 remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* used by regulator core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* chip specific features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned long features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* data passed from board for external get/set voltage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* LDO control registers ... offset is from the base of its register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * The first three registers of all power resource banks help hardware to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * manage the various resource groups.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Common offset in TWL4030/6030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define VREG_GRP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* TWL4030 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VREG_TYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VREG_REMAP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VREG_DEDICATED 3 /* LDO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VREG_VOLTAGE_SMPS_4030 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* TWL6030 register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VREG_TRANS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define VREG_STATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define VREG_VOLTAGE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define VREG_VOLTAGE_SMPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) twlreg_read(struct twlreg_info *info, unsigned slave_subgp, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u8 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) status = twl_i2c_read_u8(slave_subgp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) &value, info->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return (status < 0) ? status : value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static inline int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) twlreg_write(struct twlreg_info *info, unsigned slave_subgp, unsigned offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) return twl_i2c_write_u8(slave_subgp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) value, info->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* generic power resource operations, which work on all regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static int twlreg_grp(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return twlreg_read(rdev_get_drvdata(rdev), TWL_MODULE_PM_RECEIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) VREG_GRP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * Enable/disable regulators by joining/leaving the P1 (processor) group.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * We assume nobody else is updating the DEV_GRP registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* definition for 4030 family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define P3_GRP_4030 BIT(7) /* "peripherals" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define P2_GRP_4030 BIT(6) /* secondary processor, modem, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define P1_GRP_4030 BIT(5) /* CPU/Linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* definition for 6030 family */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define P3_GRP_6030 BIT(2) /* secondary processor, modem, etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define P2_GRP_6030 BIT(1) /* "peripherals" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define P1_GRP_6030 BIT(0) /* CPU/Linux */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int twl4030reg_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int state = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (state < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return state & P1_GRP_4030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PB_I2C_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PB_I2C_BWEN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Wait until buffer empty/ready to send a word on power bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int twl4030_wait_pb_ready(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int timeout = 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ret = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) TWL4030_PM_MASTER_PB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (!(val & PB_I2C_BUSY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) timeout--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) } while (timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* Send a word over the powerbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static int twl4030_send_pb_msg(unsigned msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* save powerbus configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = twl_i2c_read_u8(TWL_MODULE_PM_MASTER, &val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) TWL4030_PM_MASTER_PB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Enable i2c access to powerbus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val | PB_I2C_BWEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) TWL4030_PM_MASTER_PB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = twl4030_wait_pb_ready();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, msg >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) TWL4030_PM_MASTER_PB_WORD_MSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ret = twl_i2c_write_u8(TWL_MODULE_PM_MASTER, msg & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) TWL4030_PM_MASTER_PB_WORD_LSB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) ret = twl4030_wait_pb_ready();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Restore powerbus configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return twl_i2c_write_u8(TWL_MODULE_PM_MASTER, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) TWL4030_PM_MASTER_PB_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int twl4030reg_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) grp = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (grp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) grp |= P1_GRP_4030;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static int twl4030reg_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) grp = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (grp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return grp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) grp &= ~(P1_GRP_4030 | P2_GRP_4030 | P3_GRP_4030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ret = twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_GRP, grp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int twl4030reg_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int state = twlreg_grp(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (state < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) state &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* assume state != WARM_RESET; we'd not be running... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return (state & BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ? REGULATOR_STATUS_NORMAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) : REGULATOR_STATUS_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static int twl4030reg_set_mode(struct regulator_dev *rdev, unsigned mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) unsigned message;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* We can only set the mode through state machine commands... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) message = MSG_SINGULAR(DEV_GRP_P1, info->id, RES_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return twl4030_send_pb_msg(message);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static inline unsigned int twl4030reg_map_mode(unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case RES_STATE_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case RES_STATE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return REGULATOR_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Support for adjustable-voltage LDOs uses a four bit (or less) voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * select field in its control register. We use tables indexed by VSEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * to record voltages in milliVolts. (Accuracy is about three percent.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Note that VSEL values for VAUX2 changed in twl5030 and newer silicon;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * currently handled by listing two slightly different VAUX2 regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * only one of which will be configured.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * VSEL values documented as "TI cannot support these values" are flagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * in these tables as UNSUP() values; we normally won't assign them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * VAUX3 at 3V is incorrectly listed in some TI manuals as unsupported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * TI are revising the twl5030/tps659x0 specs to support that 3.0V setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define UNSUP_MASK 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define UNSUP(x) (UNSUP_MASK | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IS_UNSUP(info, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ((UNSUP_MASK & (x)) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) !((info)->features & TWL4030_ALLOW_UNSUPPORTED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define LDO_MV(x) (~UNSUP_MASK & (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const u16 VAUX1_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) UNSUP(1500), UNSUP(1800), 2500, 2800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 3000, 3000, 3000, 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const u16 VAUX2_4030_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) UNSUP(1000), UNSUP(1000), UNSUP(1200), 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 1500, 1800, UNSUP(1850), 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static const u16 VAUX2_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 1700, 1700, 1900, 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 1500, 1800, 2000, 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 2100, 2800, 2200, 2300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 2400, 2400, 2400, 2400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const u16 VAUX3_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 1500, 1800, 2500, 2800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 3000, 3000, 3000, 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const u16 VAUX4_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 700, 1000, 1200, UNSUP(1300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 1500, 1800, UNSUP(1850), 2500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) UNSUP(2600), 2800, UNSUP(2850), UNSUP(3000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const u16 VMMC1_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 1850, 2850, 3000, 3150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const u16 VMMC2_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) UNSUP(1000), UNSUP(1000), UNSUP(1200), UNSUP(1300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) UNSUP(1500), UNSUP(1800), 1850, UNSUP(2500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 2600, 2800, 2850, 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 3150, 3150, 3150, 3150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const u16 VPLL1_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 1000, 1200, 1300, 1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) UNSUP(2800), UNSUP(3000), UNSUP(3000), UNSUP(3000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const u16 VPLL2_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 700, 1000, 1200, 1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) UNSUP(1500), 1800, UNSUP(1850), UNSUP(2500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) UNSUP(2600), UNSUP(2800), UNSUP(2850), UNSUP(3000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) UNSUP(3150), UNSUP(3150), UNSUP(3150), UNSUP(3150),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static const u16 VSIM_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) UNSUP(1000), UNSUP(1200), UNSUP(1300), 1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 2800, 3000, 3000, 3000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static const u16 VDAC_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 1200, 1300, 1800, 1800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const u16 VIO_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 1800, 1850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const u16 VINTANA2_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 2500, 2750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* 600mV to 1450mV in 12.5 mV steps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const struct linear_range VDD1_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) REGULATOR_LINEAR_RANGE(600000, 0, 68, 12500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* 600mV to 1450mV in 12.5 mV steps, everything above = 1500mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static const struct linear_range VDD2_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) REGULATOR_LINEAR_RANGE(600000, 0, 68, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) REGULATOR_LINEAR_RANGE(1500000, 69, 69, 12500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int twl4030ldo_list_voltage(struct regulator_dev *rdev, unsigned index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int mV = info->table[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return IS_UNSUP(info, mV) ? 0 : (LDO_MV(mV) * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) twl4030ldo_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int twl4030ldo_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (vsel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) vsel &= info->table_len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static const struct regulator_ops twl4030ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .list_voltage = twl4030ldo_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .set_voltage_sel = twl4030ldo_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .get_voltage_sel = twl4030ldo_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .enable = twl4030reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .disable = twl4030reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .is_enabled = twl4030reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .set_mode = twl4030reg_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .get_status = twl4030reg_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) twl4030smps_set_voltage(struct regulator_dev *rdev, int min_uV, int max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned *selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int vsel = DIV_ROUND_UP(min_uV - 600000, 12500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_VOLTAGE_SMPS_4030, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int twl4030smps_get_voltage(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct twlreg_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) vsel = twlreg_read(info, TWL_MODULE_PM_RECEIVER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) VREG_VOLTAGE_SMPS_4030);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return vsel * 12500 + 600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct regulator_ops twl4030smps_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .set_voltage = twl4030smps_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .get_voltage = twl4030smps_get_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct regulator_ops twl4030fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .enable = twl4030reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .disable = twl4030reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .is_enabled = twl4030reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .set_mode = twl4030reg_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .get_status = twl4030reg_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /*----------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define TWL4030_ADJUSTABLE_LDO(label, offset, num, turnon_delay, remap_conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static const struct twlreg_info TWL4030_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .id = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .table_len = ARRAY_SIZE(label##_VSEL_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .table = label##_VSEL_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .remap = remap_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .id = TWL4030_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .n_voltages = ARRAY_SIZE(label##_VSEL_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .ops = &twl4030ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .enable_time = turnon_delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .of_map_mode = twl4030reg_map_mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define TWL4030_ADJUSTABLE_SMPS(label, offset, num, turnon_delay, remap_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) n_volt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static const struct twlreg_info TWL4030_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .id = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .remap = remap_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .id = TWL4030_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .ops = &twl4030smps_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .enable_time = turnon_delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .of_map_mode = twl4030reg_map_mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .n_voltages = n_volt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .n_linear_ranges = ARRAY_SIZE(label ## _ranges), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .linear_ranges = label ## _ranges, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define TWL4030_FIXED_LDO(label, offset, mVolts, num, turnon_delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) remap_conf) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct twlreg_info TWLFIXED_INFO_##label = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .base = offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .id = num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .remap = remap_conf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .name = #label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .id = TWL4030##_REG_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .ops = &twl4030fixed_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .min_uV = mVolts * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .enable_time = turnon_delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .of_map_mode = twl4030reg_map_mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * We list regulators here if systems need some level of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * software control over them after boot.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) TWL4030_ADJUSTABLE_LDO(VAUX1, 0x17, 1, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) TWL4030_ADJUSTABLE_LDO(VAUX2_4030, 0x1b, 2, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) TWL4030_ADJUSTABLE_LDO(VAUX2, 0x1b, 2, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) TWL4030_ADJUSTABLE_LDO(VAUX3, 0x1f, 3, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) TWL4030_ADJUSTABLE_LDO(VAUX4, 0x23, 4, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) TWL4030_ADJUSTABLE_LDO(VMMC1, 0x27, 5, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) TWL4030_ADJUSTABLE_LDO(VMMC2, 0x2b, 6, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) TWL4030_ADJUSTABLE_LDO(VPLL1, 0x2f, 7, 100, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) TWL4030_ADJUSTABLE_LDO(VPLL2, 0x33, 8, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) TWL4030_ADJUSTABLE_LDO(VSIM, 0x37, 9, 100, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) TWL4030_ADJUSTABLE_LDO(VDAC, 0x3b, 10, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) TWL4030_ADJUSTABLE_LDO(VINTANA2, 0x43, 12, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) TWL4030_ADJUSTABLE_LDO(VIO, 0x4b, 14, 1000, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) TWL4030_ADJUSTABLE_SMPS(VDD1, 0x55, 15, 1000, 0x08, 68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) TWL4030_ADJUSTABLE_SMPS(VDD2, 0x63, 16, 1000, 0x08, 69);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* VUSBCP is managed *only* by the USB subchip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TWL4030_FIXED_LDO(VINTANA1, 0x3f, 1500, 11, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) TWL4030_FIXED_LDO(VINTDIG, 0x47, 1500, 13, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) TWL4030_FIXED_LDO(VUSB1V5, 0x71, 1500, 17, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) TWL4030_FIXED_LDO(VUSB1V8, 0x74, 1800, 18, 100, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) TWL4030_FIXED_LDO(VUSB3V1, 0x77, 3100, 19, 150, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define TWL_OF_MATCH(comp, family, label) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .compatible = comp, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .data = &family##_INFO_##label, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define TWL4030_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL4030, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define TWL6030_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6030, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define TWL6032_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWL6032, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define TWLFIXED_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLFIXED, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define TWLSMPS_OF_MATCH(comp, label) TWL_OF_MATCH(comp, TWLSMPS, label)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static const struct of_device_id twl_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) TWL4030_OF_MATCH("ti,twl4030-vaux1", VAUX1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) TWL4030_OF_MATCH("ti,twl4030-vaux2", VAUX2_4030),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) TWL4030_OF_MATCH("ti,twl5030-vaux2", VAUX2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) TWL4030_OF_MATCH("ti,twl4030-vaux3", VAUX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) TWL4030_OF_MATCH("ti,twl4030-vaux4", VAUX4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) TWL4030_OF_MATCH("ti,twl4030-vmmc1", VMMC1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) TWL4030_OF_MATCH("ti,twl4030-vmmc2", VMMC2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) TWL4030_OF_MATCH("ti,twl4030-vpll1", VPLL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) TWL4030_OF_MATCH("ti,twl4030-vpll2", VPLL2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) TWL4030_OF_MATCH("ti,twl4030-vsim", VSIM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) TWL4030_OF_MATCH("ti,twl4030-vdac", VDAC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) TWL4030_OF_MATCH("ti,twl4030-vintana2", VINTANA2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) TWL4030_OF_MATCH("ti,twl4030-vio", VIO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) TWL4030_OF_MATCH("ti,twl4030-vdd1", VDD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) TWL4030_OF_MATCH("ti,twl4030-vdd2", VDD2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) TWLFIXED_OF_MATCH("ti,twl4030-vintana1", VINTANA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) TWLFIXED_OF_MATCH("ti,twl4030-vintdig", VINTDIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) TWLFIXED_OF_MATCH("ti,twl4030-vusb1v5", VUSB1V5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) TWLFIXED_OF_MATCH("ti,twl4030-vusb1v8", VUSB1V8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) TWLFIXED_OF_MATCH("ti,twl4030-vusb3v1", VUSB3V1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MODULE_DEVICE_TABLE(of, twl_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int twlreg_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct twlreg_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) const struct twlreg_info *template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct regulator_init_data *initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct regulation_constraints *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) template = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) id = template->desc.id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) initdata = of_get_regulator_init_data(&pdev->dev, pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) &template->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!initdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) info = devm_kmemdup(&pdev->dev, template, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Constrain board-specific capabilities according to what
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * this driver and the chip itself can actually do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) c = &initdata->constraints;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) c->valid_modes_mask &= REGULATOR_MODE_NORMAL | REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) c->valid_ops_mask &= REGULATOR_CHANGE_VOLTAGE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) | REGULATOR_CHANGE_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) | REGULATOR_CHANGE_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) case TWL4030_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case TWL4030_REG_VDD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case TWL4030_REG_VDD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) case TWL4030_REG_VPLL1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case TWL4030_REG_VINTANA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) case TWL4030_REG_VINTANA2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case TWL4030_REG_VINTDIG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) c->always_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) config.init_data = initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) config.driver_data = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) config.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) rdev = devm_regulator_register(&pdev->dev, &info->desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_err(&pdev->dev, "can't register %s, %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) info->desc.name, PTR_ERR(rdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) platform_set_drvdata(pdev, rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) twlreg_write(info, TWL_MODULE_PM_RECEIVER, VREG_REMAP, info->remap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /* NOTE: many regulators support short-circuit IRQs (presentable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * as REGULATOR_OVER_CURRENT notifications?) configured via:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * - SC_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * - SC_DETECT1 (vintana2, vmmc1/2, vaux1/2/3/4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * - SC_DETECT2 (vusb, vdac, vio, vdd1/2, vpll2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * - IT_CONFIG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MODULE_ALIAS("platform:twl4030_reg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static struct platform_driver twlreg_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .probe = twlreg_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* NOTE: short name, to work around driver model truncation of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * "twl_regulator.12" (and friends) to "twl_regulator.1".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .name = "twl4030_reg",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .of_match_table = of_match_ptr(twl_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int __init twlreg_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return platform_driver_register(&twlreg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) subsys_initcall(twlreg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static void __exit twlreg_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) platform_driver_unregister(&twlreg_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) module_exit(twlreg_exit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) MODULE_DESCRIPTION("TWL4030 regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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