^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // tps80031-regulator.c -- TI TPS80031 regulator driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Regulator driver for TI TPS80031/TPS80032 Fully Integrated Power
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Management with Power Path and Battery Charger.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright (c) 2012, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) // Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/tps80031.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Flags for DCDC Voltage reading */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DCDC_OFFSET_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DCDC_EXTENDED_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TRACK_MODE_ENABLE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SMPS_MULTOFFSET_VIO BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SMPS_MULTOFFSET_SMPS1 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SMPS_MULTOFFSET_SMPS2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SMPS_MULTOFFSET_SMPS3 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SMPS_MULTOFFSET_SMPS4 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SMPS_CMD_MASK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SMPS_VSEL_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LDO_VSEL_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LDO_TRACK_VSEL_MASK 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MISC2_LDOUSB_IN_VSYS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MISC2_LDOUSB_IN_PMID BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MISC2_LDOUSB_IN_MASK 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MISC2_LDO3_SEL_VIB_VAL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MISC2_LDO3_SEL_VIB_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BOOST_HW_PWR_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BOOST_HW_PWR_EN_MASK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OPA_MODE_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OPA_MODE_EN_MASK BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define USB_VBUS_CTRL_SET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define USB_VBUS_CTRL_CLR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define VBUS_DISCHRG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) struct tps80031_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Regulator register address.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u8 trans_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u8 state_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u8 force_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 volt_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 volt_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /*Power request bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) int preq_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* used by regulator core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct tps80031_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct tps80031_regulator_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 device_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int config_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) unsigned int ext_ctrl_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static inline struct device *to_tps80031_dev(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) return rdev_get_dev(rdev)->parent->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int tps80031_reg_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (ri->ext_ctrl_flag & TPS80031_EXT_PWR_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = tps80031_read(parent, TPS80031_SLAVE_ID1, ri->rinfo->state_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(&rdev->dev, "Reg 0x%02x read failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ri->rinfo->state_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return (reg_val & TPS80031_STATE_MASK) == TPS80031_STATE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int tps80031_reg_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (ri->ext_ctrl_flag & TPS80031_EXT_PWR_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ret = tps80031_update(parent, TPS80031_SLAVE_ID1, ri->rinfo->state_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) TPS80031_STATE_ON, TPS80031_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dev_err(&rdev->dev, "Reg 0x%02x update failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ri->rinfo->state_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static int tps80031_reg_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) if (ri->ext_ctrl_flag & TPS80031_EXT_PWR_REQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = tps80031_update(parent, TPS80031_SLAVE_ID1, ri->rinfo->state_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TPS80031_STATE_OFF, TPS80031_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dev_err(&rdev->dev, "Reg 0x%02x update failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) ri->rinfo->state_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* DCDC voltages for the selector of 58 to 63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const int tps80031_dcdc_voltages[4][5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 1350, 1500, 1800, 1900, 2100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 1350, 1500, 1800, 1900, 2100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 2084, 2315, 2778, 2932, 3241},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 4167, 2315, 2778, 2932, 3241},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int tps80031_dcdc_list_voltage(struct regulator_dev *rdev, unsigned sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int volt_index = ri->device_flags & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (sel == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) else if (sel < 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return regulator_list_voltage_linear(rdev, sel - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return tps80031_dcdc_voltages[volt_index][sel - 58] * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int tps80031_dcdc_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (ri->rinfo->force_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = tps80031_read(parent, ri->rinfo->volt_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ri->rinfo->force_reg, ®_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ri->rinfo->force_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (!(reg_val & SMPS_CMD_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) ret = tps80031_update(parent, ri->rinfo->volt_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ri->rinfo->force_reg, vsel, SMPS_VSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_err(ri->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "reg 0x%02x update failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ri->rinfo->force_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = tps80031_update(parent, ri->rinfo->volt_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ri->rinfo->volt_reg, vsel, SMPS_VSEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) dev_err(ri->dev, "reg 0x%02x update failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ri->rinfo->volt_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int tps80031_dcdc_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) uint8_t vsel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (ri->rinfo->force_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = tps80031_read(parent, ri->rinfo->volt_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ri->rinfo->force_reg, &vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ri->rinfo->force_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (!(vsel & SMPS_CMD_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return vsel & SMPS_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ret = tps80031_read(parent, ri->rinfo->volt_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ri->rinfo->volt_reg, &vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ri->rinfo->volt_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return vsel & SMPS_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int tps80031_ldo_list_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Check for valid setting for TPS80031 or TPS80032-ES1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) (ri->device_flags & TRACK_MODE_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned nvsel = (sel) & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (((tps80031_get_chip_info(parent) == TPS80031) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ((tps80031_get_chip_info(parent) == TPS80032) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (tps80031_get_pmu_version(parent) == 0x0))) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ((nvsel == 0x0) || (nvsel >= 0x19 && nvsel <= 0x1F))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dev_err(ri->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) "Invalid sel %d in track mode LDO2\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) nvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return regulator_list_voltage_linear(rdev, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static int tps80031_ldo_map_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int min_uV, int max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Check for valid setting for TPS80031 or TPS80032-ES1.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) if ((ri->rinfo->desc.id == TPS80031_REGULATOR_LDO2) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) (ri->device_flags & TRACK_MODE_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (((tps80031_get_chip_info(parent) == TPS80031) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ((tps80031_get_chip_info(parent) == TPS80032) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) (tps80031_get_pmu_version(parent) == 0x0)))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return regulator_map_voltage_iterate(rdev, min_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return regulator_map_voltage_linear(rdev, min_uV, max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int tps80031_vbus_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) uint8_t ctrl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) uint8_t ctrl3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = tps80031_read(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) TPS80031_CHARGERUSB_CTRL1, &ctrl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) TPS80031_CHARGERUSB_CTRL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = tps80031_read(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) TPS80031_CHARGERUSB_CTRL3, &ctrl3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) TPS80031_CHARGERUSB_CTRL3, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if ((ctrl1 & OPA_MODE_EN) && (ctrl3 & BOOST_HW_PWR_EN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int tps80031_vbus_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ret = tps80031_set_bits(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) TPS80031_CHARGERUSB_CTRL1, OPA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) TPS80031_CHARGERUSB_CTRL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = tps80031_set_bits(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) TPS80031_CHARGERUSB_CTRL3, BOOST_HW_PWR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_err(ri->dev, "reg 0x%02x read failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) TPS80031_CHARGERUSB_CTRL3, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int tps80031_vbus_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct tps80031_regulator *ri = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct device *parent = to_tps80031_dev(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ri->config_flags & TPS80031_VBUS_DISCHRG_EN_PDN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ret = tps80031_write(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) USB_VBUS_CTRL_SET, VBUS_DISCHRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dev_err(ri->dev, "reg 0x%02x write failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) USB_VBUS_CTRL_SET, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) ret = tps80031_clr_bits(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) TPS80031_CHARGERUSB_CTRL1, OPA_MODE_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_err(ri->dev, "reg 0x%02x clearbit failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) TPS80031_CHARGERUSB_CTRL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = tps80031_clr_bits(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) TPS80031_CHARGERUSB_CTRL3, BOOST_HW_PWR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dev_err(ri->dev, "reg 0x%02x clearbit failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) TPS80031_CHARGERUSB_CTRL3, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) mdelay(DIV_ROUND_UP(ri->rinfo->desc.enable_time, 1000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (ri->config_flags & TPS80031_VBUS_DISCHRG_EN_PDN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = tps80031_write(parent, TPS80031_SLAVE_ID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) USB_VBUS_CTRL_CLR, VBUS_DISCHRG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_err(ri->dev, "reg 0x%02x write failed, e = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) USB_VBUS_CTRL_CLR, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct regulator_ops tps80031_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .list_voltage = tps80031_dcdc_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .set_voltage_sel = tps80031_dcdc_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .get_voltage_sel = tps80031_dcdc_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .enable = tps80031_reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .disable = tps80031_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .is_enabled = tps80031_reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct regulator_ops tps80031_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .list_voltage = tps80031_ldo_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .map_voltage = tps80031_ldo_map_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .enable = tps80031_reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .disable = tps80031_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .is_enabled = tps80031_reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct regulator_ops tps80031_vbus_sw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .enable = tps80031_vbus_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .disable = tps80031_vbus_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .is_enabled = tps80031_vbus_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static const struct regulator_ops tps80031_vbus_hw_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static const struct regulator_ops tps80031_ext_reg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .enable = tps80031_reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .disable = tps80031_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .is_enabled = tps80031_reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Non-exiting default definition for some register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define TPS80031_SMPS3_CFG_FORCE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TPS80031_SMPS4_CFG_FORCE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TPS80031_VBUS_CFG_TRANS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TPS80031_VBUS_CFG_STATE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define TPS80031_REG_SMPS(_id, _volt_id, _pbit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .trans_reg = TPS80031_##_id##_CFG_TRANS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .state_reg = TPS80031_##_id##_CFG_STATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .force_reg = TPS80031_##_id##_CFG_FORCE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .volt_reg = TPS80031_##_id##_CFG_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .volt_id = TPS80031_SLAVE_##_volt_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .preq_bit = _pbit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .name = "tps80031_"#_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .id = TPS80031_REGULATOR_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .n_voltages = 63, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .ops = &tps80031_dcdc_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .enable_time = 500, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define TPS80031_REG_LDO(_id, _preq_bit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .trans_reg = TPS80031_##_id##_CFG_TRANS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .state_reg = TPS80031_##_id##_CFG_STATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .volt_reg = TPS80031_##_id##_CFG_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .volt_id = TPS80031_SLAVE_ID1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .preq_bit = _preq_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "tps80031_"#_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .id = TPS80031_REGULATOR_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ops = &tps80031_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .min_uV = 1000000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .uV_step = 100000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .linear_min_sel = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .n_voltages = 25, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .vsel_reg = TPS80031_##_id##_CFG_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .vsel_mask = LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .enable_time = 500, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TPS80031_REG_FIXED(_id, max_mV, _ops, _delay, _pbit) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .trans_reg = TPS80031_##_id##_CFG_TRANS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .state_reg = TPS80031_##_id##_CFG_STATE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .volt_id = TPS80031_SLAVE_ID1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .preq_bit = _pbit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .name = "tps80031_"#_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .id = TPS80031_REGULATOR_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .min_uV = max_mV * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .ops = &_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .enable_time = _delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct tps80031_regulator_info tps80031_rinfo[TPS80031_REGULATOR_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) TPS80031_REG_SMPS(VIO, ID0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) TPS80031_REG_SMPS(SMPS1, ID0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) TPS80031_REG_SMPS(SMPS2, ID0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) TPS80031_REG_SMPS(SMPS3, ID1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) TPS80031_REG_SMPS(SMPS4, ID1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) TPS80031_REG_LDO(VANA, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) TPS80031_REG_LDO(LDO1, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) TPS80031_REG_LDO(LDO2, 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) TPS80031_REG_LDO(LDO3, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) TPS80031_REG_LDO(LDO4, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) TPS80031_REG_LDO(LDO5, 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) TPS80031_REG_LDO(LDO6, 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) TPS80031_REG_LDO(LDO7, 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) TPS80031_REG_LDO(LDOLN, 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) TPS80031_REG_LDO(LDOUSB, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) TPS80031_REG_FIXED(VBUS, 5000, tps80031_vbus_hw_ops, 100000, -1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) TPS80031_REG_FIXED(REGEN1, 3300, tps80031_ext_reg_ops, 0, 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) TPS80031_REG_FIXED(REGEN2, 3300, tps80031_ext_reg_ops, 0, 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) TPS80031_REG_FIXED(SYSEN, 3300, tps80031_ext_reg_ops, 0, 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int tps80031_power_req_config(struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct tps80031_regulator *ri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct tps80031_regulator_platform_data *tps80031_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (ri->rinfo->preq_bit < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) goto skip_pwr_req_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) ret = tps80031_ext_power_req_config(parent, ri->ext_ctrl_flag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ri->rinfo->preq_bit, ri->rinfo->state_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) ri->rinfo->trans_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_err(ri->dev, "ext powerreq config failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) skip_pwr_req_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (tps80031_pdata->ext_ctrl_flag & TPS80031_PWR_ON_ON_SLEEP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) ret = tps80031_update(parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ri->rinfo->trans_reg, TPS80031_TRANS_SLEEP_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) TPS80031_TRANS_SLEEP_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev_err(ri->dev, "Reg 0x%02x update failed, e %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ri->rinfo->trans_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int tps80031_regulator_config(struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct tps80031_regulator *ri,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct tps80031_regulator_platform_data *tps80031_pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) switch (ri->rinfo->desc.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case TPS80031_REGULATOR_LDOUSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (ri->config_flags & (TPS80031_USBLDO_INPUT_VSYS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) TPS80031_USBLDO_INPUT_PMID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (ri->config_flags & TPS80031_USBLDO_INPUT_VSYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) val = MISC2_LDOUSB_IN_VSYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) val = MISC2_LDOUSB_IN_PMID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = tps80031_update(parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) TPS80031_MISC2, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MISC2_LDOUSB_IN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dev_err(ri->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "LDOUSB config failed, e= %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) case TPS80031_REGULATOR_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (ri->config_flags & TPS80031_LDO3_OUTPUT_VIB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = tps80031_update(parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) TPS80031_MISC2, MISC2_LDO3_SEL_VIB_VAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MISC2_LDO3_SEL_VIB_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(ri->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "LDO3 config failed, e = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case TPS80031_REGULATOR_VBUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Provide SW control Ops if VBUS is SW control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!(ri->config_flags & TPS80031_VBUS_SW_ONLY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ri->rinfo->desc.ops = &tps80031_vbus_sw_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Configure Active state to ON, SLEEP to OFF and OFF_state to OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ret = tps80031_update(parent, TPS80031_SLAVE_ID1, ri->rinfo->trans_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) TPS80031_TRANS_ACTIVE_ON | TPS80031_TRANS_SLEEP_OFF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) TPS80031_TRANS_OFF_OFF, TPS80031_TRANS_ACTIVE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) TPS80031_TRANS_SLEEP_MASK | TPS80031_TRANS_OFF_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) dev_err(ri->dev, "trans reg update failed, e %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int check_smps_mode_mult(struct device *parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct tps80031_regulator *ri)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int mult_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u8 smps_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u8 smps_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) ret = tps80031_read(parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) TPS80031_SMPS_OFFSET, &smps_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) dev_err(parent, "Error in reading smps offset register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ret = tps80031_read(parent, TPS80031_SLAVE_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) TPS80031_SMPS_MULT, &smps_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_err(parent, "Error in reading smps mult register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) switch (ri->rinfo->desc.id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case TPS80031_REGULATOR_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) mult_offset = SMPS_MULTOFFSET_VIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) case TPS80031_REGULATOR_SMPS1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) mult_offset = SMPS_MULTOFFSET_SMPS1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) case TPS80031_REGULATOR_SMPS2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) mult_offset = SMPS_MULTOFFSET_SMPS2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case TPS80031_REGULATOR_SMPS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) mult_offset = SMPS_MULTOFFSET_SMPS3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) case TPS80031_REGULATOR_SMPS4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) mult_offset = SMPS_MULTOFFSET_SMPS4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case TPS80031_REGULATOR_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ri->device_flags = smps_mult & BIT(5) ? TRACK_MODE_ENABLE : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) /* TRACK mode the ldo2 varies from 600mV to 1300mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (ri->device_flags & TRACK_MODE_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ri->rinfo->desc.min_uV = 600000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ri->rinfo->desc.uV_step = 12500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ri->rinfo->desc.n_voltages = 57;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ri->rinfo->desc.vsel_mask = LDO_TRACK_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ri->device_flags = (smps_offset & mult_offset) ? DCDC_OFFSET_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ri->device_flags |= (smps_mult & mult_offset) ? DCDC_EXTENDED_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) switch (ri->device_flags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ri->rinfo->desc.min_uV = 607700;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ri->rinfo->desc.uV_step = 12660;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case DCDC_OFFSET_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ri->rinfo->desc.min_uV = 700000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ri->rinfo->desc.uV_step = 12500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case DCDC_EXTENDED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ri->rinfo->desc.min_uV = 1852000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ri->rinfo->desc.uV_step = 38600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case DCDC_OFFSET_EN | DCDC_EXTENDED_EN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ri->rinfo->desc.min_uV = 2161000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ri->rinfo->desc.uV_step = 38600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int tps80031_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct tps80031_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct tps80031_regulator_platform_data *tps_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct tps80031_regulator *ri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct tps80031_regulator *pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct tps80031 *tps80031_mfd = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pdata = dev_get_platdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(&pdev->dev, "No platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) pmic = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) TPS80031_REGULATOR_MAX, sizeof(*pmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) for (num = 0; num < TPS80031_REGULATOR_MAX; ++num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) tps_pdata = pdata->regulator_pdata[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ri = &pmic[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ri->rinfo = &tps80031_rinfo[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ri->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) check_smps_mode_mult(pdev->dev.parent, ri);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) config.init_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) config.driver_data = ri;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) config.regmap = tps80031_mfd->regmap[ri->rinfo->volt_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (tps_pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) config.init_data = tps_pdata->reg_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ri->config_flags = tps_pdata->config_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ri->ext_ctrl_flag = tps_pdata->ext_ctrl_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = tps80031_regulator_config(pdev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ri, tps_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) "regulator config failed, e %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = tps80031_power_req_config(pdev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ri, tps_pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "pwr_req config failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) rdev = devm_regulator_register(&pdev->dev, &ri->rinfo->desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "register regulator failed %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ri->rinfo->desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) platform_set_drvdata(pdev, pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) static struct platform_driver tps80031_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .name = "tps80031-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .probe = tps80031_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) static int __init tps80031_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return platform_driver_register(&tps80031_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) subsys_initcall(tps80031_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void __exit tps80031_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) platform_driver_unregister(&tps80031_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) module_exit(tps80031_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) MODULE_ALIAS("platform:tps80031-regulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) MODULE_DESCRIPTION("Regulator Driver for TI TPS80031/TPS80032 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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