^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tps65910.c -- TI tps65910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2010 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Graeme Gregory <gg@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/tps65910.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TPS65910_SUPPLY_STATE_ENABLED 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EXT_SLEEP_CONTROL (TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* supported VIO voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const unsigned int VIO_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 1500000, 1800000, 2500000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* VSEL tables for TPS65910 specific LDOs and dcdc's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* supported VRTC voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const unsigned int VRTC_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* supported VDD3 voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const unsigned int VDD3_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* supported VDIG1 voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const unsigned int VDIG1_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 1200000, 1500000, 1800000, 2700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* supported VDIG2 voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const unsigned int VDIG2_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 1000000, 1100000, 1200000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* supported VPLL voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static const unsigned int VPLL_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 1000000, 1100000, 1800000, 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* supported VDAC voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static const unsigned int VDAC_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1800000, 2600000, 2800000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* supported VAUX1 voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static const unsigned int VAUX1_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 1800000, 2500000, 2800000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* supported VAUX2 voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const unsigned int VAUX2_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 1800000, 2800000, 2900000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* supported VAUX33 voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const unsigned int VAUX33_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 1800000, 2000000, 2800000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* supported VMMC voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const unsigned int VMMC_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 1800000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* supported BBCH voltages in microvolts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const unsigned int VBB_VSEL_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 3000000, 2520000, 3150000, 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct tps_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const char *vin_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 n_voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) const unsigned int *voltage_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int enable_time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static struct tps_info tps65910_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .name = "vrtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .vin_name = "vcc7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .n_voltages = ARRAY_SIZE(VRTC_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .voltage_table = VRTC_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .enable_time_us = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = "vio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .vin_name = "vccio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .voltage_table = VIO_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .enable_time_us = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "vdd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .vin_name = "vcc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .enable_time_us = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .name = "vdd2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .vin_name = "vcc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .enable_time_us = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .name = "vdd3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .n_voltages = ARRAY_SIZE(VDD3_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .voltage_table = VDD3_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .enable_time_us = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .name = "vdig1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .vin_name = "vcc6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .n_voltages = ARRAY_SIZE(VDIG1_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) .voltage_table = VDIG1_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .name = "vdig2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .vin_name = "vcc6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .n_voltages = ARRAY_SIZE(VDIG2_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .voltage_table = VDIG2_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "vpll",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .vin_name = "vcc5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .n_voltages = ARRAY_SIZE(VPLL_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .voltage_table = VPLL_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "vdac",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .vin_name = "vcc5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .n_voltages = ARRAY_SIZE(VDAC_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .voltage_table = VDAC_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .name = "vaux1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .vin_name = "vcc4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .n_voltages = ARRAY_SIZE(VAUX1_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .voltage_table = VAUX1_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .name = "vaux2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .vin_name = "vcc4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .n_voltages = ARRAY_SIZE(VAUX2_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .voltage_table = VAUX2_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .name = "vaux33",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .vin_name = "vcc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .n_voltages = ARRAY_SIZE(VAUX33_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .voltage_table = VAUX33_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .name = "vmmc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .vin_name = "vcc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .n_voltages = ARRAY_SIZE(VMMC_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .voltage_table = VMMC_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .enable_time_us = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .name = "vbb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .vin_name = "vcc7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .n_voltages = ARRAY_SIZE(VBB_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .voltage_table = VBB_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct tps_info tps65911_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "vrtc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .vin_name = "vcc7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .enable_time_us = 2200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "vio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .vin_name = "vccio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .n_voltages = ARRAY_SIZE(VIO_VSEL_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .voltage_table = VIO_VSEL_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .enable_time_us = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "vdd1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .vin_name = "vcc1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .n_voltages = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .enable_time_us = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "vdd2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .vin_name = "vcc2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .n_voltages = 0x4C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .enable_time_us = 350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .name = "vddctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .n_voltages = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enable_time_us = 900,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "ldo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .vin_name = "vcc6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .n_voltages = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .enable_time_us = 420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .name = "ldo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .vin_name = "vcc6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .n_voltages = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .enable_time_us = 420,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .name = "ldo3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .vin_name = "vcc5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .n_voltages = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .enable_time_us = 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .name = "ldo4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .vin_name = "vcc5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .n_voltages = 0x33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .enable_time_us = 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .name = "ldo5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .vin_name = "vcc4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .n_voltages = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .enable_time_us = 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .name = "ldo6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .vin_name = "vcc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .n_voltages = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .enable_time_us = 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "ldo7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .vin_name = "vcc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .n_voltages = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .enable_time_us = 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .name = "ldo8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .vin_name = "vcc3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .n_voltages = 0x1A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .enable_time_us = 230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EXT_CONTROL_REG_BITS(id, regs_offs, bits) (((regs_offs) << 8) | (bits))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) static unsigned int tps65910_ext_sleep_control[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) EXT_CONTROL_REG_BITS(VIO, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) EXT_CONTROL_REG_BITS(VDD1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) EXT_CONTROL_REG_BITS(VDD2, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) EXT_CONTROL_REG_BITS(VDD3, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) EXT_CONTROL_REG_BITS(VDIG1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) EXT_CONTROL_REG_BITS(VDIG2, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) EXT_CONTROL_REG_BITS(VPLL, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) EXT_CONTROL_REG_BITS(VDAC, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) EXT_CONTROL_REG_BITS(VAUX1, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) EXT_CONTROL_REG_BITS(VAUX2, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) EXT_CONTROL_REG_BITS(VAUX33, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) EXT_CONTROL_REG_BITS(VMMC, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static unsigned int tps65911_ext_sleep_control[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) EXT_CONTROL_REG_BITS(VIO, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) EXT_CONTROL_REG_BITS(VDD1, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) EXT_CONTROL_REG_BITS(VDD2, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) EXT_CONTROL_REG_BITS(VDDCTRL, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) EXT_CONTROL_REG_BITS(LDO1, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) EXT_CONTROL_REG_BITS(LDO2, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) EXT_CONTROL_REG_BITS(LDO3, 0, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) EXT_CONTROL_REG_BITS(LDO4, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) EXT_CONTROL_REG_BITS(LDO5, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) EXT_CONTROL_REG_BITS(LDO6, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EXT_CONTROL_REG_BITS(LDO7, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) EXT_CONTROL_REG_BITS(LDO8, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct tps65910_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct tps65910 *mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct regulator_dev **rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct tps_info **info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int (*get_ctrl_reg)(int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int *ext_sleep_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int board_ext_control[TPS65910_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int tps65910_get_ctrl_register(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) case TPS65910_REG_VRTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return TPS65910_VRTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return TPS65910_VIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) case TPS65910_REG_VDD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return TPS65910_VDD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) case TPS65910_REG_VDD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return TPS65910_VDD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) case TPS65910_REG_VDD3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return TPS65910_VDD3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) case TPS65910_REG_VDIG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return TPS65910_VDIG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) case TPS65910_REG_VDIG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return TPS65910_VDIG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case TPS65910_REG_VPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return TPS65910_VPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) case TPS65910_REG_VDAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return TPS65910_VDAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) case TPS65910_REG_VAUX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return TPS65910_VAUX1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) case TPS65910_REG_VAUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return TPS65910_VAUX2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) case TPS65910_REG_VAUX33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return TPS65910_VAUX33;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case TPS65910_REG_VMMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return TPS65910_VMMC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case TPS65910_REG_VBB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return TPS65910_BBCH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int tps65911_get_ctrl_register(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case TPS65910_REG_VRTC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return TPS65910_VRTC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return TPS65910_VIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) case TPS65910_REG_VDD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return TPS65910_VDD1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) case TPS65910_REG_VDD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return TPS65910_VDD2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) case TPS65911_REG_VDDCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return TPS65911_VDDCTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case TPS65911_REG_LDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return TPS65911_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) case TPS65911_REG_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return TPS65911_LDO2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case TPS65911_REG_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return TPS65911_LDO3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case TPS65911_REG_LDO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return TPS65911_LDO4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case TPS65911_REG_LDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return TPS65911_LDO5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case TPS65911_REG_LDO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return TPS65911_LDO6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case TPS65911_REG_LDO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return TPS65911_LDO7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) case TPS65911_REG_LDO8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return TPS65911_LDO8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int tps65910_set_mode(struct regulator_dev *dev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int reg, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) reg = pmic->get_ctrl_reg(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return regmap_update_bits(regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) LDO_ST_MODE_BIT | LDO_ST_ON_BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) LDO_ST_ON_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return regmap_set_bits(regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) LDO_ST_ON_BIT | LDO_ST_MODE_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return regmap_clear_bits(regmap, reg, LDO_ST_ON_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static unsigned int tps65910_get_mode(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int ret, reg, value, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) reg = pmic->get_ctrl_reg(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) ret = regmap_read(regmap, reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (!(value & LDO_ST_ON_BIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) else if (value & LDO_ST_MODE_BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int tps65910_get_voltage_dcdc_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int opvsel = 0, srvsel = 0, vselmax = 0, mult = 0, sr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) case TPS65910_REG_VDD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = regmap_read(regmap, TPS65910_VDD1_OP, &opvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = regmap_read(regmap, TPS65910_VDD1, &mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) mult = (mult & VDD1_VGAIN_SEL_MASK) >> VDD1_VGAIN_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ret = regmap_read(regmap, TPS65910_VDD1_SR, &srvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sr = opvsel & VDD1_OP_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) opvsel &= VDD1_OP_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) srvsel &= VDD1_SR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) vselmax = 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) case TPS65910_REG_VDD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = regmap_read(regmap, TPS65910_VDD2_OP, &opvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_read(regmap, TPS65910_VDD2, &mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) mult = (mult & VDD2_VGAIN_SEL_MASK) >> VDD2_VGAIN_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ret = regmap_read(regmap, TPS65910_VDD2_SR, &srvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) sr = opvsel & VDD2_OP_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) opvsel &= VDD2_OP_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) srvsel &= VDD2_SR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) vselmax = 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) case TPS65911_REG_VDDCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = regmap_read(regmap, TPS65911_VDDCTRL_OP, &opvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = regmap_read(regmap, TPS65911_VDDCTRL_SR, &srvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sr = opvsel & VDDCTRL_OP_CMD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) opvsel &= VDDCTRL_OP_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) srvsel &= VDDCTRL_SR_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) vselmax = 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* multiplier 0 == 1 but 2,3 normal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!mult)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (sr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* normalise to valid range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (srvsel < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) srvsel = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (srvsel > vselmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) srvsel = vselmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return srvsel - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* normalise to valid range*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (opvsel < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) opvsel = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (opvsel > vselmax)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) opvsel = vselmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) return opvsel - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int tps65910_get_voltage_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret, reg, value, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) reg = pmic->get_ctrl_reg(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = regmap_read(regmap, reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case TPS65910_REG_VDIG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) case TPS65910_REG_VDIG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case TPS65910_REG_VPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) case TPS65910_REG_VDAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) case TPS65910_REG_VAUX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case TPS65910_REG_VAUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case TPS65910_REG_VAUX33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case TPS65910_REG_VMMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) value &= LDO_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) value >>= LDO_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) case TPS65910_REG_VBB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) value &= BBCH_BBSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) value >>= BBCH_BBSEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int tps65910_get_voltage_vdd3(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return dev->desc->volt_table[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int tps65911_get_voltage_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) int ret, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned int value, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) reg = pmic->get_ctrl_reg(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = regmap_read(regmap, reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case TPS65911_REG_LDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) case TPS65911_REG_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) case TPS65911_REG_LDO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) value &= LDO1_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) value >>= LDO_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case TPS65911_REG_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case TPS65911_REG_LDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case TPS65911_REG_LDO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case TPS65911_REG_LDO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) case TPS65911_REG_LDO8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) value &= LDO3_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) value >>= LDO_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) value &= LDO_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) value >>= LDO_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static int tps65910_set_voltage_dcdc_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int id = rdev_get_id(dev), vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int dcdc_mult = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case TPS65910_REG_VDD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (dcdc_mult == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dcdc_mult--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_update_bits(regmap, TPS65910_VDD1, VDD1_VGAIN_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dcdc_mult << VDD1_VGAIN_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regmap_write(regmap, TPS65910_VDD1_OP, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) case TPS65910_REG_VDD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dcdc_mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (dcdc_mult == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dcdc_mult--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) vsel = (selector % VDD1_2_NUM_VOLT_FINE) + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) regmap_update_bits(regmap, TPS65910_VDD2, VDD1_VGAIN_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dcdc_mult << VDD2_VGAIN_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) regmap_write(regmap, TPS65910_VDD2_OP, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) case TPS65911_REG_VDDCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) vsel = selector + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) regmap_write(regmap, TPS65911_VDDCTRL_OP, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int tps65910_set_voltage_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int reg, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) reg = pmic->get_ctrl_reg(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case TPS65910_REG_VDIG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case TPS65910_REG_VDIG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) case TPS65910_REG_VPLL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case TPS65910_REG_VDAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case TPS65910_REG_VAUX1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case TPS65910_REG_VAUX2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) case TPS65910_REG_VAUX33:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case TPS65910_REG_VMMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return regmap_update_bits(regmap, reg, LDO_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) selector << LDO_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) case TPS65910_REG_VBB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return regmap_update_bits(regmap, reg, BBCH_BBSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) selector << BBCH_BBSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int tps65911_set_voltage_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct regmap *regmap = rdev_get_regmap(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int reg, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) reg = pmic->get_ctrl_reg(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case TPS65911_REG_LDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case TPS65911_REG_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) case TPS65911_REG_LDO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return regmap_update_bits(regmap, reg, LDO1_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) selector << LDO_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) case TPS65911_REG_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) case TPS65911_REG_LDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case TPS65911_REG_LDO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) case TPS65911_REG_LDO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) case TPS65911_REG_LDO8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return regmap_update_bits(regmap, reg, LDO3_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) selector << LDO_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return regmap_update_bits(regmap, reg, LDO_SEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) selector << LDO_SEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case TPS65910_REG_VBB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return regmap_update_bits(regmap, reg, BBCH_BBSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) selector << BBCH_BBSEL_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static int tps65910_list_voltage_dcdc(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int volt, mult = 1, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) case TPS65910_REG_VDD1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case TPS65910_REG_VDD2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mult = (selector / VDD1_2_NUM_VOLT_FINE) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) volt = VDD1_2_MIN_VOLT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) (selector % VDD1_2_NUM_VOLT_FINE) * VDD1_2_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) case TPS65911_REG_VDDCTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) volt = VDDCTRL_MIN_VOLT + (selector * VDDCTRL_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return volt * 100 * mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static int tps65911_list_voltage(struct regulator_dev *dev, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct tps65910_reg *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int step_mv = 0, id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) case TPS65911_REG_LDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) case TPS65911_REG_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) case TPS65911_REG_LDO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* The first 5 values of the selector correspond to 1V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (selector < 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) selector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) selector -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) step_mv = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case TPS65911_REG_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case TPS65911_REG_LDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case TPS65911_REG_LDO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case TPS65911_REG_LDO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case TPS65911_REG_LDO8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* The first 3 values of the selector correspond to 1V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (selector < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) selector = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) selector -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) step_mv = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case TPS65910_REG_VIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return pmic->info[id]->voltage_table[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return (LDO_MIN_VOLT + selector * step_mv) * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* Regulator ops (except VRTC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct regulator_ops tps65910_ops_dcdc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .set_mode = tps65910_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .get_mode = tps65910_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .get_voltage_sel = tps65910_get_voltage_dcdc_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .set_voltage_sel = tps65910_set_voltage_dcdc_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .list_voltage = tps65910_list_voltage_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct regulator_ops tps65910_ops_vdd3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .set_mode = tps65910_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .get_mode = tps65910_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .get_voltage = tps65910_get_voltage_vdd3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const struct regulator_ops tps65910_ops_vbb = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .set_mode = tps65910_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .get_mode = tps65910_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .get_voltage_sel = tps65910_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .set_voltage_sel = tps65910_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .map_voltage = regulator_map_voltage_iterate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static const struct regulator_ops tps65910_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .set_mode = tps65910_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .get_mode = tps65910_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .get_voltage_sel = tps65910_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .set_voltage_sel = tps65910_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static const struct regulator_ops tps65911_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .set_mode = tps65910_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .get_mode = tps65910_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .get_voltage_sel = tps65911_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .set_voltage_sel = tps65911_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .list_voltage = tps65911_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int tps65910_set_ext_sleep_config(struct tps65910_reg *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int id, int ext_sleep_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct tps65910 *mfd = pmic->mfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u8 regoffs = (pmic->ext_sleep_control[id] >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u8 bit_pos = (1 << pmic->ext_sleep_control[id] & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) * Regulator can not be control from multiple external input EN1, EN2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) * and EN3 together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ext_sleep_config & EXT_SLEEP_CONTROL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int en_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) en_count = ((ext_sleep_config &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) en_count += ((ext_sleep_config &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) en_count += ((ext_sleep_config &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) en_count += ((ext_sleep_config &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (en_count > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "External sleep control flag is not proper\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pmic->board_ext_control[id] = ext_sleep_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* External EN1 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = regmap_set_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) TPS65910_EN1_LDO_ASS + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "Error in configuring external control EN1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* External EN2 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret = regmap_set_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) TPS65910_EN2_LDO_ASS + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "Error in configuring external control EN2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* External EN3 control for TPS65910 LDO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if ((tps65910_chip_id(mfd) == TPS65910) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) (id >= TPS65910_REG_VDIG1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (ext_sleep_config & TPS65910_SLEEP_CONTROL_EXT_INPUT_EN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = regmap_set_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) TPS65910_EN3_LDO_ASS + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "Error in configuring external control EN3\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Return if no external control is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!(ext_sleep_config & EXT_SLEEP_CONTROL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Clear all sleep controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) "Error in configuring SLEEP register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * For regulator that has separate operational and sleep register make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * sure that operational is used and clear sleep register to turn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * regulator off when external control is inactive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if ((id == TPS65910_REG_VDD1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) (id == TPS65910_REG_VDD2) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ((id == TPS65911_REG_VDDCTRL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) (tps65910_chip_id(mfd) == TPS65911))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int op_reg_add = pmic->get_ctrl_reg(id) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) int sr_reg_add = pmic->get_ctrl_reg(id) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int opvsel, srvsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = regmap_read(mfd->regmap, op_reg_add, &opvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = regmap_read(mfd->regmap, sr_reg_add, &srvsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (opvsel & VDD1_OP_CMD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u8 reg_val = srvsel & VDD1_OP_SEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = regmap_write(mfd->regmap, op_reg_add, reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) "Error in configuring op register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = regmap_write(mfd->regmap, sr_reg_add, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(mfd->dev, "Error in setting sr register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) TPS65910_SLEEP_KEEP_LDO_ON + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ext_sleep_config & TPS65911_SLEEP_CONTROL_EXT_INPUT_SLEEP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = regmap_set_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = regmap_clear_bits(mfd->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) TPS65910_SLEEP_SET_LDO_OFF + regoffs, bit_pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_err(mfd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) "Error in configuring SLEEP register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static struct of_regulator_match tps65910_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) { .name = "vrtc", .driver_data = (void *) &tps65910_regs[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) { .name = "vio", .driver_data = (void *) &tps65910_regs[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) { .name = "vdd1", .driver_data = (void *) &tps65910_regs[2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) { .name = "vdd2", .driver_data = (void *) &tps65910_regs[3] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) { .name = "vdd3", .driver_data = (void *) &tps65910_regs[4] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) { .name = "vdig1", .driver_data = (void *) &tps65910_regs[5] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) { .name = "vdig2", .driver_data = (void *) &tps65910_regs[6] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) { .name = "vpll", .driver_data = (void *) &tps65910_regs[7] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) { .name = "vdac", .driver_data = (void *) &tps65910_regs[8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) { .name = "vaux1", .driver_data = (void *) &tps65910_regs[9] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) { .name = "vaux2", .driver_data = (void *) &tps65910_regs[10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) { .name = "vaux33", .driver_data = (void *) &tps65910_regs[11] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) { .name = "vmmc", .driver_data = (void *) &tps65910_regs[12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) { .name = "vbb", .driver_data = (void *) &tps65910_regs[13] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static struct of_regulator_match tps65911_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) { .name = "vrtc", .driver_data = (void *) &tps65911_regs[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) { .name = "vio", .driver_data = (void *) &tps65911_regs[1] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) { .name = "vdd1", .driver_data = (void *) &tps65911_regs[2] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) { .name = "vdd2", .driver_data = (void *) &tps65911_regs[3] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) { .name = "vddctrl", .driver_data = (void *) &tps65911_regs[4] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) { .name = "ldo1", .driver_data = (void *) &tps65911_regs[5] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) { .name = "ldo2", .driver_data = (void *) &tps65911_regs[6] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) { .name = "ldo3", .driver_data = (void *) &tps65911_regs[7] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) { .name = "ldo4", .driver_data = (void *) &tps65911_regs[8] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) { .name = "ldo5", .driver_data = (void *) &tps65911_regs[9] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) { .name = "ldo6", .driver_data = (void *) &tps65911_regs[10] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) { .name = "ldo7", .driver_data = (void *) &tps65911_regs[11] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) { .name = "ldo8", .driver_data = (void *) &tps65911_regs[12] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct tps65910_board *tps65910_parse_dt_reg_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct of_regulator_match **tps65910_reg_matches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct tps65910_board *pmic_plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct device_node *np, *regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct of_regulator_match *matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) unsigned int prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int idx = 0, ret, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) pmic_plat_data = devm_kzalloc(&pdev->dev, sizeof(*pmic_plat_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!pmic_plat_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) np = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) regulators = of_get_child_by_name(np, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!regulators) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) dev_err(&pdev->dev, "regulator node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) switch (tps65910_chip_id(tps65910)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case TPS65910:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) count = ARRAY_SIZE(tps65910_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) matches = tps65910_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case TPS65911:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) count = ARRAY_SIZE(tps65911_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) matches = tps65911_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) of_node_put(regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) dev_err(&pdev->dev, "Invalid tps chip version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = of_regulator_match(&pdev->dev, regulators, matches, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) of_node_put(regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) dev_err(&pdev->dev, "Error parsing regulator init data: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) *tps65910_reg_matches = matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) for (idx = 0; idx < count; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (!matches[idx].of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) pmic_plat_data->tps65910_pmic_init_data[idx] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) matches[idx].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ret = of_property_read_u32(matches[idx].of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "ti,regulator-ext-sleep-control", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pmic_plat_data->regulator_ext_sleep_control[idx] = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return pmic_plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) static inline struct tps65910_board *tps65910_parse_dt_reg_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct of_regulator_match **tps65910_reg_matches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) *tps65910_reg_matches = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int tps65910_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct tps65910 *tps65910 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct tps_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct tps65910_reg *pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct tps65910_board *pmic_plat_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct of_regulator_match *tps65910_reg_matches = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pmic_plat_data = dev_get_platdata(tps65910->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!pmic_plat_data && tps65910->dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) pmic_plat_data = tps65910_parse_dt_reg_data(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) &tps65910_reg_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!pmic_plat_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev_err(&pdev->dev, "Platform data not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pmic->mfd = tps65910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) platform_set_drvdata(pdev, pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* Give control of all register to control port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) err = regmap_set_bits(pmic->mfd->regmap, TPS65910_DEVCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) DEVCTRL_SR_CTL_I2C_SEL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) switch (tps65910_chip_id(tps65910)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) case TPS65910:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65910_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) pmic->get_ctrl_reg = &tps65910_get_ctrl_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) pmic->num_regulators = ARRAY_SIZE(tps65910_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pmic->ext_sleep_control = tps65910_ext_sleep_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) info = tps65910_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Work around silicon erratum SWCZ010: output programmed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * voltage level can go higher than expected or crash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Workaround: use no synchronization of DCDC clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) regmap_clear_bits(pmic->mfd->regmap, TPS65910_DCDCCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) DCDCCTRL_DCDCCKSYNC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case TPS65911:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) BUILD_BUG_ON(TPS65910_NUM_REGS < ARRAY_SIZE(tps65911_regs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) pmic->get_ctrl_reg = &tps65911_get_ctrl_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) pmic->num_regulators = ARRAY_SIZE(tps65911_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) pmic->ext_sleep_control = tps65911_ext_sleep_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) info = tps65911_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev_err(&pdev->dev, "Invalid tps chip version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pmic->desc = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pmic->num_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) sizeof(struct regulator_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!pmic->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) pmic->info = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) pmic->num_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) sizeof(struct tps_info *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (!pmic->info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pmic->rdev = devm_kcalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pmic->num_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) sizeof(struct regulator_dev *),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!pmic->rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) for (i = 0; i < pmic->num_regulators; i++, info++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* Register the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) pmic->info[i] = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) pmic->desc[i].name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) pmic->desc[i].supply_name = info->vin_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pmic->desc[i].id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) pmic->desc[i].n_voltages = info->n_voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) pmic->desc[i].enable_time = info->enable_time_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (i == TPS65910_REG_VDD1 || i == TPS65910_REG_VDD2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) pmic->desc[i].ops = &tps65910_ops_dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) pmic->desc[i].n_voltages = VDD1_2_NUM_VOLT_FINE *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) VDD1_2_NUM_VOLT_COARSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) pmic->desc[i].ramp_delay = 12500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) } else if (i == TPS65910_REG_VDD3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (tps65910_chip_id(tps65910) == TPS65910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) pmic->desc[i].ops = &tps65910_ops_vdd3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) pmic->desc[i].volt_table = info->voltage_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pmic->desc[i].ops = &tps65910_ops_dcdc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) pmic->desc[i].ramp_delay = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) } else if (i == TPS65910_REG_VBB &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) tps65910_chip_id(tps65910) == TPS65910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) pmic->desc[i].ops = &tps65910_ops_vbb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) pmic->desc[i].volt_table = info->voltage_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (tps65910_chip_id(tps65910) == TPS65910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) pmic->desc[i].ops = &tps65910_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pmic->desc[i].volt_table = info->voltage_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pmic->desc[i].ops = &tps65911_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err = tps65910_set_ext_sleep_config(pmic, i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) pmic_plat_data->regulator_ext_sleep_control[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) * Failing on regulator for configuring externally control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) * is not a serious issue, just throw warning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_warn(tps65910->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "Failed to initialise ext control config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pmic->desc[i].type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pmic->desc[i].owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) pmic->desc[i].enable_reg = pmic->get_ctrl_reg(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pmic->desc[i].enable_mask = TPS65910_SUPPLY_STATE_ENABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) config.dev = tps65910->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) config.init_data = pmic_plat_data->tps65910_pmic_init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) config.driver_data = pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) config.regmap = tps65910->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (tps65910_reg_matches)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) config.of_node = tps65910_reg_matches[i].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) rdev = devm_regulator_register(&pdev->dev, &pmic->desc[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (IS_ERR(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return dev_err_probe(tps65910->dev, PTR_ERR(rdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* Save regulator for cleanup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) pmic->rdev[i] = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static void tps65910_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct tps65910_reg *pmic = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Before bootloader jumps to kernel, it makes sure that required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) * external control signals are in desired state so that given rails
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * can be configure accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) * If rails are configured to be controlled from external control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * then before shutting down/rebooting the system, the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * control configuration need to be remove from the rails so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * its output will be available as per register programming even
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * if external controls are removed. This is require when the POR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * value of the control signals are not in active state and before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * bootloader initializes it, the system requires the rail output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * to be active for booting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) for (i = 0; i < pmic->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (!pmic->rdev[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) err = tps65910_set_ext_sleep_config(pmic, i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) "Error in clearing external control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static struct platform_driver tps65910_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .name = "tps65910-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .probe = tps65910_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .shutdown = tps65910_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static int __init tps65910_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return platform_driver_register(&tps65910_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) subsys_initcall(tps65910_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static void __exit tps65910_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) platform_driver_unregister(&tps65910_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) module_exit(tps65910_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) MODULE_DESCRIPTION("TPS65910/TPS65911 voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) MODULE_ALIAS("platform:tps65910-pmic");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags