^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Regulator driver for TPS6524x PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2010 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/spi/spi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_LDO_SET 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LDO_ILIM_MASK 1 /* 0 = 400-800, 1 = 900-1500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LDO_VSEL_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LDO2_ILIM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LDO2_VSEL_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LDO1_ILIM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LDO1_VSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define REG_BLOCK_EN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BLOCK_MASK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BLOCK_LDO1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BLOCK_LDO2_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BLOCK_LCD_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BLOCK_USB_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_DCDC_SET 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DCDC_VDCDC_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DCDC_VDCDC1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DCDC_VDCDC2_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DCDC_VDCDC3_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_DCDC_EN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DCDCDCDC_EN_MASK 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DCDCDCDC1_EN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DCDCDCDC1_PG_MSK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DCDCDCDC2_EN_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DCDCDCDC2_PG_MSK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DCDCDCDC3_EN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DCDCDCDC3_PG_MSK BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_USB 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define USB_ILIM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define USB_ILIM_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define USB_TSD_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define USB_TSD_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define USB_TWARN_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB_TWARN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USB_IWARN_SD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define USB_FAST_LOOP BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_ALARM 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ALARM_LDO1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ALARM_DCDC1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ALARM_DCDC2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ALARM_DCDC3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ALARM_LDO2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ALARM_USB_WARN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ALARM_USB_ALARM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ALARM_LCD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ALARM_TEMP_WARM BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ALARM_TEMP_HOT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ALARM_NRST BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ALARM_POWERUP BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_INT_ENABLE 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define INT_LDO1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define INT_DCDC1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define INT_DCDC2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define INT_DCDC3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define INT_LDO2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define INT_USB_WARN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define INT_USB_ALARM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define INT_LCD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define INT_TEMP_WARM BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define INT_TEMP_HOT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define INT_GLOBAL_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_INT_STATUS 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STATUS_LDO1 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STATUS_DCDC1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STATUS_DCDC2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STATUS_DCDC3 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STATUS_LDO2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STATUS_USB_WARN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STATUS_USB_ALARM BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STATUS_LCD BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define STATUS_TEMP_WARM BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define STATUS_TEMP_HOT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_SOFTWARE_RESET 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_WRITE_ENABLE 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_REV_ID 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define N_DCDC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define N_LDO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define N_SWITCH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define N_REGULATORS (N_DCDC + N_LDO + N_SWITCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CMD_READ(reg) ((reg) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CMD_WRITE(reg) (BIT(5) | (reg) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define STAT_CLK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define STAT_WRITE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define STAT_INVALID BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define STAT_WP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct supply_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int n_voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const unsigned int *voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int n_ilimsels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const unsigned int *ilimsels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct field enable, voltage, ilimsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct tps6524x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct spi_device *spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct regulator_desc desc[N_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int __read_reg(struct tps6524x *hw, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 cmd = CMD_READ(reg), in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct spi_transfer t[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) memset(t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) t[0].tx_buf = &cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) t[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) t[0].bits_per_word = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) t[1].rx_buf = ∈
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) t[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) t[1].bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) t[2].rx_buf = &status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) t[2].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) t[2].bits_per_word = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) spi_message_add_tail(&t[2], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) error = spi_sync(hw->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) dev_dbg(hw->dev, "read reg %d, data %x, status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg, in, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!(status & STAT_CLK) || (status & STAT_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (status & STAT_INVALID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int read_reg(struct tps6524x *hw, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mutex_lock(&hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = __read_reg(hw, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) mutex_unlock(&hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static int __write_reg(struct tps6524x *hw, int reg, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u16 cmd = CMD_WRITE(reg), out = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u8 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct spi_message m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct spi_transfer t[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) spi_message_init(&m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) memset(t, 0, sizeof(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) t[0].tx_buf = &cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) t[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) t[0].bits_per_word = 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) spi_message_add_tail(&t[0], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) t[1].tx_buf = &out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) t[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) t[1].bits_per_word = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) spi_message_add_tail(&t[1], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) t[2].rx_buf = &status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) t[2].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) t[2].bits_per_word = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) spi_message_add_tail(&t[2], &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) error = spi_sync(hw->spi, &m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) if (error < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) dev_dbg(hw->dev, "wrote reg %d, data %x, status %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) reg, out, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (!(status & STAT_CLK) || !(status & STAT_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (status & (STAT_INVALID | STAT_WP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static int __rmw_reg(struct tps6524x *hw, int reg, int mask, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ret = __read_reg(hw, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ret |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = __write_reg(hw, reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return (ret < 0) ? ret : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int rmw_protect(struct tps6524x *hw, int reg, int mask, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) mutex_lock(&hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = __write_reg(hw, REG_WRITE_ENABLE, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_err(hw->dev, "failed to set write enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = __rmw_reg(hw, reg, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev_err(hw->dev, "failed to rmw register %d\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) ret = __write_reg(hw, REG_WRITE_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_err(hw->dev, "failed to clear write enable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mutex_unlock(&hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int read_field(struct tps6524x *hw, const struct field *field)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) tmp = read_reg(hw, field->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (tmp < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return (tmp >> field->shift) & field->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static int write_field(struct tps6524x *hw, const struct field *field,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (val & ~field->mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return -EOVERFLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return rmw_protect(hw, field->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) field->mask << field->shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) val << field->shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const unsigned int dcdc1_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 800000, 825000, 850000, 875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 900000, 925000, 950000, 975000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 1000000, 1025000, 1050000, 1075000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 1100000, 1125000, 1150000, 1175000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 1200000, 1225000, 1250000, 1275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 1300000, 1325000, 1350000, 1375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 1400000, 1425000, 1450000, 1475000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 1500000, 1525000, 1550000, 1575000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const unsigned int dcdc2_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 1400000, 1450000, 1500000, 1550000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 1600000, 1650000, 1700000, 1750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 1800000, 1850000, 1900000, 1950000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 2000000, 2050000, 2100000, 2150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 2200000, 2250000, 2300000, 2350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 2400000, 2450000, 2500000, 2550000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 2600000, 2650000, 2700000, 2750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 2800000, 2850000, 2900000, 2950000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const unsigned int dcdc3_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 2400000, 2450000, 2500000, 2550000, 2600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 2650000, 2700000, 2750000, 2800000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 2900000, 2950000, 3000000, 3050000, 3100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 3150000, 3200000, 3250000, 3300000, 3350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 3400000, 3450000, 3500000, 3550000, 3600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const unsigned int ldo1_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 4300000, 4350000, 4400000, 4450000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 4500000, 4550000, 4600000, 4650000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 4700000, 4750000, 4800000, 4850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 4900000, 4950000, 5000000, 5050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const unsigned int ldo2_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 1100000, 1150000, 1200000, 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 1300000, 1700000, 1750000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 1850000, 1900000, 3150000, 3200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 3250000, 3300000, 3350000, 3400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const unsigned int fixed_5000000_voltage[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static const unsigned int ldo_ilimsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 400000, 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const unsigned int usb_ilimsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 200000, 400000, 800000, 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const unsigned int fixed_2400000_ilimsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 2400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const unsigned int fixed_1200000_ilimsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 1200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const unsigned int fixed_400000_ilimsel[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define __MK_FIELD(_reg, _mask, _shift) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { .reg = (_reg), .mask = (_mask), .shift = (_shift), }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct supply_info supply_info[N_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .name = "DCDC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .n_voltages = ARRAY_SIZE(dcdc1_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .voltages = dcdc1_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .n_ilimsels = ARRAY_SIZE(fixed_2400000_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .ilimsels = fixed_2400000_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .enable = __MK_FIELD(REG_DCDC_EN, DCDCDCDC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) DCDCDCDC1_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .voltage = __MK_FIELD(REG_DCDC_SET, DCDC_VDCDC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) DCDC_VDCDC1_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .name = "DCDC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .n_voltages = ARRAY_SIZE(dcdc2_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .voltages = dcdc2_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .n_ilimsels = ARRAY_SIZE(fixed_1200000_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .ilimsels = fixed_1200000_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .enable = __MK_FIELD(REG_DCDC_EN, DCDCDCDC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DCDCDCDC2_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .voltage = __MK_FIELD(REG_DCDC_SET, DCDC_VDCDC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DCDC_VDCDC2_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .name = "DCDC3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .n_voltages = ARRAY_SIZE(dcdc3_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .voltages = dcdc3_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .n_ilimsels = ARRAY_SIZE(fixed_1200000_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .ilimsels = fixed_1200000_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .enable = __MK_FIELD(REG_DCDC_EN, DCDCDCDC_EN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) DCDCDCDC3_EN_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .voltage = __MK_FIELD(REG_DCDC_SET, DCDC_VDCDC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DCDC_VDCDC3_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .name = "LDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .n_voltages = ARRAY_SIZE(ldo1_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .voltages = ldo1_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .n_ilimsels = ARRAY_SIZE(ldo_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .ilimsels = ldo_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .enable = __MK_FIELD(REG_BLOCK_EN, BLOCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) BLOCK_LDO1_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .voltage = __MK_FIELD(REG_LDO_SET, LDO_VSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) LDO1_VSEL_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .ilimsel = __MK_FIELD(REG_LDO_SET, LDO_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) LDO1_ILIM_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .name = "LDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .n_voltages = ARRAY_SIZE(ldo2_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .voltages = ldo2_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .n_ilimsels = ARRAY_SIZE(ldo_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .ilimsels = ldo_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .enable = __MK_FIELD(REG_BLOCK_EN, BLOCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) BLOCK_LDO2_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .voltage = __MK_FIELD(REG_LDO_SET, LDO_VSEL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) LDO2_VSEL_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .ilimsel = __MK_FIELD(REG_LDO_SET, LDO_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) LDO2_ILIM_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .name = "USB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .n_voltages = ARRAY_SIZE(fixed_5000000_voltage),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .voltages = fixed_5000000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .n_ilimsels = ARRAY_SIZE(usb_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .ilimsels = usb_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .enable = __MK_FIELD(REG_BLOCK_EN, BLOCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) BLOCK_USB_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .ilimsel = __MK_FIELD(REG_USB, USB_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) USB_ILIM_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .name = "LCD",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .n_voltages = ARRAY_SIZE(fixed_5000000_voltage),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .voltages = fixed_5000000_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .n_ilimsels = ARRAY_SIZE(fixed_400000_ilimsel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .ilimsels = fixed_400000_ilimsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .enable = __MK_FIELD(REG_BLOCK_EN, BLOCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) BLOCK_LCD_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (rdev->desc->n_voltages == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return write_field(hw, &info->voltage, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (rdev->desc->n_voltages == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ret = read_field(hw, &info->voltage);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (WARN_ON(ret >= info->n_voltages))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int set_current_limit(struct regulator_dev *rdev, int min_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int max_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (info->n_ilimsels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) for (i = info->n_ilimsels - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (min_uA <= info->ilimsels[i] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) max_uA >= info->ilimsels[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return write_field(hw, &info->ilimsel, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int get_current_limit(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (info->n_ilimsels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return info->ilimsels[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = read_field(hw, &info->ilimsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (WARN_ON(ret >= info->n_ilimsels))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return info->ilimsels[ret];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int enable_supply(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return write_field(hw, &info->enable, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static int disable_supply(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return write_field(hw, &info->enable, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int is_supply_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const struct supply_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) hw = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) info = &supply_info[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return read_field(hw, &info->enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static const struct regulator_ops regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .is_enabled = is_supply_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .enable = enable_supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .disable = disable_supply,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .get_voltage_sel = get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .set_voltage_sel = set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .set_current_limit = set_current_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .get_current_limit = get_current_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static int pmic_probe(struct spi_device *spi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct tps6524x *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct device *dev = &spi->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const struct supply_info *info = supply_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct regulator_init_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) init_data = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev_err(dev, "could not find regulator platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) hw = devm_kzalloc(&spi->dev, sizeof(struct tps6524x), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) spi_set_drvdata(spi, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) memset(hw, 0, sizeof(struct tps6524x));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) hw->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) hw->spi = spi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mutex_init(&hw->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) for (i = 0; i < N_REGULATORS; i++, info++, init_data++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) hw->desc[i].name = info->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hw->desc[i].id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) hw->desc[i].n_voltages = info->n_voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) hw->desc[i].volt_table = info->voltages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) hw->desc[i].ops = ®ulator_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) hw->desc[i].type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) hw->desc[i].owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) config.init_data = init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) config.driver_data = hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) rdev = devm_regulator_register(dev, &hw->desc[i], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (IS_ERR(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static struct spi_driver pmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .probe = pmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .name = "tps6524x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) module_spi_driver(pmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_DESCRIPTION("TPS6524X PMIC Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MODULE_AUTHOR("Cyril Chemparathy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) MODULE_ALIAS("spi:tps6524x");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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