Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * tps51632-regulator.c -- TI TPS51632
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Regulator driver for TPS51632 3-2-1 Phase D-Cap Step Down Driverless
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Controller with serial VID control and DVFS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2012, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * 02111-1307, USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #include <linux/regulator/tps51632-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TPS51632_VOLTAGE_SELECT_REG		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TPS51632_VOLTAGE_BASE_REG		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TPS51632_OFFSET_REG			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TPS51632_IMON_REG			0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TPS51632_VMAX_REG			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TPS51632_DVFS_CONTROL_REG		0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TPS51632_POWER_STATE_REG		0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TPS51632_SLEW_REGS			0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TPS51632_FAULT_REG			0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define TPS51632_MAX_REG			0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TPS51632_VOUT_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TPS51632_VOUT_OFFSET_MASK		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define TPS51632_VMAX_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TPS51632_VMAX_LOCK			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* TPS51632_DVFS_CONTROL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define TPS51632_DVFS_PWMEN			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TPS51632_DVFS_STEP_20			0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TPS51632_DVFS_VMAX_PG			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TPS51632_DVFS_PWMRST			0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define TPS51632_DVFS_OCA_EN			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TPS51632_DVFS_FCCM			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* TPS51632_POWER_STATE_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TPS51632_POWER_STATE_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TPS51632_POWER_STATE_MULTI_PHASE_CCM	0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define TPS51632_POWER_STATE_SINGLE_PHASE_CCM	0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TPS51632_POWER_STATE_SINGLE_PHASE_DCM	0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TPS51632_MIN_VOLTAGE			500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TPS51632_MAX_VOLTAGE			1520000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TPS51632_VOLTAGE_STEP_10mV		10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TPS51632_VOLTAGE_STEP_20mV		20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TPS51632_MAX_VSEL			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TPS51632_MIN_VSEL			0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TPS51632_DEFAULT_RAMP_DELAY		6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TPS51632_VOLT_VSEL(uV)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		(DIV_ROUND_UP(uV - TPS51632_MIN_VOLTAGE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			TPS51632_VOLTAGE_STEP_10mV) +		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			TPS51632_MIN_VSEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* TPS51632 chip information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) struct tps51632_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static int tps51632_dcdc_set_ramp_delay(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	struct tps51632_chip *tps = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	if (ramp_delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		bit = DIV_ROUND_UP(ramp_delay, 6000) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	ret = regmap_write(tps->regmap, TPS51632_SLEW_REGS, BIT(bit));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		dev_err(tps->dev, "SLEW reg write failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct regulator_ops tps51632_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.list_voltage		= regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.set_ramp_delay		= tps51632_dcdc_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int tps51632_init_dcdc(struct tps51632_chip *tps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		struct tps51632_regulator_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	uint8_t	control = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	int vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	if (!pdata->enable_pwm_dvfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		goto skip_pwm_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	control |= TPS51632_DVFS_PWMEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	vsel = TPS51632_VOLT_VSEL(pdata->base_voltage_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	ret = regmap_write(tps->regmap, TPS51632_VOLTAGE_BASE_REG, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		dev_err(tps->dev, "BASE reg write failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (pdata->dvfs_step_20mV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		control |= TPS51632_DVFS_STEP_20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	if (pdata->max_voltage_uV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		unsigned int vmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		/**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		 * TPS51632 hw behavior: VMAX register can be write only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		 * once as it get locked after first write. The lock get
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		 * reset only when device is power-reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		 * Write register only when lock bit is not enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		ret = regmap_read(tps->regmap, TPS51632_VMAX_REG, &vmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			dev_err(tps->dev, "VMAX read failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		if (!(vmax & TPS51632_VMAX_LOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			vsel = TPS51632_VOLT_VSEL(pdata->max_voltage_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			ret = regmap_write(tps->regmap, TPS51632_VMAX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 					vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 				dev_err(tps->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 					"VMAX write failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) skip_pwm_config:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	ret = regmap_write(tps->regmap, TPS51632_DVFS_CONTROL_REG, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		dev_err(tps->dev, "DVFS reg write failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static bool is_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	case TPS51632_OFFSET_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	case TPS51632_FAULT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	case TPS51632_IMON_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static bool is_read_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case 0x08 ... 0x0F:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static bool is_write_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	case TPS51632_VOLTAGE_SELECT_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	case TPS51632_VOLTAGE_BASE_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	case TPS51632_VMAX_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	case TPS51632_DVFS_CONTROL_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	case TPS51632_POWER_STATE_REG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	case TPS51632_SLEW_REGS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct regmap_config tps51632_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.reg_bits		= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.val_bits		= 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.writeable_reg		= is_write_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.readable_reg		= is_read_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.volatile_reg		= is_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.max_register		= TPS51632_MAX_REG - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	.cache_type		= REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #if defined(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct of_device_id tps51632_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ .compatible = "ti,tps51632",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_DEVICE_TABLE(of, tps51632_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct tps51632_regulator_platform_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	of_get_tps51632_platform_data(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 				      const struct regulator_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	struct tps51632_regulator_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	pdata->reg_init_data = of_get_regulator_init_data(dev, dev->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 							  desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	if (!pdata->reg_init_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		dev_err(dev, "Not able to get OF regulator init data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	pdata->enable_pwm_dvfs =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			of_property_read_bool(np, "ti,enable-pwm-dvfs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	pdata->dvfs_step_20mV = of_property_read_bool(np, "ti,dvfs-step-20mV");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	pdata->base_voltage_uV = pdata->reg_init_data->constraints.min_uV ? :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 					TPS51632_MIN_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	pdata->max_voltage_uV = pdata->reg_init_data->constraints.max_uV ? :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 					TPS51632_MAX_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static struct tps51632_regulator_platform_data *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	of_get_tps51632_platform_data(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 				      const struct regulator_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int tps51632_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	struct tps51632_regulator_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct tps51632_chip *tps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	if (client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		match = of_match_device(of_match_ptr(tps51632_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			dev_err(&client->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	tps = devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (!tps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	tps->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	tps->desc.name = client->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	tps->desc.id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	tps->desc.ramp_delay = TPS51632_DEFAULT_RAMP_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	tps->desc.min_uV = TPS51632_MIN_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	tps->desc.uV_step = TPS51632_VOLTAGE_STEP_10mV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	tps->desc.linear_min_sel = TPS51632_MIN_VSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	tps->desc.n_voltages = TPS51632_MAX_VSEL + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	tps->desc.ops = &tps51632_dcdc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	tps->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	tps->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (!pdata && client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		pdata = of_get_tps51632_platform_data(&client->dev, &tps->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		dev_err(&client->dev, "No Platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	if (pdata->enable_pwm_dvfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		if ((pdata->base_voltage_uV < TPS51632_MIN_VOLTAGE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		    (pdata->base_voltage_uV > TPS51632_MAX_VOLTAGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 			dev_err(&client->dev, "Invalid base_voltage_uV setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		if ((pdata->max_voltage_uV) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		    ((pdata->max_voltage_uV < TPS51632_MIN_VOLTAGE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		     (pdata->max_voltage_uV > TPS51632_MAX_VOLTAGE))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 			dev_err(&client->dev, "Invalid max_voltage_uV setting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	if (pdata->enable_pwm_dvfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		tps->desc.vsel_reg = TPS51632_VOLTAGE_BASE_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		tps->desc.vsel_reg = TPS51632_VOLTAGE_SELECT_REG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	tps->desc.vsel_mask = TPS51632_VOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	tps->regmap = devm_regmap_init_i2c(client, &tps51632_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (IS_ERR(tps->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		ret = PTR_ERR(tps->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		dev_err(&client->dev, "regmap init failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	i2c_set_clientdata(client, tps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	ret = tps51632_init_dcdc(tps, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		dev_err(tps->dev, "Init failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* Register the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	config.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	config.init_data = pdata->reg_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	config.driver_data = tps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	config.regmap = tps->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	config.of_node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	rdev = devm_regulator_register(&client->dev, &tps->desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		dev_err(tps->dev, "regulator register failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 		return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	tps->rdev = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static const struct i2c_device_id tps51632_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	{.name = "tps51632",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DEVICE_TABLE(i2c, tps51632_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static struct i2c_driver tps51632_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		.name = "tps51632",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		.of_match_table = of_match_ptr(tps51632_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	.probe = tps51632_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	.id_table = tps51632_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int __init tps51632_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	return i2c_add_driver(&tps51632_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) subsys_initcall(tps51632_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static void __exit tps51632_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	i2c_del_driver(&tps51632_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) module_exit(tps51632_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_DESCRIPTION("TPS51632 voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MODULE_LICENSE("GPL v2");