^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Fabrice Gasnier <fabrice.gasnier@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* STM32 VREFBUF registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define STM32_VREFBUF_CSR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* STM32 VREFBUF CSR bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define STM32_VRS GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define STM32_VRR BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define STM32_HIZ BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define STM32_ENVR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define STM32_VREFBUF_AUTO_SUSPEND_DELAY_MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct stm32_vrefbuf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const unsigned int stm32_vrefbuf_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Matches resp. VRS = 000b, 001b, 010b, 011b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2500000, 2048000, 1800000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static int stm32_vrefbuf_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) ret = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) val = (val & ~STM32_HIZ) | STM32_ENVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Vrefbuf startup time depends on external capacitor: wait here for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * VRR to be set. That means output has reached expected value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * ~650us sleep should be enough for caps up to 1.5uF. Use 10ms as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * arbitrary timeout.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) val & STM32_VRR, 650, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) val = (val & ~STM32_ENVR) | STM32_HIZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pm_runtime_mark_last_busy(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pm_runtime_put_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static int stm32_vrefbuf_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val &= ~STM32_ENVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) pm_runtime_mark_last_busy(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) pm_runtime_put_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int stm32_vrefbuf_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ret = readl_relaxed(priv->base + STM32_VREFBUF_CSR) & STM32_ENVR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pm_runtime_mark_last_busy(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) pm_runtime_put_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static int stm32_vrefbuf_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) val = (val & ~STM32_VRS) | FIELD_PREP(STM32_VRS, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) writel_relaxed(val, priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pm_runtime_mark_last_busy(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) pm_runtime_put_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static int stm32_vrefbuf_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ret = pm_runtime_get_sync(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) pm_runtime_put_noidle(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val = readl_relaxed(priv->base + STM32_VREFBUF_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) ret = FIELD_GET(STM32_VRS, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) pm_runtime_mark_last_busy(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pm_runtime_put_autosuspend(priv->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct regulator_ops stm32_vrefbuf_volt_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .enable = stm32_vrefbuf_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .disable = stm32_vrefbuf_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .is_enabled = stm32_vrefbuf_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .get_voltage_sel = stm32_vrefbuf_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .set_voltage_sel = stm32_vrefbuf_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct regulator_desc stm32_vrefbuf_regu = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .name = "vref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .supply_name = "vdda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .volt_table = stm32_vrefbuf_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .n_voltages = ARRAY_SIZE(stm32_vrefbuf_voltages),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .ops = &stm32_vrefbuf_volt_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .off_on_delay = 1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int stm32_vrefbuf_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct stm32_vrefbuf *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) priv->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) priv->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (IS_ERR(priv->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return PTR_ERR(priv->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) priv->clk = devm_clk_get(&pdev->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (IS_ERR(priv->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pm_runtime_get_noresume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pm_runtime_set_active(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) pm_runtime_set_autosuspend_delay(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) STM32_VREFBUF_AUTO_SUSPEND_DELAY_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) pm_runtime_use_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) dev_err(&pdev->dev, "clk prepare failed with error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) goto err_pm_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) config.driver_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) config.of_node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) config.init_data = of_get_regulator_init_data(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) &stm32_vrefbuf_regu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) rdev = regulator_register(&stm32_vrefbuf_regu, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(&pdev->dev, "register failed with error %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) goto err_clk_dis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) platform_set_drvdata(pdev, rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pm_runtime_mark_last_busy(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) pm_runtime_put_autosuspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) err_clk_dis:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) err_pm_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static int stm32_vrefbuf_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct regulator_dev *rdev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) pm_runtime_get_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) regulator_unregister(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) pm_runtime_set_suspended(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) pm_runtime_put_noidle(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int __maybe_unused stm32_vrefbuf_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct regulator_dev *rdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static int __maybe_unused stm32_vrefbuf_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct regulator_dev *rdev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct stm32_vrefbuf *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static const struct dev_pm_ops stm32_vrefbuf_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) SET_RUNTIME_PM_OPS(stm32_vrefbuf_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) stm32_vrefbuf_runtime_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static const struct of_device_id __maybe_unused stm32_vrefbuf_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { .compatible = "st,stm32-vrefbuf", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MODULE_DEVICE_TABLE(of, stm32_vrefbuf_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct platform_driver stm32_vrefbuf_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .probe = stm32_vrefbuf_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .remove = stm32_vrefbuf_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "stm32-vrefbuf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .of_match_table = of_match_ptr(stm32_vrefbuf_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .pm = &stm32_vrefbuf_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) module_platform_driver(stm32_vrefbuf_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) MODULE_DESCRIPTION("STMicroelectronics STM32 VREFBUF driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) MODULE_ALIAS("platform:stm32-vrefbuf");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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