^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) STMicroelectronics 2019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Authors: Gabriel Fernandez <gabriel.fernandez@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Pascal Paillet <p.paillet@st.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Registers description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define REG_PWR_CR3 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define USB_3_3_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define USB_3_3_RDY BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define REG_1_8_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define REG_1_8_RDY BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define REG_1_1_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_1_1_RDY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* list of supported regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) PWR_REG11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PWR_REG18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PWR_USB33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) STM32PWR_REG_NUM_REGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u32 ready_mask_table[STM32PWR_REG_NUM_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) [PWR_REG11] = REG_1_1_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) [PWR_REG18] = REG_1_8_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [PWR_USB33] = USB_3_3_RDY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct stm32_pwr_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 ready_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int stm32_pwr_reg_is_ready(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) val = readl_relaxed(priv->base + REG_PWR_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return (val & priv->ready_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static int stm32_pwr_reg_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) val = readl_relaxed(priv->base + REG_PWR_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return (val & rdev->desc->enable_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int stm32_pwr_reg_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) val = readl_relaxed(priv->base + REG_PWR_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) val |= rdev->desc->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) writel_relaxed(val, priv->base + REG_PWR_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* use an arbitrary timeout of 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 100, 20 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) dev_err(&rdev->dev, "regulator enable timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int stm32_pwr_reg_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct stm32_pwr_reg *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) val = readl_relaxed(priv->base + REG_PWR_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) val &= ~rdev->desc->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) writel_relaxed(val, priv->base + REG_PWR_CR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* use an arbitrary timeout of 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = readx_poll_timeout(stm32_pwr_reg_is_ready, rdev, val, !val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 100, 20 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_err(&rdev->dev, "regulator disable timed out!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct regulator_ops stm32_pwr_reg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .enable = stm32_pwr_reg_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .disable = stm32_pwr_reg_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .is_enabled = stm32_pwr_reg_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PWR_REG(_id, _name, _volt, _en, _supply) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) [_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .id = _id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .name = _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .of_match = of_match_ptr(_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .fixed_uV = _volt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ops = &stm32_pwr_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .enable_mask = _en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .supply_name = _supply, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const struct regulator_desc stm32_pwr_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) PWR_REG(PWR_REG11, "reg11", 1100000, REG_1_1_EN, "vdd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PWR_REG(PWR_REG18, "reg18", 1800000, REG_1_8_EN, "vdd"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PWR_REG(PWR_USB33, "usb33", 3300000, USB_3_3_EN, "vdd_3v3_usbfs"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static int stm32_pwr_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct stm32_pwr_reg *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) base = of_iomap(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dev_err(&pdev->dev, "Unable to map IO memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) for (i = 0; i < STM32PWR_REG_NUM_REGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) priv = devm_kzalloc(&pdev->dev, sizeof(struct stm32_pwr_reg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) priv->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) priv->ready_mask = ready_mask_table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) config.driver_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) &stm32_pwr_desc[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "Failed to register regulator: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct of_device_id __maybe_unused stm32_pwr_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { .compatible = "st,stm32mp1,pwr-reg", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) MODULE_DEVICE_TABLE(of, stm32_pwr_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static struct platform_driver stm32_pwr_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .probe = stm32_pwr_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "stm32-pwr-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .of_match_table = of_match_ptr(stm32_pwr_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) module_platform_driver(stm32_pwr_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) MODULE_DESCRIPTION("STM32MP1 PWR voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_AUTHOR("Pascal Paillet <p.paillet@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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