^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SLG51000 High PSRR, Multi-Output Regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Dialog Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Eric Jeong <eric.jeong.opensource@diasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __SLG51000_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __SLG51000_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SLG51000_SYSCTL_PATN_ID_B0 0x1105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SLG51000_SYSCTL_PATN_ID_B1 0x1106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SLG51000_SYSCTL_PATN_ID_B2 0x1107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SLG51000_SYSCTL_SYS_CONF_A 0x1109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SLG51000_SYSCTL_SYS_CONF_D 0x110c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SLG51000_SYSCTL_MATRIX_CONF_A 0x110d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SLG51000_SYSCTL_MATRIX_CONF_B 0x110e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SLG51000_SYSCTL_REFGEN_CONF_C 0x1111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SLG51000_SYSCTL_UVLO_CONF_A 0x1112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SLG51000_SYSCTL_FAULT_LOG1 0x1115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SLG51000_SYSCTL_EVENT 0x1116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLG51000_SYSCTL_STATUS 0x1117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLG51000_SYSCTL_IRQ_MASK 0x1118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLG51000_IO_GPIO1_CONF 0x1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLG51000_IO_GPIO2_CONF 0x1501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SLG51000_IO_GPIO3_CONF 0x1502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SLG51000_IO_GPIO4_CONF 0x1503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SLG51000_IO_GPIO5_CONF 0x1504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLG51000_IO_GPIO6_CONF 0x1505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLG51000_IO_GPIO_STATUS 0x1506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SLG51000_LUTARRAY_LUT_VAL_0 0x1600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SLG51000_LUTARRAY_LUT_VAL_1 0x1601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLG51000_LUTARRAY_LUT_VAL_2 0x1602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLG51000_LUTARRAY_LUT_VAL_3 0x1603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SLG51000_LUTARRAY_LUT_VAL_4 0x1604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SLG51000_LUTARRAY_LUT_VAL_5 0x1605
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SLG51000_LUTARRAY_LUT_VAL_6 0x1606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SLG51000_LUTARRAY_LUT_VAL_7 0x1607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLG51000_LUTARRAY_LUT_VAL_8 0x1608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SLG51000_LUTARRAY_LUT_VAL_9 0x1609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLG51000_LUTARRAY_LUT_VAL_10 0x160a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLG51000_LUTARRAY_LUT_VAL_11 0x160b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLG51000_MUXARRAY_INPUT_SEL_0 0x1700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SLG51000_MUXARRAY_INPUT_SEL_1 0x1701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLG51000_MUXARRAY_INPUT_SEL_2 0x1702
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SLG51000_MUXARRAY_INPUT_SEL_3 0x1703
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLG51000_MUXARRAY_INPUT_SEL_4 0x1704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLG51000_MUXARRAY_INPUT_SEL_5 0x1705
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLG51000_MUXARRAY_INPUT_SEL_6 0x1706
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLG51000_MUXARRAY_INPUT_SEL_7 0x1707
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLG51000_MUXARRAY_INPUT_SEL_8 0x1708
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SLG51000_MUXARRAY_INPUT_SEL_9 0x1709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLG51000_MUXARRAY_INPUT_SEL_10 0x170a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLG51000_MUXARRAY_INPUT_SEL_11 0x170b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SLG51000_MUXARRAY_INPUT_SEL_12 0x170c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLG51000_MUXARRAY_INPUT_SEL_13 0x170d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLG51000_MUXARRAY_INPUT_SEL_14 0x170e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLG51000_MUXARRAY_INPUT_SEL_15 0x170f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLG51000_MUXARRAY_INPUT_SEL_16 0x1710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SLG51000_MUXARRAY_INPUT_SEL_17 0x1711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLG51000_MUXARRAY_INPUT_SEL_18 0x1712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLG51000_MUXARRAY_INPUT_SEL_19 0x1713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLG51000_MUXARRAY_INPUT_SEL_20 0x1714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLG51000_MUXARRAY_INPUT_SEL_21 0x1715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLG51000_MUXARRAY_INPUT_SEL_22 0x1716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLG51000_MUXARRAY_INPUT_SEL_23 0x1717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLG51000_MUXARRAY_INPUT_SEL_24 0x1718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLG51000_MUXARRAY_INPUT_SEL_25 0x1719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLG51000_MUXARRAY_INPUT_SEL_26 0x171a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLG51000_MUXARRAY_INPUT_SEL_27 0x171b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SLG51000_MUXARRAY_INPUT_SEL_28 0x171c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SLG51000_MUXARRAY_INPUT_SEL_29 0x171d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLG51000_MUXARRAY_INPUT_SEL_30 0x171e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SLG51000_MUXARRAY_INPUT_SEL_31 0x171f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SLG51000_MUXARRAY_INPUT_SEL_32 0x1720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SLG51000_MUXARRAY_INPUT_SEL_33 0x1721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLG51000_MUXARRAY_INPUT_SEL_34 0x1722
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLG51000_MUXARRAY_INPUT_SEL_35 0x1723
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SLG51000_MUXARRAY_INPUT_SEL_36 0x1724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SLG51000_MUXARRAY_INPUT_SEL_37 0x1725
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SLG51000_MUXARRAY_INPUT_SEL_38 0x1726
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SLG51000_MUXARRAY_INPUT_SEL_39 0x1727
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLG51000_MUXARRAY_INPUT_SEL_40 0x1728
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLG51000_MUXARRAY_INPUT_SEL_41 0x1729
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SLG51000_MUXARRAY_INPUT_SEL_42 0x172a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLG51000_MUXARRAY_INPUT_SEL_43 0x172b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLG51000_MUXARRAY_INPUT_SEL_44 0x172c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLG51000_MUXARRAY_INPUT_SEL_45 0x172d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SLG51000_MUXARRAY_INPUT_SEL_46 0x172e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLG51000_MUXARRAY_INPUT_SEL_47 0x172f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SLG51000_MUXARRAY_INPUT_SEL_48 0x1730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SLG51000_MUXARRAY_INPUT_SEL_49 0x1731
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SLG51000_MUXARRAY_INPUT_SEL_50 0x1732
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SLG51000_MUXARRAY_INPUT_SEL_51 0x1733
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SLG51000_MUXARRAY_INPUT_SEL_52 0x1734
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SLG51000_MUXARRAY_INPUT_SEL_53 0x1735
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SLG51000_MUXARRAY_INPUT_SEL_54 0x1736
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SLG51000_MUXARRAY_INPUT_SEL_55 0x1737
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SLG51000_MUXARRAY_INPUT_SEL_56 0x1738
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SLG51000_MUXARRAY_INPUT_SEL_57 0x1739
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLG51000_MUXARRAY_INPUT_SEL_58 0x173a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SLG51000_MUXARRAY_INPUT_SEL_59 0x173b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SLG51000_MUXARRAY_INPUT_SEL_60 0x173c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SLG51000_MUXARRAY_INPUT_SEL_61 0x173d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SLG51000_MUXARRAY_INPUT_SEL_62 0x173e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SLG51000_MUXARRAY_INPUT_SEL_63 0x173f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SLG51000_PWRSEQ_RESOURCE_EN_0 0x1900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SLG51000_PWRSEQ_RESOURCE_EN_1 0x1901
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SLG51000_PWRSEQ_RESOURCE_EN_2 0x1902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SLG51000_PWRSEQ_RESOURCE_EN_3 0x1903
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SLG51000_PWRSEQ_RESOURCE_EN_4 0x1904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SLG51000_PWRSEQ_RESOURCE_EN_5 0x1905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 0x1906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 0x1907
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP1 0x1908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN1 0x1909
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP2 0x190a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN2 0x190b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP3 0x190c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN3 0x190d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP4 0x190e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN4 0x190f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5 0x1910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5 0x1911
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A 0x1912
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_B 0x1913
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C 0x1914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_A 0x1915
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SLG51000_PWRSEQ_INPUT_SENSE_CONF_B 0x1916
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define SLG51000_LDO1_VSEL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define SLG51000_LDO1_MINV 0x2060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define SLG51000_LDO1_MAXV 0x2061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define SLG51000_LDO1_MISC1 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SLG51000_LDO1_VSEL_ACTUAL 0x2065
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SLG51000_LDO1_EVENT 0x20c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SLG51000_LDO1_STATUS 0x20c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SLG51000_LDO1_IRQ_MASK 0x20c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SLG51000_LDO2_VSEL 0x2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SLG51000_LDO2_MINV 0x2260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SLG51000_LDO2_MAXV 0x2261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SLG51000_LDO2_MISC1 0x2264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SLG51000_LDO2_VSEL_ACTUAL 0x2265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SLG51000_LDO2_EVENT 0x22c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SLG51000_LDO2_STATUS 0x22c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SLG51000_LDO2_IRQ_MASK 0x22c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SLG51000_LDO3_VSEL 0x2300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SLG51000_LDO3_MINV 0x2360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SLG51000_LDO3_MAXV 0x2361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SLG51000_LDO3_CONF1 0x2364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define SLG51000_LDO3_CONF2 0x2365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define SLG51000_LDO3_VSEL_ACTUAL 0x2366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SLG51000_LDO3_EVENT 0x23c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SLG51000_LDO3_STATUS 0x23c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define SLG51000_LDO3_IRQ_MASK 0x23c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SLG51000_LDO4_VSEL 0x2500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define SLG51000_LDO4_MINV 0x2560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SLG51000_LDO4_MAXV 0x2561
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define SLG51000_LDO4_CONF1 0x2564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SLG51000_LDO4_CONF2 0x2565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define SLG51000_LDO4_VSEL_ACTUAL 0x2566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SLG51000_LDO4_EVENT 0x25c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SLG51000_LDO4_STATUS 0x25c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SLG51000_LDO4_IRQ_MASK 0x25c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SLG51000_LDO5_VSEL 0x2700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SLG51000_LDO5_MINV 0x2760
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SLG51000_LDO5_MAXV 0x2761
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SLG51000_LDO5_TRIM2 0x2763
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SLG51000_LDO5_CONF1 0x2765
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SLG51000_LDO5_CONF2 0x2766
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SLG51000_LDO5_VSEL_ACTUAL 0x2767
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SLG51000_LDO5_EVENT 0x27c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SLG51000_LDO5_STATUS 0x27c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SLG51000_LDO5_IRQ_MASK 0x27c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SLG51000_LDO6_VSEL 0x2900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SLG51000_LDO6_MINV 0x2960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SLG51000_LDO6_MAXV 0x2961
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SLG51000_LDO6_TRIM2 0x2963
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define SLG51000_LDO6_CONF1 0x2965
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SLG51000_LDO6_CONF2 0x2966
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SLG51000_LDO6_VSEL_ACTUAL 0x2967
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SLG51000_LDO6_EVENT 0x29c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SLG51000_LDO6_STATUS 0x29c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SLG51000_LDO6_IRQ_MASK 0x29c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SLG51000_LDO7_VSEL 0x3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SLG51000_LDO7_MINV 0x3160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SLG51000_LDO7_MAXV 0x3161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SLG51000_LDO7_CONF1 0x3164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SLG51000_LDO7_CONF2 0x3165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SLG51000_LDO7_VSEL_ACTUAL 0x3166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SLG51000_LDO7_EVENT 0x31c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SLG51000_LDO7_STATUS 0x31c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SLG51000_LDO7_IRQ_MASK 0x31c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SLG51000_OTP_EVENT 0x782b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SLG51000_OTP_IRQ_MASK 0x782d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SLG51000_OTP_LOCK_OTP_PROG 0x78fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SLG51000_OTP_LOCK_CTRL 0x78ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SLG51000_LOCK_GLOBAL_LOCK_CTRL1 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Register Bit Fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* SLG51000_SYSCTL_PATTERN_ID_BYTE0 = 0x1105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SLG51000_PATTERN_ID_BYTE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SLG51000_PATTERN_ID_BYTE0_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* SLG51000_SYSCTL_PATTERN_ID_BYTE1 = 0x1106 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SLG51000_PATTERN_ID_BYTE1_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SLG51000_PATTERN_ID_BYTE1_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* SLG51000_SYSCTL_PATTERN_ID_BYTE2 = 0x1107 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SLG51000_PATTERN_ID_BYTE2_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SLG51000_PATTERN_ID_BYTE2_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* SLG51000_SYSCTL_SYS_CONF_A = 0x1109 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SLG51000_I2C_ADDRESS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SLG51000_I2C_ADDRESS_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define SLG51000_I2C_DISABLE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SLG51000_I2C_DISABLE_MASK (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* SLG51000_SYSCTL_SYS_CONF_D = 0x110c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SLG51000_CS_T_DEB_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SLG51000_CS_T_DEB_MASK (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define SLG51000_I2C_CLR_MODE_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SLG51000_I2C_CLR_MODE_MASK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_A = 0x110d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SLG51000_RESOURCE_CTRL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define SLG51000_RESOURCE_CTRL_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* SLG51000_SYSCTL_MATRIX_CTRL_CONF_B = 0x110e */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SLG51000_MATRIX_EVENT_SENSE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SLG51000_MATRIX_EVENT_SENSE_MASK (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* SLG51000_SYSCTL_REFGEN_CONF_C = 0x1111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define SLG51000_REFGEN_SEL_TEMP_WARN_DEBOUNCE_MASK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define SLG51000_REFGEN_SEL_TEMP_WARN_THR_MASK (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* SLG51000_SYSCTL_UVLO_CONF_A = 0x1112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define SLG51000_VMON_UVLO_SEL_THR_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define SLG51000_VMON_UVLO_SEL_THR_MASK (0x1f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* SLG51000_SYSCTL_FAULT_LOG1 = 0x1115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SLG51000_FLT_POR_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define SLG51000_FLT_POR_MASK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define SLG51000_FLT_RST_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SLG51000_FLT_RST_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SLG51000_FLT_OVER_TEMP_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SLG51000_FLT_OVER_TEMP_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* SLG51000_SYSCTL_EVENT = 0x1116 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SLG51000_EVT_MATRIX_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SLG51000_EVT_MATRIX_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SLG51000_EVT_HIGH_TEMP_WARN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SLG51000_EVT_HIGH_TEMP_WARN_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* SLG51000_SYSCTL_STATUS = 0x1117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SLG51000_STA_MATRIX_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SLG51000_STA_MATRIX_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SLG51000_STA_HIGH_TEMP_WARN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SLG51000_STA_HIGH_TEMP_WARN_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* SLG51000_SYSCTL_IRQ_MASK = 0x1118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define SLG51000_IRQ_MATRIX_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SLG51000_IRQ_MATRIX_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SLG51000_IRQ_HIGH_TEMP_WARN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define SLG51000_IRQ_HIGH_TEMP_WARN_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* SLG51000_IO_GPIO1_CONF ~ SLG51000_IO_GPIO5_CONF =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 0x1500, 0x1501, 0x1502, 0x1503, 0x1504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SLG51000_GPIO_DIR_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SLG51000_GPIO_DIR_MASK (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SLG51000_GPIO_SENS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SLG51000_GPIO_SENS_MASK (0x03 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SLG51000_GPIO_INVERT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define SLG51000_GPIO_INVERT_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SLG51000_GPIO_BYP_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SLG51000_GPIO_BYP_MASK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SLG51000_GPIO_T_DEB_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SLG51000_GPIO_T_DEB_MASK (0x03 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SLG51000_GPIO_LEVEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define SLG51000_GPIO_LEVEL_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* SLG51000_IO_GPIO6_CONF = 0x1505 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define SLG51000_GPIO6_SENS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define SLG51000_GPIO6_SENS_MASK (0x03 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SLG51000_GPIO6_INVERT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define SLG51000_GPIO6_INVERT_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define SLG51000_GPIO6_T_DEB_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define SLG51000_GPIO6_T_DEB_MASK (0x03 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define SLG51000_GPIO6_LEVEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define SLG51000_GPIO6_LEVEL_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* SLG51000_IO_GPIO_STATUS = 0x1506 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define SLG51000_GPIO6_STATUS_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define SLG51000_GPIO6_STATUS_MASK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define SLG51000_GPIO5_STATUS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define SLG51000_GPIO5_STATUS_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SLG51000_GPIO4_STATUS_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define SLG51000_GPIO4_STATUS_MASK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define SLG51000_GPIO3_STATUS_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define SLG51000_GPIO3_STATUS_MASK (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define SLG51000_GPIO2_STATUS_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define SLG51000_GPIO2_STATUS_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SLG51000_GPIO1_STATUS_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SLG51000_GPIO1_STATUS_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* SLG51000_LUTARRAY_LUT_VAL_0 ~ SLG51000_LUTARRAY_LUT_VAL_11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * 0x1600, 0x1601, 0x1602, 0x1603, 0x1604, 0x1605,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * 0x1606, 0x1607, 0x1608, 0x1609, 0x160a, 0x160b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define SLG51000_LUT_VAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SLG51000_LUT_VAL_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* SLG51000_MUXARRAY_INPUT_SEL_0 ~ SLG51000_MUXARRAY_INPUT_SEL_63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * 0x1700, 0x1701, 0x1702, 0x1703, 0x1704, 0x1705,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * 0x1706, 0x1707, 0x1708, 0x1709, 0x170a, 0x170b,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * 0x170c, 0x170d, 0x170e, 0x170f, 0x1710, 0x1711,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * 0x1712, 0x1713, 0x1714, 0x1715, 0x1716, 0x1717,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * 0x1718, 0x1719, 0x171a, 0x171b, 0x171c, 0x171d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 0x171e, 0x171f, 0x1720, 0x1721, 0x1722, 0x1723,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * 0x1724, 0x1725, 0x1726, 0x1727, 0x1728, 0x1729,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 0x173a, 0x173b, 0x173c, 0x173d, 0x173e, 0x173f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define SLG51000_INPUT_SEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define SLG51000_INPUT_SEL_MASK (0x3f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* SLG51000_PWRSEQ_RESOURCE_EN_0 ~ SLG51000_PWRSEQ_RESOURCE_EN_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * 0x1900, 0x1901, 0x1902, 0x1903, 0x1904, 0x1905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SLG51000_RESOURCE_EN_DOWN0_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define SLG51000_RESOURCE_EN_DOWN0_MASK (0x07 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define SLG51000_RESOURCE_EN_UP0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SLG51000_RESOURCE_EN_UP0_MASK (0x07 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* SLG51000_PWRSEQ_SLOT_TIME_MIN_UP0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_UP5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * 0x1906, 0x1908, 0x190a, 0x190c, 0x190e, 0x1910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define SLG51000_SLOT_TIME_MIN_UP_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SLG51000_SLOT_TIME_MIN_UP_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN0 ~ SLG51000_PWRSEQ_SLOT_TIME_MIN_DOWN5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * 0x1907, 0x1909, 0x190b, 0x190d, 0x190f, 0x1911
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define SLG51000_SLOT_TIME_MIN_DOWN_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define SLG51000_SLOT_TIME_MIN_DOWN_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_A ~ SLG51000_PWRSEQ_SLOT_TIME_MAX_CONF_C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * 0x1912, 0x1913, 0x1914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define SLG51000_SLOT_TIME_MAX_DOWN1_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define SLG51000_SLOT_TIME_MAX_DOWN1_MASK (0x03 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SLG51000_SLOT_TIME_MAX_UP1_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define SLG51000_SLOT_TIME_MAX_UP1_MASK (0x03 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define SLG51000_SLOT_TIME_MAX_DOWN0_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SLG51000_SLOT_TIME_MAX_DOWN0_MASK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SLG51000_SLOT_TIME_MAX_UP0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SLG51000_SLOT_TIME_MAX_UP0_MASK (0x03 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_A = 0x1915 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SLG51000_TRIG_UP_SENSE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SLG51000_TRIG_UP_SENSE_MASK (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SLG51000_UP_EN_SENSE5_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SLG51000_UP_EN_SENSE5_MASK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SLG51000_UP_EN_SENSE4_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SLG51000_UP_EN_SENSE4_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SLG51000_UP_EN_SENSE3_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SLG51000_UP_EN_SENSE3_MASK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SLG51000_UP_EN_SENSE2_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define SLG51000_UP_EN_SENSE2_MASK (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define SLG51000_UP_EN_SENSE1_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SLG51000_UP_EN_SENSE1_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SLG51000_UP_EN_SENSE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SLG51000_UP_EN_SENSE0_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* SLG51000_PWRSEQ_INPUT_SENSE_CONF_B = 0x1916 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SLG51000_CRASH_DETECT_SENSE_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SLG51000_CRASH_DETECT_SENSE_MASK (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SLG51000_TRIG_DOWN_SENSE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SLG51000_TRIG_DOWN_SENSE_MASK (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define SLG51000_DOWN_EN_SENSE5_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define SLG51000_DOWN_EN_SENSE5_MASK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define SLG51000_DOWN_EN_SENSE4_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define SLG51000_DOWN_EN_SENSE4_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SLG51000_DOWN_EN_SENSE3_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SLG51000_DOWN_EN_SENSE3_MASK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SLG51000_DOWN_EN_SENSE2_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SLG51000_DOWN_EN_SENSE2_MASK (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SLG51000_DOWN_EN_SENSE1_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SLG51000_DOWN_EN_SENSE1_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SLG51000_DOWN_EN_SENSE0_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SLG51000_DOWN_EN_SENSE0_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* SLG51000_LDO1_VSEL ~ SLG51000_LDO7_VSEL =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * 0x2000, 0x2200, 0x2300, 0x2500, 0x2700, 0x2900, 0x3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SLG51000_VSEL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SLG51000_VSEL_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* SLG51000_LDO1_MINV ~ SLG51000_LDO7_MINV =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * 0x2060, 0x2260, 0x2360, 0x2560, 0x2760, 0x2960, 0x3160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SLG51000_MINV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SLG51000_MINV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /* SLG51000_LDO1_MAXV ~ SLG51000_LDO7_MAXV =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * 0x2061, 0x2261, 0x2361, 0x2561, 0x2761, 0x2961, 0x3161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SLG51000_MAXV_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SLG51000_MAXV_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* SLG51000_LDO1_MISC1 = 0x2064, SLG51000_LDO2_MISC1 = 0x2264 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SLG51000_SEL_VRANGE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SLG51000_SEL_VRANGE_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* SLG51000_LDO1_VSEL_ACTUAL ~ SLG51000_LDO7_VSEL_ACTUAL =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * 0x2065, 0x2265, 0x2366, 0x2566, 0x2767, 0x2967, 0x3166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SLG51000_VSEL_ACTUAL_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SLG51000_VSEL_ACTUAL_MASK (0xff << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* SLG51000_LDO1_EVENT ~ SLG51000_LDO7_EVENT =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * 0x20c0, 0x22c0, 0x23c0, 0x25c0, 0x27c0, 0x29c0, 0x31c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SLG51000_EVT_ILIM_FLAG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SLG51000_EVT_ILIM_FLAG_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SLG51000_EVT_VOUT_OK_FLAG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SLG51000_EVT_VOUT_OK_FLAG_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) /* SLG51000_LDO1_STATUS ~ SLG51000_LDO7_STATUS =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * 0x20c1, 0x22c1, 0x23c1, 0x25c1, 0x27c1, 0x29c1, 0x31c1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define SLG51000_STA_ILIM_FLAG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define SLG51000_STA_ILIM_FLAG_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SLG51000_STA_VOUT_OK_FLAG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SLG51000_STA_VOUT_OK_FLAG_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* SLG51000_LDO1_IRQ_MASK ~ SLG51000_LDO7_IRQ_MASK =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * 0x20c2, 0x22c2, 0x23c2, 0x25c2, 0x27c2, 0x29c2, 0x31c2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SLG51000_IRQ_ILIM_FLAG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SLG51000_IRQ_ILIM_FLAG_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* SLG51000_LDO3_CONF1 ~ SLG51000_LDO7_CONF1 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * 0x2364, 0x2564, 0x2765, 0x2965, 0x3164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SLG51000_SEL_START_ILIM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SLG51000_SEL_START_ILIM_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /* SLG51000_LDO3_CONF2 ~ SLG51000_LDO7_CONF2 =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * 0x2365, 0x2565, 0x2766, 0x2966, 0x3165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SLG51000_SEL_FUNC_ILIM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SLG51000_SEL_FUNC_ILIM_MASK (0x7f << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* SLG51000_LDO5_TRIM2 = 0x2763, SLG51000_LDO6_TRIM2 = 0x2963 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SLG51000_SEL_BYP_SLEW_RATE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SLG51000_SEL_BYP_SLEW_RATE_MASK (0x03 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SLG51000_SEL_BYP_VGATE_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SLG51000_SEL_BYP_VGATE_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SLG51000_SEL_BYP_MODE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SLG51000_SEL_BYP_MODE_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* SLG51000_OTP_EVENT = 0x782b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SLG51000_EVT_CRC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SLG51000_EVT_CRC_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* SLG51000_OTP_IRQ_MASK = 0x782d */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SLG51000_IRQ_CRC_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SLG51000_IRQ_CRC_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* SLG51000_OTP_LOCK_OTP_PROG = 0x78fe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SLG51000_LOCK_OTP_PROG_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SLG51000_LOCK_OTP_PROG_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* SLG51000_OTP_LOCK_CTRL = 0x78ff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SLG51000_LOCK_DFT_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SLG51000_LOCK_DFT_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SLG51000_LOCK_RWT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SLG51000_LOCK_RWT_MASK (0x01 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* SLG51000_LOCK_GLOBAL_LOCK_CTRL1 = 0x8000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SLG51000_LDO7_LOCK_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SLG51000_LDO7_LOCK_MASK (0x01 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SLG51000_LDO6_LOCK_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SLG51000_LDO6_LOCK_MASK (0x01 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SLG51000_LDO5_LOCK_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SLG51000_LDO5_LOCK_MASK (0x01 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SLG51000_LDO4_LOCK_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SLG51000_LDO4_LOCK_MASK (0x01 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SLG51000_LDO3_LOCK_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SLG51000_LDO3_LOCK_MASK (0x01 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SLG51000_LDO2_LOCK_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SLG51000_LDO2_LOCK_MASK (0x01 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SLG51000_LDO1_LOCK_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SLG51000_LDO1_LOCK_MASK (0x01 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #endif /* __SLG51000_REGISTERS_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags