Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // SLG51000 High PSRR, Multi-Output Regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright (C) 2019  Dialog Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) // Author: Eric Jeong <eric.jeong.opensource@diasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include "slg51000-regulator.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SLG51000_SCTL_EVT               7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SLG51000_MAX_EVT_REGISTER       8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SLG51000_LDOHP_LV_MIN           1200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SLG51000_LDOHP_HV_MIN           2400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) enum slg51000_regulators {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	SLG51000_REGULATOR_LDO1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	SLG51000_REGULATOR_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	SLG51000_REGULATOR_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	SLG51000_REGULATOR_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	SLG51000_REGULATOR_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	SLG51000_REGULATOR_LDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	SLG51000_REGULATOR_LDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	SLG51000_MAX_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct slg51000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct regulator_desc *rdesc[SLG51000_MAX_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct regulator_dev *rdev[SLG51000_MAX_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct gpio_desc *cs_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	int chip_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) struct slg51000_evt_sta {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	unsigned int ereg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	unsigned int sreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const struct slg51000_evt_sta es_reg[SLG51000_MAX_EVT_REGISTER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	{SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	{SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	{SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	{SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	{SLG51000_SYSCTL_EVENT, SLG51000_SYSCTL_STATUS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) static const struct regmap_range slg51000_writeable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	regmap_reg_range(SLG51000_SYSCTL_MATRIX_CONF_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 			 SLG51000_SYSCTL_MATRIX_CONF_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	regmap_reg_range(SLG51000_LDO1_IRQ_MASK, SLG51000_LDO1_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	regmap_reg_range(SLG51000_LDO2_IRQ_MASK, SLG51000_LDO2_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	regmap_reg_range(SLG51000_LDO3_IRQ_MASK, SLG51000_LDO3_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	regmap_reg_range(SLG51000_LDO4_IRQ_MASK, SLG51000_LDO4_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	regmap_reg_range(SLG51000_LDO5_IRQ_MASK, SLG51000_LDO5_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	regmap_reg_range(SLG51000_LDO6_IRQ_MASK, SLG51000_LDO6_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	regmap_reg_range(SLG51000_LDO7_IRQ_MASK, SLG51000_LDO7_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const struct regmap_range slg51000_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	regmap_reg_range(SLG51000_SYSCTL_PATN_ID_B0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			 SLG51000_SYSCTL_PATN_ID_B2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 			 SLG51000_SYSCTL_SYS_CONF_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	regmap_reg_range(SLG51000_SYSCTL_SYS_CONF_D,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			 SLG51000_SYSCTL_MATRIX_CONF_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	regmap_reg_range(SLG51000_SYSCTL_REFGEN_CONF_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 			 SLG51000_SYSCTL_UVLO_CONF_A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	regmap_reg_range(SLG51000_IO_GPIO1_CONF, SLG51000_IO_GPIO_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	regmap_reg_range(SLG51000_LUTARRAY_LUT_VAL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			 SLG51000_LUTARRAY_LUT_VAL_11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	regmap_reg_range(SLG51000_MUXARRAY_INPUT_SEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 			 SLG51000_MUXARRAY_INPUT_SEL_63),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	regmap_reg_range(SLG51000_PWRSEQ_RESOURCE_EN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			 SLG51000_PWRSEQ_INPUT_SENSE_CONF_B),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	regmap_reg_range(SLG51000_LDO1_VSEL, SLG51000_LDO1_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	regmap_reg_range(SLG51000_LDO1_MINV, SLG51000_LDO1_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	regmap_reg_range(SLG51000_LDO1_MISC1, SLG51000_LDO1_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	regmap_reg_range(SLG51000_LDO2_VSEL, SLG51000_LDO2_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	regmap_reg_range(SLG51000_LDO2_MINV, SLG51000_LDO2_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	regmap_reg_range(SLG51000_LDO2_MISC1, SLG51000_LDO2_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	regmap_reg_range(SLG51000_LDO3_VSEL, SLG51000_LDO3_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	regmap_reg_range(SLG51000_LDO3_MINV, SLG51000_LDO3_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	regmap_reg_range(SLG51000_LDO3_CONF1, SLG51000_LDO3_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	regmap_reg_range(SLG51000_LDO4_VSEL, SLG51000_LDO4_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	regmap_reg_range(SLG51000_LDO4_MINV, SLG51000_LDO4_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	regmap_reg_range(SLG51000_LDO4_CONF1, SLG51000_LDO4_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	regmap_reg_range(SLG51000_LDO5_VSEL, SLG51000_LDO5_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	regmap_reg_range(SLG51000_LDO5_MINV, SLG51000_LDO5_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	regmap_reg_range(SLG51000_LDO5_TRIM2, SLG51000_LDO5_TRIM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	regmap_reg_range(SLG51000_LDO5_CONF1, SLG51000_LDO5_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	regmap_reg_range(SLG51000_LDO6_VSEL, SLG51000_LDO6_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	regmap_reg_range(SLG51000_LDO6_MINV, SLG51000_LDO6_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	regmap_reg_range(SLG51000_LDO6_TRIM2, SLG51000_LDO6_TRIM2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	regmap_reg_range(SLG51000_LDO6_CONF1, SLG51000_LDO6_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	regmap_reg_range(SLG51000_LDO7_VSEL, SLG51000_LDO7_VSEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	regmap_reg_range(SLG51000_LDO7_MINV, SLG51000_LDO7_MAXV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	regmap_reg_range(SLG51000_LDO7_CONF1, SLG51000_LDO7_VSEL_ACTUAL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	regmap_reg_range(SLG51000_OTP_IRQ_MASK, SLG51000_OTP_IRQ_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	regmap_reg_range(SLG51000_OTP_LOCK_OTP_PROG, SLG51000_OTP_LOCK_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	regmap_reg_range(SLG51000_LOCK_GLOBAL_LOCK_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			 SLG51000_LOCK_GLOBAL_LOCK_CTRL1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct regmap_range slg51000_volatile_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	regmap_reg_range(SLG51000_SYSCTL_FAULT_LOG1, SLG51000_SYSCTL_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	regmap_reg_range(SLG51000_IO_GPIO_STATUS, SLG51000_IO_GPIO_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	regmap_reg_range(SLG51000_LDO1_EVENT, SLG51000_LDO1_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	regmap_reg_range(SLG51000_LDO2_EVENT, SLG51000_LDO2_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	regmap_reg_range(SLG51000_LDO3_EVENT, SLG51000_LDO3_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	regmap_reg_range(SLG51000_LDO4_EVENT, SLG51000_LDO4_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	regmap_reg_range(SLG51000_LDO5_EVENT, SLG51000_LDO5_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	regmap_reg_range(SLG51000_LDO6_EVENT, SLG51000_LDO6_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	regmap_reg_range(SLG51000_LDO7_EVENT, SLG51000_LDO7_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	regmap_reg_range(SLG51000_OTP_EVENT, SLG51000_OTP_EVENT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct regmap_access_table slg51000_writeable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.yes_ranges	= slg51000_writeable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.n_yes_ranges	= ARRAY_SIZE(slg51000_writeable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const struct regmap_access_table slg51000_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.yes_ranges	= slg51000_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.n_yes_ranges	= ARRAY_SIZE(slg51000_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct regmap_access_table slg51000_volatile_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	.yes_ranges	= slg51000_volatile_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.n_yes_ranges	= ARRAY_SIZE(slg51000_volatile_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct regmap_config slg51000_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.reg_bits = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.max_register = 0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.wr_table = &slg51000_writeable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.rd_table = &slg51000_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.volatile_table = &slg51000_volatile_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct regulator_ops slg51000_regl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct regulator_ops slg51000_switch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int slg51000_of_parse_cb(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 				const struct regulator_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 				struct regulator_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	struct gpio_desc *ena_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	ena_gpiod = fwnode_gpiod_get_index(of_fwnode_handle(np), "enable", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 					   GPIOD_OUT_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 						GPIOD_FLAGS_BIT_NONEXCLUSIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					   "gpio-en-ldo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	if (!IS_ERR(ena_gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		config->ena_gpiod = ena_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SLG51000_REGL_DESC(_id, _name, _s_name, _min, _step) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	[SLG51000_REGULATOR_##_id] = {                             \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 		.name = #_name,                                    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		.supply_name = _s_name,				   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		.id = SLG51000_REGULATOR_##_id,                    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		.of_match = of_match_ptr(#_name),                  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		.of_parse_cb = slg51000_of_parse_cb,               \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		.ops = &slg51000_regl_ops,                         \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		.regulators_node = of_match_ptr("regulators"),     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		.n_voltages = 256,                                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.min_uV = _min,                                    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.uV_step = _step,                                  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.linear_min_sel = 0,                               \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.vsel_mask = SLG51000_VSEL_MASK,                   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.vsel_reg = SLG51000_##_id##_VSEL,                 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.enable_reg = SLG51000_SYSCTL_MATRIX_CONF_A,       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.enable_mask = BIT(SLG51000_REGULATOR_##_id),      \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.type = REGULATOR_VOLTAGE,                         \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.owner = THIS_MODULE,                              \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static struct regulator_desc regls_desc[SLG51000_MAX_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	SLG51000_REGL_DESC(LDO1, ldo1, NULL,   2400000,  5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	SLG51000_REGL_DESC(LDO2, ldo2, NULL,   2400000,  5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	SLG51000_REGL_DESC(LDO3, ldo3, "vin3", 1200000, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	SLG51000_REGL_DESC(LDO4, ldo4, "vin4", 1200000, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	SLG51000_REGL_DESC(LDO5, ldo5, "vin5",  400000,  5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	SLG51000_REGL_DESC(LDO6, ldo6, "vin6",  400000,  5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	SLG51000_REGL_DESC(LDO7, ldo7, "vin7", 1200000, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static int slg51000_regulator_init(struct slg51000 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	struct regulator_desc *rdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	unsigned int reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	u8 vsel_range[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	int id, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	const unsigned int min_regs[SLG51000_MAX_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 		SLG51000_LDO1_MINV, SLG51000_LDO2_MINV, SLG51000_LDO3_MINV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		SLG51000_LDO4_MINV, SLG51000_LDO5_MINV, SLG51000_LDO6_MINV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		SLG51000_LDO7_MINV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	for (id = 0; id < SLG51000_MAX_REGULATORS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		chip->rdesc[id] = &regls_desc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		rdesc = chip->rdesc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		config.regmap = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		config.dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		config.driver_data = chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		ret = regmap_bulk_read(chip->regmap, min_regs[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				       vsel_range, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 				"Failed to read the MIN register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		case SLG51000_REGULATOR_LDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		case SLG51000_REGULATOR_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			if (id == SLG51000_REGULATOR_LDO1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				reg = SLG51000_LDO1_MISC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 				reg = SLG51000_LDO2_MISC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			ret = regmap_read(chip->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 				dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 					"Failed to read voltage range of ldo%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 					id + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			rdesc->linear_min_sel = vsel_range[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			rdesc->n_voltages = vsel_range[1] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			if (val & SLG51000_SEL_VRANGE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				rdesc->min_uV = SLG51000_LDOHP_HV_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 						+ (vsel_range[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 						   * rdesc->uV_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 				rdesc->min_uV = SLG51000_LDOHP_LV_MIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 						+ (vsel_range[0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 						   * rdesc->uV_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		case SLG51000_REGULATOR_LDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		case SLG51000_REGULATOR_LDO6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			if (id == SLG51000_REGULATOR_LDO5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				reg = SLG51000_LDO5_TRIM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 				reg = SLG51000_LDO6_TRIM2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 			ret = regmap_read(chip->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 			if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 				dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					"Failed to read LDO mode register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			if (val & SLG51000_SEL_BYP_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 				rdesc->ops = &slg51000_switch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 				rdesc->n_voltages = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				rdesc->min_uV = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 				rdesc->uV_step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				rdesc->linear_min_sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			fallthrough;	/* to the check below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 			rdesc->linear_min_sel = vsel_range[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 			rdesc->n_voltages = vsel_range[1] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			rdesc->min_uV = rdesc->min_uV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 					+ (vsel_range[0] * rdesc->uV_step);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		chip->rdev[id] = devm_regulator_register(chip->dev, rdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 							 &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		if (IS_ERR(chip->rdev[id])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 			ret = PTR_ERR(chip->rdev[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 				"Failed to register regulator(%s):%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				chip->rdesc[id]->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static irqreturn_t slg51000_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct slg51000 *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct regmap *regmap = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	enum { R0 = 0, R1, R2, REG_MAX };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	u8 evt[SLG51000_MAX_EVT_REGISTER][REG_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	int ret, i, handled = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	unsigned int evt_otp, mask_otp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* Read event[R0], status[R1] and mask[R2] register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	for (i = 0; i < SLG51000_MAX_EVT_REGISTER; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		ret = regmap_bulk_read(regmap, es_reg[i].ereg, evt[i], REG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				"Failed to read event registers(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	ret = regmap_read(regmap, SLG51000_OTP_EVENT, &evt_otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			"Failed to read otp event registers(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ret = regmap_read(regmap, SLG51000_OTP_IRQ_MASK, &mask_otp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 			"Failed to read otp mask register(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	if ((evt_otp & SLG51000_EVT_CRC_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	    !(mask_otp & SLG51000_IRQ_CRC_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		dev_info(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			 "OTP has been read or OTP crc is not zero\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		if (!(evt[i][R2] & SLG51000_IRQ_ILIM_FLAG_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		    (evt[i][R0] & SLG51000_EVT_ILIM_FLAG_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			regulator_notifier_call_chain(chip->rdev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 					    REGULATOR_EVENT_OVER_CURRENT, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			if (evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 				dev_warn(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 					 "Over-current limit(ldo%d)\n", i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (!(evt[SLG51000_SCTL_EVT][R2] & SLG51000_IRQ_HIGH_TEMP_WARN_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	    (evt[SLG51000_SCTL_EVT][R0] & SLG51000_EVT_HIGH_TEMP_WARN_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		for (i = 0; i < SLG51000_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 			if (!(evt[i][R1] & SLG51000_STA_ILIM_FLAG_MASK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 			    (evt[i][R1] & SLG51000_STA_VOUT_OK_FLAG_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 				regulator_notifier_call_chain(chip->rdev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 					       REGULATOR_EVENT_OVER_TEMP, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		handled = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		if (evt[SLG51000_SCTL_EVT][R1] &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		    SLG51000_STA_HIGH_TEMP_WARN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			dev_warn(chip->dev, "High temperature warning!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void slg51000_clear_fault_log(struct slg51000 *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	ret = regmap_read(chip->regmap, SLG51000_SYSCTL_FAULT_LOG1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		dev_err(chip->dev, "Failed to read Fault log register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	if (val & SLG51000_FLT_OVER_TEMP_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		dev_dbg(chip->dev, "Fault log: FLT_OVER_TEMP\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	if (val & SLG51000_FLT_POWER_SEQ_CRASH_REQ_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 		dev_dbg(chip->dev, "Fault log: FLT_POWER_SEQ_CRASH_REQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	if (val & SLG51000_FLT_RST_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		dev_dbg(chip->dev, "Fault log: FLT_RST\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (val & SLG51000_FLT_POR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		dev_dbg(chip->dev, "Fault log: FLT_POR\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int slg51000_i2c_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	struct slg51000 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	struct gpio_desc *cs_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	int error, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	chip = devm_kzalloc(dev, sizeof(struct slg51000), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	cs_gpiod = devm_gpiod_get_optional(dev, "dlg,cs",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 					   GPIOD_OUT_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 						GPIOD_FLAGS_BIT_NONEXCLUSIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	if (IS_ERR(cs_gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		return PTR_ERR(cs_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	if (cs_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		dev_info(dev, "Found chip selector property\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		chip->cs_gpiod = cs_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	i2c_set_clientdata(client, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	chip->chip_irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	chip->regmap = devm_regmap_init_i2c(client, &slg51000_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (IS_ERR(chip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		error = PTR_ERR(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		dev_err(dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 			error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	ret = slg51000_regulator_init(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		dev_err(chip->dev, "Failed to init regulator(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	slg51000_clear_fault_log(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	if (chip->chip_irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		ret = devm_request_threaded_irq(dev, chip->chip_irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 						slg51000_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 						(IRQF_TRIGGER_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 						IRQF_ONESHOT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 						"slg51000-irq", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 			dev_err(dev, "Failed to request IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 				chip->chip_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		dev_info(dev, "No IRQ configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static const struct i2c_device_id slg51000_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	{"slg51000", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) MODULE_DEVICE_TABLE(i2c, slg51000_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static struct i2c_driver slg51000_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		.name = "slg51000-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	.probe_new = slg51000_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	.id_table = slg51000_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) module_i2c_driver(slg51000_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) MODULE_DESCRIPTION("SLG51000 regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)