Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1)  //SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2017 Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * SC2731 regulator lock register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SC2731_PWR_WR_PROT		0xf0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SC2731_WR_UNLOCK_VALUE		0x6e7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * SC2731 enable register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SC2731_POWER_PD_SW		0xc28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SC2731_LDO_CAMA0_PD		0xcfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SC2731_LDO_CAMA1_PD		0xd04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SC2731_LDO_CAMMOT_PD		0xd0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SC2731_LDO_VLDO_PD		0xd6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SC2731_LDO_EMMCCORE_PD		0xd2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SC2731_LDO_SDCORE_PD		0xd74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SC2731_LDO_SDIO_PD		0xd70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SC2731_LDO_WIFIPA_PD		0xd4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SC2731_LDO_USB33_PD		0xd5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SC2731_LDO_CAMD0_PD		0xd7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SC2731_LDO_CAMD1_PD		0xd84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SC2731_LDO_CON_PD		0xd8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SC2731_LDO_CAMIO_PD		0xd94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SC2731_LDO_SRAM_PD		0xd78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * SC2731 enable mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SC2731_DCDC_CPU0_PD_MASK	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SC2731_DCDC_CPU1_PD_MASK	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SC2731_DCDC_RF_PD_MASK		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SC2731_LDO_CAMA0_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SC2731_LDO_CAMA1_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SC2731_LDO_CAMMOT_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SC2731_LDO_VLDO_PD_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SC2731_LDO_EMMCCORE_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SC2731_LDO_SDCORE_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SC2731_LDO_SDIO_PD_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SC2731_LDO_WIFIPA_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SC2731_LDO_USB33_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SC2731_LDO_CAMD0_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SC2731_LDO_CAMD1_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SC2731_LDO_CON_PD_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SC2731_LDO_CAMIO_PD_MASK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SC2731_LDO_SRAM_PD_MASK		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * SC2731 vsel register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SC2731_DCDC_CPU0_VOL		0xc54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SC2731_DCDC_CPU1_VOL		0xc64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SC2731_DCDC_RF_VOL		0xcb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SC2731_LDO_CAMA0_VOL		0xd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SC2731_LDO_CAMA1_VOL		0xd08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SC2731_LDO_CAMMOT_VOL		0xd10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SC2731_LDO_VLDO_VOL		0xd28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SC2731_LDO_EMMCCORE_VOL		0xd30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SC2731_LDO_SDCORE_VOL		0xd38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SC2731_LDO_SDIO_VOL		0xd40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SC2731_LDO_WIFIPA_VOL		0xd50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SC2731_LDO_USB33_VOL		0xd60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SC2731_LDO_CAMD0_VOL		0xd80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SC2731_LDO_CAMD1_VOL		0xd88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SC2731_LDO_CON_VOL		0xd90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SC2731_LDO_CAMIO_VOL		0xd98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SC2731_LDO_SRAM_VOL		0xdB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81)  * SC2731 vsel register mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define SC2731_DCDC_CPU0_VOL_MASK	GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define SC2731_DCDC_CPU1_VOL_MASK	GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define SC2731_DCDC_RF_VOL_MASK		GENMASK(8, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define SC2731_LDO_CAMA0_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define SC2731_LDO_CAMA1_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define SC2731_LDO_CAMMOT_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SC2731_LDO_VLDO_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define SC2731_LDO_EMMCCORE_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define SC2731_LDO_SDCORE_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define SC2731_LDO_SDIO_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define SC2731_LDO_WIFIPA_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define SC2731_LDO_USB33_VOL_MASK	GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define SC2731_LDO_CAMD0_VOL_MASK	GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define SC2731_LDO_CAMD1_VOL_MASK	GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define SC2731_LDO_CON_VOL_MASK		GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define SC2731_LDO_CAMIO_VOL_MASK	GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define SC2731_LDO_SRAM_VOL_MASK	GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) enum sc2731_regulator_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	SC2731_BUCK_CPU0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	SC2731_BUCK_CPU1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	SC2731_BUCK_RF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	SC2731_LDO_CAMA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	SC2731_LDO_CAMA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	SC2731_LDO_CAMMOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	SC2731_LDO_VLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	SC2731_LDO_EMMCCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	SC2731_LDO_SDCORE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	SC2731_LDO_SDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	SC2731_LDO_WIFIPA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	SC2731_LDO_USB33,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	SC2731_LDO_CAMD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	SC2731_LDO_CAMD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	SC2731_LDO_CON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	SC2731_LDO_CAMIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	SC2731_LDO_SRAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct regulator_ops sc2731_regu_linear_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SC2731_REGU_LINEAR(_id, en_reg, en_mask, vreg, vmask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			  vstep, vmin, vmax) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	.name			= #_id,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	.of_match		= of_match_ptr(#_id),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	.ops			= &sc2731_regu_linear_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	.type			= REGULATOR_VOLTAGE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.id			= SC2731_##_id,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.owner			= THIS_MODULE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	.min_uV			= vmin,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	.n_voltages		= ((vmax) - (vmin)) / (vstep) + 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.uV_step		= vstep,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.enable_is_inverted	= true,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.enable_val		= 0,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.enable_reg		= en_reg,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.enable_mask		= en_mask,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.vsel_reg		= vreg,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.vsel_mask		= vmask,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct regulator_desc regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	SC2731_REGU_LINEAR(BUCK_CPU0, SC2731_POWER_PD_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			   SC2731_DCDC_CPU0_PD_MASK, SC2731_DCDC_CPU0_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			   SC2731_DCDC_CPU0_VOL_MASK, 3125, 400000, 1996875),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	SC2731_REGU_LINEAR(BUCK_CPU1, SC2731_POWER_PD_SW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			   SC2731_DCDC_CPU1_PD_MASK, SC2731_DCDC_CPU1_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			   SC2731_DCDC_CPU1_VOL_MASK, 3125, 400000, 1996875),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	SC2731_REGU_LINEAR(BUCK_RF, SC2731_POWER_PD_SW, SC2731_DCDC_RF_PD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			   SC2731_DCDC_RF_VOL, SC2731_DCDC_RF_VOL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			   3125, 600000, 2196875),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	SC2731_REGU_LINEAR(LDO_CAMA0, SC2731_LDO_CAMA0_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			   SC2731_LDO_CAMA0_PD_MASK, SC2731_LDO_CAMA0_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			   SC2731_LDO_CAMA0_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	SC2731_REGU_LINEAR(LDO_CAMA1, SC2731_LDO_CAMA1_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			   SC2731_LDO_CAMA1_PD_MASK, SC2731_LDO_CAMA1_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			   SC2731_LDO_CAMA1_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	SC2731_REGU_LINEAR(LDO_CAMMOT, SC2731_LDO_CAMMOT_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			   SC2731_LDO_CAMMOT_PD_MASK, SC2731_LDO_CAMMOT_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			   SC2731_LDO_CAMMOT_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	SC2731_REGU_LINEAR(LDO_VLDO, SC2731_LDO_VLDO_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			   SC2731_LDO_VLDO_PD_MASK, SC2731_LDO_VLDO_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			   SC2731_LDO_VLDO_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	SC2731_REGU_LINEAR(LDO_EMMCCORE, SC2731_LDO_EMMCCORE_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			   SC2731_LDO_EMMCCORE_PD_MASK, SC2731_LDO_EMMCCORE_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			   SC2731_LDO_EMMCCORE_VOL_MASK, 10000, 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			   3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	SC2731_REGU_LINEAR(LDO_SDCORE, SC2731_LDO_SDCORE_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			   SC2731_LDO_SDCORE_PD_MASK, SC2731_LDO_SDCORE_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			   SC2731_LDO_SDCORE_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	SC2731_REGU_LINEAR(LDO_SDIO, SC2731_LDO_SDIO_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			   SC2731_LDO_SDIO_PD_MASK, SC2731_LDO_SDIO_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 			   SC2731_LDO_SDIO_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	SC2731_REGU_LINEAR(LDO_WIFIPA, SC2731_LDO_WIFIPA_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 			   SC2731_LDO_WIFIPA_PD_MASK, SC2731_LDO_WIFIPA_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 			   SC2731_LDO_WIFIPA_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	SC2731_REGU_LINEAR(LDO_USB33, SC2731_LDO_USB33_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 			   SC2731_LDO_USB33_PD_MASK, SC2731_LDO_USB33_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 			   SC2731_LDO_USB33_VOL_MASK, 10000, 1200000, 3750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	SC2731_REGU_LINEAR(LDO_CAMD0, SC2731_LDO_CAMD0_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			   SC2731_LDO_CAMD0_PD_MASK, SC2731_LDO_CAMD0_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 			   SC2731_LDO_CAMD0_VOL_MASK, 6250, 1000000, 1793750),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	SC2731_REGU_LINEAR(LDO_CAMD1, SC2731_LDO_CAMD1_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			   SC2731_LDO_CAMD1_PD_MASK, SC2731_LDO_CAMD1_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			   SC2731_LDO_CAMD1_VOL_MASK, 6250, 1000000, 1793750),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	SC2731_REGU_LINEAR(LDO_CON, SC2731_LDO_CON_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 			   SC2731_LDO_CON_PD_MASK, SC2731_LDO_CON_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 			   SC2731_LDO_CON_VOL_MASK, 6250, 1000000, 1793750),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	SC2731_REGU_LINEAR(LDO_CAMIO, SC2731_LDO_CAMIO_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			   SC2731_LDO_CAMIO_PD_MASK, SC2731_LDO_CAMIO_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			   SC2731_LDO_CAMIO_VOL_MASK, 6250, 1000000, 1793750),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	SC2731_REGU_LINEAR(LDO_SRAM, SC2731_LDO_SRAM_PD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 			   SC2731_LDO_SRAM_PD_MASK, SC2731_LDO_SRAM_VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 			   SC2731_LDO_SRAM_VOL_MASK, 6250, 1000000, 1793750),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int sc2731_regulator_unlock(struct regmap *regmap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return regmap_write(regmap, SC2731_PWR_WR_PROT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			    SC2731_WR_UNLOCK_VALUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int sc2731_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (!regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		dev_err(&pdev->dev, "failed to get regmap.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = sc2731_regulator_unlock(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(&pdev->dev, "failed to release regulator lock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	config.regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	for (i = 0; i < ARRAY_SIZE(regulators); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		rdev = devm_regulator_register(&pdev->dev, &regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 					       &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			dev_err(&pdev->dev, "failed to register regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 				regulators[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static struct platform_driver sc2731_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.name = "sc27xx-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.probe = sc2731_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) module_platform_driver(sc2731_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MODULE_AUTHOR("Chen Junhui <erick.chen@spreadtrum.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MODULE_DESCRIPTION("Spreadtrum SC2731 regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MODULE_LICENSE("GPL v2");