^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2012-2014 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/samsung/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mfd/samsung/s2mps11.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/mfd/samsung/s2mps13.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/samsung/s2mps14.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/mfd/samsung/s2mps15.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mfd/samsung/s2mpu02.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* The highest number of possible regulators for supported devices. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define S2MPS_REGULATOR_MAX S2MPS13_REGULATOR_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) struct s2mps11_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int ramp_delay2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int ramp_delay34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int ramp_delay5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) int ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int ramp_delay7810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) int ramp_delay9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum sec_device_type dev_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * One bit for each S2MPS11/S2MPS13/S2MPS14/S2MPU02 regulator whether
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * the suspend mode was enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Array (size: number of regulators) with GPIO-s for external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * sleep control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct gpio_desc **ext_control_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static int get_ramp_delay(int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) unsigned char cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ramp_delay /= 6250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) ramp_delay = ramp_delay >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (ramp_delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) if (cnt > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int s2mps11_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) unsigned int old_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) unsigned int new_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int rdev_id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) unsigned int ramp_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int old_volt, new_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) switch (rdev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) case S2MPS11_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ramp_delay = s2mps11->ramp_delay2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) case S2MPS11_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) case S2MPS11_BUCK4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ramp_delay = s2mps11->ramp_delay34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) case S2MPS11_BUCK5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) ramp_delay = s2mps11->ramp_delay5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) case S2MPS11_BUCK6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) case S2MPS11_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) ramp_delay = s2mps11->ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) case S2MPS11_BUCK7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) case S2MPS11_BUCK8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) case S2MPS11_BUCK10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) ramp_delay = s2mps11->ramp_delay7810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) case S2MPS11_BUCK9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ramp_delay = s2mps11->ramp_delay9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (ramp_delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ramp_delay = rdev->desc->ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) old_volt = rdev->desc->min_uV + (rdev->desc->uV_step * old_selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) new_volt = rdev->desc->min_uV + (rdev->desc->uV_step * new_selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return DIV_ROUND_UP(abs(new_volt - old_volt), ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int s2mps11_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int ramp_val, ramp_shift, ramp_reg = S2MPS11_REG_RAMP_BUCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int ramp_enable = 1, enable_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int rdev_id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) switch (rdev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) case S2MPS11_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ramp_delay > s2mps11->ramp_delay16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) s2mps11->ramp_delay16 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) ramp_delay = s2mps11->ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) ramp_shift = S2MPS11_BUCK16_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case S2MPS11_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enable_shift = S2MPS11_BUCK2_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) s2mps11->ramp_delay2 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ramp_shift = S2MPS11_BUCK2_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) ramp_reg = S2MPS11_REG_RAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) case S2MPS11_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enable_shift = S2MPS11_BUCK3_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ramp_delay > s2mps11->ramp_delay34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) s2mps11->ramp_delay34 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) ramp_delay = s2mps11->ramp_delay34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ramp_shift = S2MPS11_BUCK34_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ramp_reg = S2MPS11_REG_RAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) case S2MPS11_BUCK4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) enable_shift = S2MPS11_BUCK4_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ramp_delay > s2mps11->ramp_delay34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) s2mps11->ramp_delay34 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ramp_delay = s2mps11->ramp_delay34;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ramp_shift = S2MPS11_BUCK34_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ramp_reg = S2MPS11_REG_RAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) case S2MPS11_BUCK5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) s2mps11->ramp_delay5 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ramp_shift = S2MPS11_BUCK5_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case S2MPS11_BUCK6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) enable_shift = S2MPS11_BUCK6_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ramp_delay > s2mps11->ramp_delay16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) s2mps11->ramp_delay16 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ramp_delay = s2mps11->ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ramp_shift = S2MPS11_BUCK16_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) case S2MPS11_BUCK7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case S2MPS11_BUCK8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case S2MPS11_BUCK10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (ramp_delay > s2mps11->ramp_delay7810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) s2mps11->ramp_delay7810 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ramp_delay = s2mps11->ramp_delay7810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ramp_shift = S2MPS11_BUCK7810_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) case S2MPS11_BUCK9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) s2mps11->ramp_delay9 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ramp_shift = S2MPS11_BUCK9_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!ramp_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) goto ramp_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Ramp delay can be enabled/disabled only for buck[2346] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if ((rdev_id >= S2MPS11_BUCK2 && rdev_id <= S2MPS11_BUCK4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) rdev_id == S2MPS11_BUCK6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ret = regmap_update_bits(rdev->regmap, S2MPS11_REG_RAMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 1 << enable_shift, 1 << enable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dev_err(&rdev->dev, "failed to enable ramp rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ramp_val = get_ramp_delay(ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) return regmap_update_bits(rdev->regmap, ramp_reg, 0x3 << ramp_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ramp_val << ramp_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ramp_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return regmap_update_bits(rdev->regmap, S2MPS11_REG_RAMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 1 << enable_shift, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static int s2mps11_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int rdev_id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) switch (s2mps11->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) case S2MPS11X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) if (test_bit(rdev_id, s2mps11->suspend_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val = S2MPS14_ENABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) val = rdev->desc->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (test_bit(rdev_id, s2mps11->suspend_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) val = S2MPS14_ENABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) else if (s2mps11->ext_control_gpiod[rdev_id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) val = S2MPS14_ENABLE_EXT_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) val = rdev->desc->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) case S2MPU02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (test_bit(rdev_id, s2mps11->suspend_state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) val = S2MPU02_ENABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) val = rdev->desc->enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) rdev->desc->enable_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int s2mps11_regulator_set_suspend_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int val, state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct s2mps11_info *s2mps11 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int rdev_id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Below LDO should be always on or does not support suspend mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) switch (s2mps11->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) case S2MPS11X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) switch (rdev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) case S2MPS11_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) case S2MPS11_LDO36:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) case S2MPS11_LDO37:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) case S2MPS11_LDO38:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) state = S2MPS14_ENABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) switch (rdev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case S2MPS14_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) state = S2MPS14_ENABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) case S2MPU02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) switch (rdev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) case S2MPU02_LDO13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) case S2MPU02_LDO14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) case S2MPU02_LDO15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case S2MPU02_LDO17:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) case S2MPU02_BUCK7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) state = S2MPU02_DISABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) state = S2MPU02_ENABLE_SUSPEND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = regmap_read(rdev->regmap, rdev->desc->enable_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) set_bit(rdev_id, s2mps11->suspend_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Don't enable suspend mode if regulator is already disabled because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * this would effectively for a short time turn on the regulator after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * resuming.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * However we still want to toggle the suspend_state bit for regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * in case if it got enabled before suspending the system.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!(val & rdev->desc->enable_mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) rdev->desc->enable_mask, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const struct regulator_ops s2mps11_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .enable = s2mps11_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .set_suspend_disable = s2mps11_regulator_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct regulator_ops s2mps11_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .enable = s2mps11_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .set_voltage_time_sel = s2mps11_regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .set_ramp_delay = s2mps11_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .set_suspend_disable = s2mps11_regulator_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define regulator_desc_s2mps11_ldo(num, step) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .id = S2MPS11_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ops = &s2mps11_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .ramp_delay = RAMP_DELAY_12_MVUS, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .min_uV = MIN_800_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .n_voltages = S2MPS11_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .vsel_reg = S2MPS11_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .vsel_mask = S2MPS11_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .enable_reg = S2MPS11_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .enable_mask = S2MPS11_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define regulator_desc_s2mps11_buck1_4(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .id = S2MPS11_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .ops = &s2mps11_buck_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .min_uV = MIN_650_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .uV_step = STEP_6_25_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .linear_min_sel = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .n_voltages = S2MPS11_BUCK12346_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .ramp_delay = S2MPS11_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .vsel_reg = S2MPS11_REG_B1CTRL2 + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .vsel_mask = S2MPS11_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .enable_reg = S2MPS11_REG_B1CTRL1 + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .enable_mask = S2MPS11_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define regulator_desc_s2mps11_buck5 { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .name = "BUCK5", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .id = S2MPS11_BUCK5, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .ops = &s2mps11_buck_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .min_uV = MIN_650_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .uV_step = STEP_6_25_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .linear_min_sel = 8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .n_voltages = S2MPS11_BUCK5_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .ramp_delay = S2MPS11_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .vsel_reg = S2MPS11_REG_B5CTRL2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .vsel_mask = S2MPS11_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .enable_reg = S2MPS11_REG_B5CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .enable_mask = S2MPS11_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define regulator_desc_s2mps11_buck67810(num, min, step, min_sel, voltages) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .id = S2MPS11_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ops = &s2mps11_buck_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .linear_min_sel = min_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .n_voltages = voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .ramp_delay = S2MPS11_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .vsel_reg = S2MPS11_REG_B6CTRL2 + (num - 6) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .vsel_mask = S2MPS11_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .enable_reg = S2MPS11_REG_B6CTRL1 + (num - 6) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .enable_mask = S2MPS11_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define regulator_desc_s2mps11_buck9 { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .name = "BUCK9", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .id = S2MPS11_BUCK9, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .ops = &s2mps11_buck_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .min_uV = MIN_3000_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .uV_step = STEP_25_MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .n_voltages = S2MPS11_BUCK9_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .ramp_delay = S2MPS11_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .vsel_reg = S2MPS11_REG_B9CTRL2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .vsel_mask = S2MPS11_BUCK9_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .enable_reg = S2MPS11_REG_B9CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .enable_mask = S2MPS11_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static const struct regulator_desc s2mps11_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) regulator_desc_s2mps11_ldo(1, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) regulator_desc_s2mps11_ldo(2, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) regulator_desc_s2mps11_ldo(3, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) regulator_desc_s2mps11_ldo(4, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) regulator_desc_s2mps11_ldo(5, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) regulator_desc_s2mps11_ldo(6, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regulator_desc_s2mps11_ldo(7, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) regulator_desc_s2mps11_ldo(8, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) regulator_desc_s2mps11_ldo(9, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) regulator_desc_s2mps11_ldo(10, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) regulator_desc_s2mps11_ldo(11, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) regulator_desc_s2mps11_ldo(12, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) regulator_desc_s2mps11_ldo(13, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) regulator_desc_s2mps11_ldo(14, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) regulator_desc_s2mps11_ldo(15, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) regulator_desc_s2mps11_ldo(16, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) regulator_desc_s2mps11_ldo(17, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) regulator_desc_s2mps11_ldo(18, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) regulator_desc_s2mps11_ldo(19, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) regulator_desc_s2mps11_ldo(20, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) regulator_desc_s2mps11_ldo(21, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) regulator_desc_s2mps11_ldo(22, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) regulator_desc_s2mps11_ldo(23, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) regulator_desc_s2mps11_ldo(24, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) regulator_desc_s2mps11_ldo(25, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) regulator_desc_s2mps11_ldo(26, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) regulator_desc_s2mps11_ldo(27, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) regulator_desc_s2mps11_ldo(28, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) regulator_desc_s2mps11_ldo(29, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) regulator_desc_s2mps11_ldo(30, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) regulator_desc_s2mps11_ldo(31, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) regulator_desc_s2mps11_ldo(32, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) regulator_desc_s2mps11_ldo(33, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) regulator_desc_s2mps11_ldo(34, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) regulator_desc_s2mps11_ldo(35, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) regulator_desc_s2mps11_ldo(36, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) regulator_desc_s2mps11_ldo(37, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) regulator_desc_s2mps11_ldo(38, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) regulator_desc_s2mps11_buck1_4(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) regulator_desc_s2mps11_buck1_4(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) regulator_desc_s2mps11_buck1_4(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) regulator_desc_s2mps11_buck1_4(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) regulator_desc_s2mps11_buck5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) regulator_desc_s2mps11_buck67810(6, MIN_650_MV, STEP_6_25_MV, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) S2MPS11_BUCK12346_N_VOLTAGES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) regulator_desc_s2mps11_buck67810(7, MIN_750_MV, STEP_12_5_MV, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) S2MPS11_BUCK7810_N_VOLTAGES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) regulator_desc_s2mps11_buck67810(8, MIN_750_MV, STEP_12_5_MV, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) S2MPS11_BUCK7810_N_VOLTAGES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) regulator_desc_s2mps11_buck9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) regulator_desc_s2mps11_buck67810(10, MIN_750_MV, STEP_12_5_MV, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) S2MPS11_BUCK7810_N_VOLTAGES),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct regulator_ops s2mps14_reg_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define regulator_desc_s2mps13_ldo(num, min, step, min_sel) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .id = S2MPS13_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .ops = &s2mps14_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .linear_min_sel = min_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .n_voltages = S2MPS14_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .vsel_reg = S2MPS13_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .vsel_mask = S2MPS14_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .enable_reg = S2MPS13_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .enable_mask = S2MPS14_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define regulator_desc_s2mps13_buck(num, min, step, min_sel) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .id = S2MPS13_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .ops = &s2mps14_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .linear_min_sel = min_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .n_voltages = S2MPS14_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .ramp_delay = S2MPS13_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .vsel_reg = S2MPS13_REG_B1OUT + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .vsel_mask = S2MPS14_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .enable_reg = S2MPS13_REG_B1CTRL + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .enable_mask = S2MPS14_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define regulator_desc_s2mps13_buck7(num, min, step, min_sel) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .id = S2MPS13_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &s2mps14_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .linear_min_sel = min_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .n_voltages = S2MPS14_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .ramp_delay = S2MPS13_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .vsel_reg = S2MPS13_REG_B1OUT + (num) * 2 - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .vsel_mask = S2MPS14_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .enable_reg = S2MPS13_REG_B1CTRL + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .enable_mask = S2MPS14_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define regulator_desc_s2mps13_buck8_10(num, min, step, min_sel) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .id = S2MPS13_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .ops = &s2mps14_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .linear_min_sel = min_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .n_voltages = S2MPS14_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .ramp_delay = S2MPS13_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .vsel_reg = S2MPS13_REG_B1OUT + (num) * 2 - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .vsel_mask = S2MPS14_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .enable_reg = S2MPS13_REG_B1CTRL + (num) * 2 - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .enable_mask = S2MPS14_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static const struct regulator_desc s2mps13_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) regulator_desc_s2mps13_ldo(1, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) regulator_desc_s2mps13_ldo(2, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) regulator_desc_s2mps13_ldo(3, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regulator_desc_s2mps13_ldo(4, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) regulator_desc_s2mps13_ldo(5, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) regulator_desc_s2mps13_ldo(6, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) regulator_desc_s2mps13_ldo(7, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) regulator_desc_s2mps13_ldo(8, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) regulator_desc_s2mps13_ldo(9, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) regulator_desc_s2mps13_ldo(10, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) regulator_desc_s2mps13_ldo(11, MIN_800_MV, STEP_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) regulator_desc_s2mps13_ldo(12, MIN_800_MV, STEP_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) regulator_desc_s2mps13_ldo(13, MIN_800_MV, STEP_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) regulator_desc_s2mps13_ldo(14, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) regulator_desc_s2mps13_ldo(15, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) regulator_desc_s2mps13_ldo(16, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) regulator_desc_s2mps13_ldo(17, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) regulator_desc_s2mps13_ldo(18, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) regulator_desc_s2mps13_ldo(19, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) regulator_desc_s2mps13_ldo(20, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) regulator_desc_s2mps13_ldo(21, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) regulator_desc_s2mps13_ldo(22, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) regulator_desc_s2mps13_ldo(23, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) regulator_desc_s2mps13_ldo(24, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) regulator_desc_s2mps13_ldo(25, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regulator_desc_s2mps13_ldo(26, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) regulator_desc_s2mps13_ldo(27, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) regulator_desc_s2mps13_ldo(28, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) regulator_desc_s2mps13_ldo(29, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) regulator_desc_s2mps13_ldo(30, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) regulator_desc_s2mps13_ldo(31, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) regulator_desc_s2mps13_ldo(32, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) regulator_desc_s2mps13_ldo(33, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) regulator_desc_s2mps13_ldo(34, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) regulator_desc_s2mps13_ldo(35, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) regulator_desc_s2mps13_ldo(36, MIN_800_MV, STEP_12_5_MV, 0x00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) regulator_desc_s2mps13_ldo(37, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) regulator_desc_s2mps13_ldo(38, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) regulator_desc_s2mps13_ldo(39, MIN_1000_MV, STEP_25_MV, 0x08),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) regulator_desc_s2mps13_ldo(40, MIN_1400_MV, STEP_50_MV, 0x0C),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) regulator_desc_s2mps13_buck(1, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) regulator_desc_s2mps13_buck(2, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) regulator_desc_s2mps13_buck(3, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) regulator_desc_s2mps13_buck(4, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regulator_desc_s2mps13_buck(5, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) regulator_desc_s2mps13_buck(6, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regulator_desc_s2mps13_buck7(7, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) regulator_desc_s2mps13_buck8_10(8, MIN_1000_MV, STEP_12_5_MV, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regulator_desc_s2mps13_buck8_10(9, MIN_1000_MV, STEP_12_5_MV, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) regulator_desc_s2mps13_buck8_10(10, MIN_500_MV, STEP_6_25_MV, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static const struct regulator_ops s2mps14_reg_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .enable = s2mps11_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .set_suspend_disable = s2mps11_regulator_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define regulator_desc_s2mps14_ldo(num, min, step) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .id = S2MPS14_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .ops = &s2mps14_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .n_voltages = S2MPS14_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .vsel_reg = S2MPS14_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .vsel_mask = S2MPS14_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .enable_reg = S2MPS14_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .enable_mask = S2MPS14_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define regulator_desc_s2mps14_buck(num, min, step, min_sel) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .id = S2MPS14_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .ops = &s2mps14_reg_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .n_voltages = S2MPS14_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .linear_min_sel = min_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .ramp_delay = S2MPS14_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .vsel_reg = S2MPS14_REG_B1CTRL2 + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .vsel_mask = S2MPS14_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .enable_reg = S2MPS14_REG_B1CTRL1 + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .enable_mask = S2MPS14_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const struct regulator_desc s2mps14_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) regulator_desc_s2mps14_ldo(1, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) regulator_desc_s2mps14_ldo(2, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) regulator_desc_s2mps14_ldo(3, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) regulator_desc_s2mps14_ldo(4, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) regulator_desc_s2mps14_ldo(5, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) regulator_desc_s2mps14_ldo(6, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) regulator_desc_s2mps14_ldo(7, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) regulator_desc_s2mps14_ldo(8, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) regulator_desc_s2mps14_ldo(9, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) regulator_desc_s2mps14_ldo(10, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) regulator_desc_s2mps14_ldo(11, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) regulator_desc_s2mps14_ldo(12, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) regulator_desc_s2mps14_ldo(13, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) regulator_desc_s2mps14_ldo(14, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) regulator_desc_s2mps14_ldo(15, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) regulator_desc_s2mps14_ldo(16, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) regulator_desc_s2mps14_ldo(17, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) regulator_desc_s2mps14_ldo(18, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) regulator_desc_s2mps14_ldo(19, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) regulator_desc_s2mps14_ldo(20, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) regulator_desc_s2mps14_ldo(21, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) regulator_desc_s2mps14_ldo(22, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) regulator_desc_s2mps14_ldo(23, MIN_800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) regulator_desc_s2mps14_ldo(24, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) regulator_desc_s2mps14_ldo(25, MIN_1800_MV, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) regulator_desc_s2mps14_buck(1, MIN_600_MV, STEP_6_25_MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) S2MPS14_BUCK1235_START_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) regulator_desc_s2mps14_buck(2, MIN_600_MV, STEP_6_25_MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) S2MPS14_BUCK1235_START_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) regulator_desc_s2mps14_buck(3, MIN_600_MV, STEP_6_25_MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) S2MPS14_BUCK1235_START_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) regulator_desc_s2mps14_buck(4, MIN_1400_MV, STEP_12_5_MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) S2MPS14_BUCK4_START_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) regulator_desc_s2mps14_buck(5, MIN_600_MV, STEP_6_25_MV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) S2MPS14_BUCK1235_START_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static const struct regulator_ops s2mps15_reg_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) static const struct regulator_ops s2mps15_reg_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define regulator_desc_s2mps15_ldo(num, range) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .id = S2MPS15_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .ops = &s2mps15_reg_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .linear_ranges = range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .n_linear_ranges = ARRAY_SIZE(range), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .n_voltages = S2MPS15_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .vsel_reg = S2MPS15_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .vsel_mask = S2MPS15_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .enable_reg = S2MPS15_REG_L1CTRL + num - 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .enable_mask = S2MPS15_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define regulator_desc_s2mps15_buck(num, range) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .id = S2MPS15_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .ops = &s2mps15_reg_buck_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .linear_ranges = range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .n_linear_ranges = ARRAY_SIZE(range), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .ramp_delay = 12500, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .n_voltages = S2MPS15_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .vsel_reg = S2MPS15_REG_B1CTRL2 + ((num - 1) * 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .vsel_mask = S2MPS15_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .enable_reg = S2MPS15_REG_B1CTRL1 + ((num - 1) * 2), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .enable_mask = S2MPS15_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* voltage range for s2mps15 LDO 3, 5, 15, 16, 18, 20, 23 and 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static const struct linear_range s2mps15_ldo_voltage_ranges1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) REGULATOR_LINEAR_RANGE(1000000, 0xc, 0x38, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* voltage range for s2mps15 LDO 2, 6, 14, 17, 19, 21, 24 and 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static const struct linear_range s2mps15_ldo_voltage_ranges2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) REGULATOR_LINEAR_RANGE(1800000, 0x0, 0x3f, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* voltage range for s2mps15 LDO 4, 11, 12, 13, 22 and 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct linear_range s2mps15_ldo_voltage_ranges3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) REGULATOR_LINEAR_RANGE(700000, 0x0, 0x34, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* voltage range for s2mps15 LDO 7, 8, 9 and 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static const struct linear_range s2mps15_ldo_voltage_ranges4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) REGULATOR_LINEAR_RANGE(700000, 0x10, 0x20, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* voltage range for s2mps15 LDO 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static const struct linear_range s2mps15_ldo_voltage_ranges5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) REGULATOR_LINEAR_RANGE(500000, 0x0, 0x20, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* voltage range for s2mps15 BUCK 1, 2, 3, 4, 5, 6 and 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static const struct linear_range s2mps15_buck_voltage_ranges1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) REGULATOR_LINEAR_RANGE(500000, 0x20, 0xc0, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* voltage range for s2mps15 BUCK 8, 9 and 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static const struct linear_range s2mps15_buck_voltage_ranges2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) REGULATOR_LINEAR_RANGE(1000000, 0x20, 0x78, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static const struct regulator_desc s2mps15_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) regulator_desc_s2mps15_ldo(1, s2mps15_ldo_voltage_ranges5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) regulator_desc_s2mps15_ldo(2, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) regulator_desc_s2mps15_ldo(3, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) regulator_desc_s2mps15_ldo(4, s2mps15_ldo_voltage_ranges3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) regulator_desc_s2mps15_ldo(5, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) regulator_desc_s2mps15_ldo(6, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) regulator_desc_s2mps15_ldo(7, s2mps15_ldo_voltage_ranges4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) regulator_desc_s2mps15_ldo(8, s2mps15_ldo_voltage_ranges4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) regulator_desc_s2mps15_ldo(9, s2mps15_ldo_voltage_ranges4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) regulator_desc_s2mps15_ldo(10, s2mps15_ldo_voltage_ranges4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) regulator_desc_s2mps15_ldo(11, s2mps15_ldo_voltage_ranges3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) regulator_desc_s2mps15_ldo(12, s2mps15_ldo_voltage_ranges3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) regulator_desc_s2mps15_ldo(13, s2mps15_ldo_voltage_ranges3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) regulator_desc_s2mps15_ldo(14, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) regulator_desc_s2mps15_ldo(15, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) regulator_desc_s2mps15_ldo(16, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) regulator_desc_s2mps15_ldo(17, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) regulator_desc_s2mps15_ldo(18, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) regulator_desc_s2mps15_ldo(19, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) regulator_desc_s2mps15_ldo(20, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) regulator_desc_s2mps15_ldo(21, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) regulator_desc_s2mps15_ldo(22, s2mps15_ldo_voltage_ranges3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) regulator_desc_s2mps15_ldo(23, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) regulator_desc_s2mps15_ldo(24, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) regulator_desc_s2mps15_ldo(25, s2mps15_ldo_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) regulator_desc_s2mps15_ldo(26, s2mps15_ldo_voltage_ranges3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) regulator_desc_s2mps15_ldo(27, s2mps15_ldo_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) regulator_desc_s2mps15_buck(1, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) regulator_desc_s2mps15_buck(2, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) regulator_desc_s2mps15_buck(3, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) regulator_desc_s2mps15_buck(4, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) regulator_desc_s2mps15_buck(5, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) regulator_desc_s2mps15_buck(6, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) regulator_desc_s2mps15_buck(7, s2mps15_buck_voltage_ranges1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) regulator_desc_s2mps15_buck(8, s2mps15_buck_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) regulator_desc_s2mps15_buck(9, s2mps15_buck_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) regulator_desc_s2mps15_buck(10, s2mps15_buck_voltage_ranges2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int s2mps14_pmic_enable_ext_control(struct s2mps11_info *s2mps11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct of_regulator_match *rdata, struct s2mps11_info *s2mps11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct gpio_desc **gpio = s2mps11->ext_control_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) unsigned int valid_regulators[3] = { S2MPS14_LDO10, S2MPS14_LDO11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) S2MPS14_LDO12 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) for (i = 0; i < ARRAY_SIZE(valid_regulators); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) unsigned int reg = valid_regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!rdata[reg].init_data || !rdata[reg].of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) gpio[reg] = devm_fwnode_gpiod_get(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) of_fwnode_handle(rdata[reg].of_node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "samsung,ext-control",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "s2mps11-regulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (PTR_ERR(gpio[reg]) == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) gpio[reg] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) else if (IS_ERR(gpio[reg])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) reg, rdata[reg].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) gpio[reg] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (gpio[reg])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) dev_dbg(&pdev->dev, "Using GPIO for ext-control over %d/%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) reg, rdata[reg].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) static int s2mps11_pmic_dt_parse(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct of_regulator_match *rdata, struct s2mps11_info *s2mps11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) unsigned int rdev_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct device_node *reg_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) reg_np = of_get_child_by_name(pdev->dev.parent->of_node, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (!reg_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) dev_err(&pdev->dev, "could not find regulators sub-node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) of_regulator_match(&pdev->dev, reg_np, rdata, rdev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (s2mps11->dev_type == S2MPS14X)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) s2mps14_pmic_dt_parse_ext_control_gpio(pdev, rdata, s2mps11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) of_node_put(reg_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int s2mpu02_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned int ramp_val, ramp_shift, ramp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int rdev_id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) switch (rdev_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) case S2MPU02_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ramp_shift = S2MPU02_BUCK1_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case S2MPU02_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ramp_shift = S2MPU02_BUCK2_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case S2MPU02_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) ramp_shift = S2MPU02_BUCK3_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case S2MPU02_BUCK4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ramp_shift = S2MPU02_BUCK4_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ramp_reg = S2MPU02_REG_RAMP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ramp_val = get_ramp_delay(ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return regmap_update_bits(rdev->regmap, ramp_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) S2MPU02_BUCK1234_RAMP_MASK << ramp_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ramp_val << ramp_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static const struct regulator_ops s2mpu02_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .enable = s2mps11_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .set_suspend_disable = s2mps11_regulator_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static const struct regulator_ops s2mpu02_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .enable = s2mps11_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .set_suspend_disable = s2mps11_regulator_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) .set_ramp_delay = s2mpu02_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define regulator_desc_s2mpu02_ldo1(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) .id = S2MPU02_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .min_uV = S2MPU02_LDO_MIN_900MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .uV_step = S2MPU02_LDO_STEP_12_5MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .linear_min_sel = S2MPU02_LDO_GROUP1_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .n_voltages = S2MPU02_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .vsel_reg = S2MPU02_REG_L1CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .vsel_mask = S2MPU02_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .enable_reg = S2MPU02_REG_L1CTRL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define regulator_desc_s2mpu02_ldo2(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .id = S2MPU02_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .min_uV = S2MPU02_LDO_MIN_1050MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .uV_step = S2MPU02_LDO_STEP_25MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .linear_min_sel = S2MPU02_LDO_GROUP2_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .n_voltages = S2MPU02_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .vsel_reg = S2MPU02_REG_L2CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) .vsel_mask = S2MPU02_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .enable_reg = S2MPU02_REG_L2CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define regulator_desc_s2mpu02_ldo3(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .id = S2MPU02_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .min_uV = S2MPU02_LDO_MIN_900MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .uV_step = S2MPU02_LDO_STEP_12_5MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .linear_min_sel = S2MPU02_LDO_GROUP1_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .n_voltages = S2MPU02_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .vsel_reg = S2MPU02_REG_L3CTRL + num - 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .vsel_mask = S2MPU02_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .enable_reg = S2MPU02_REG_L3CTRL + num - 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define regulator_desc_s2mpu02_ldo4(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .id = S2MPU02_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .min_uV = S2MPU02_LDO_MIN_1050MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .uV_step = S2MPU02_LDO_STEP_25MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .linear_min_sel = S2MPU02_LDO_GROUP2_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .n_voltages = S2MPU02_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .vsel_reg = S2MPU02_REG_L3CTRL + num - 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .vsel_mask = S2MPU02_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .enable_reg = S2MPU02_REG_L3CTRL + num - 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define regulator_desc_s2mpu02_ldo5(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .name = "LDO"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) .id = S2MPU02_LDO##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .min_uV = S2MPU02_LDO_MIN_1600MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) .uV_step = S2MPU02_LDO_STEP_50MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) .linear_min_sel = S2MPU02_LDO_GROUP3_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .n_voltages = S2MPU02_LDO_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .vsel_reg = S2MPU02_REG_L3CTRL + num - 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) .vsel_mask = S2MPU02_LDO_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) .enable_reg = S2MPU02_REG_L3CTRL + num - 3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define regulator_desc_s2mpu02_buck1234(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .id = S2MPU02_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .ops = &s2mpu02_buck_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) .min_uV = S2MPU02_BUCK1234_MIN_600MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) .uV_step = S2MPU02_BUCK1234_STEP_6_25MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) .n_voltages = S2MPU02_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .linear_min_sel = S2MPU02_BUCK1234_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .ramp_delay = S2MPU02_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .vsel_reg = S2MPU02_REG_B1CTRL2 + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .vsel_mask = S2MPU02_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .enable_reg = S2MPU02_REG_B1CTRL1 + (num - 1) * 2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define regulator_desc_s2mpu02_buck5(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .id = S2MPU02_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .min_uV = S2MPU02_BUCK5_MIN_1081_25MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .uV_step = S2MPU02_BUCK5_STEP_6_25MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .n_voltages = S2MPU02_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .linear_min_sel = S2MPU02_BUCK5_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .ramp_delay = S2MPU02_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .vsel_reg = S2MPU02_REG_B5CTRL2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .vsel_mask = S2MPU02_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .enable_reg = S2MPU02_REG_B5CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define regulator_desc_s2mpu02_buck6(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .id = S2MPU02_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .min_uV = S2MPU02_BUCK6_MIN_1700MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .uV_step = S2MPU02_BUCK6_STEP_2_50MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .n_voltages = S2MPU02_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .linear_min_sel = S2MPU02_BUCK6_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .ramp_delay = S2MPU02_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) .vsel_reg = S2MPU02_REG_B6CTRL2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .vsel_mask = S2MPU02_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .enable_reg = S2MPU02_REG_B6CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define regulator_desc_s2mpu02_buck7(num) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .name = "BUCK"#num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .id = S2MPU02_BUCK##num, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .ops = &s2mpu02_ldo_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .min_uV = S2MPU02_BUCK7_MIN_900MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .uV_step = S2MPU02_BUCK7_STEP_6_25MV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .n_voltages = S2MPU02_BUCK_N_VOLTAGES, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .linear_min_sel = S2MPU02_BUCK7_START_SEL, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .ramp_delay = S2MPU02_BUCK_RAMP_DELAY, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .vsel_reg = S2MPU02_REG_B7CTRL2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .vsel_mask = S2MPU02_BUCK_VSEL_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .enable_reg = S2MPU02_REG_B7CTRL1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .enable_mask = S2MPU02_ENABLE_MASK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const struct regulator_desc s2mpu02_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) regulator_desc_s2mpu02_ldo1(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) regulator_desc_s2mpu02_ldo2(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) regulator_desc_s2mpu02_ldo4(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) regulator_desc_s2mpu02_ldo5(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) regulator_desc_s2mpu02_ldo4(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) regulator_desc_s2mpu02_ldo3(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) regulator_desc_s2mpu02_ldo3(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) regulator_desc_s2mpu02_ldo4(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) regulator_desc_s2mpu02_ldo5(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) regulator_desc_s2mpu02_ldo3(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) regulator_desc_s2mpu02_ldo4(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) regulator_desc_s2mpu02_ldo5(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) regulator_desc_s2mpu02_ldo5(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) regulator_desc_s2mpu02_ldo5(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) regulator_desc_s2mpu02_ldo5(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) regulator_desc_s2mpu02_ldo5(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) regulator_desc_s2mpu02_ldo4(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) regulator_desc_s2mpu02_ldo5(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) regulator_desc_s2mpu02_ldo3(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) regulator_desc_s2mpu02_ldo4(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) regulator_desc_s2mpu02_ldo5(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) regulator_desc_s2mpu02_ldo5(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) regulator_desc_s2mpu02_ldo5(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) regulator_desc_s2mpu02_ldo4(24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) regulator_desc_s2mpu02_ldo5(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) regulator_desc_s2mpu02_ldo4(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) regulator_desc_s2mpu02_ldo5(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) regulator_desc_s2mpu02_ldo5(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) regulator_desc_s2mpu02_buck1234(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) regulator_desc_s2mpu02_buck1234(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) regulator_desc_s2mpu02_buck1234(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) regulator_desc_s2mpu02_buck1234(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) regulator_desc_s2mpu02_buck5(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) regulator_desc_s2mpu02_buck6(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) regulator_desc_s2mpu02_buck7(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int s2mps11_pmic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct sec_platform_data *pdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct of_regulator_match *rdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct s2mps11_info *s2mps11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unsigned int rdev_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) const struct regulator_desc *regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) s2mps11 = devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (!s2mps11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) s2mps11->dev_type = platform_get_device_id(pdev)->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) switch (s2mps11->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) case S2MPS11X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) rdev_num = ARRAY_SIZE(s2mps11_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) regulators = s2mps11_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps11_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case S2MPS13X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) rdev_num = ARRAY_SIZE(s2mps13_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) regulators = s2mps13_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps13_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case S2MPS14X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) rdev_num = ARRAY_SIZE(s2mps14_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) regulators = s2mps14_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps14_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) case S2MPS15X:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) rdev_num = ARRAY_SIZE(s2mps15_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) regulators = s2mps15_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mps15_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) case S2MPU02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) rdev_num = ARRAY_SIZE(s2mpu02_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) regulators = s2mpu02_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu02_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) dev_err(&pdev->dev, "Invalid device type: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) s2mps11->dev_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) s2mps11->ext_control_gpiod = devm_kcalloc(&pdev->dev, rdev_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) sizeof(*s2mps11->ext_control_gpiod), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (!s2mps11->ext_control_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!iodev->dev->of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (iodev->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) pdata = iodev->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) goto common_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dev_err(pdev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "Platform data or DT node not supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) rdata = kcalloc(rdev_num, sizeof(*rdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (!rdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) for (i = 0; i < rdev_num; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) rdata[i].name = regulators[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret = s2mps11_pmic_dt_parse(pdev, rdata, s2mps11, rdev_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) common_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) platform_set_drvdata(pdev, s2mps11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) config.regmap = iodev->regmap_pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) config.driver_data = s2mps11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) for (i = 0; i < rdev_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct regulator_dev *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) config.init_data = pdata->regulators[i].initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) config.of_node = pdata->regulators[i].reg_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) config.init_data = rdata[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) config.of_node = rdata[i].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) config.ena_gpiod = s2mps11->ext_control_gpiod[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) * Hand the GPIO descriptor management over to the regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) * core, remove it from devres management.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (config.ena_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) regulator = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ®ulators[i], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (IS_ERR(regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = PTR_ERR(regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_err(&pdev->dev, "regulator init failed for %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (config.ena_gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = s2mps14_pmic_enable_ext_control(s2mps11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "failed to enable GPIO control over %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) regulator->desc->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) kfree(rdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static const struct platform_device_id s2mps11_pmic_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) { "s2mps11-regulator", S2MPS11X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) { "s2mps13-regulator", S2MPS13X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) { "s2mps14-regulator", S2MPS14X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) { "s2mps15-regulator", S2MPS15X},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) { "s2mpu02-regulator", S2MPU02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) MODULE_DEVICE_TABLE(platform, s2mps11_pmic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static struct platform_driver s2mps11_pmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .name = "s2mps11-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .probe = s2mps11_pmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .id_table = s2mps11_pmic_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) module_platform_driver(s2mps11_pmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) MODULE_DESCRIPTION("Samsung S2MPS11/S2MPS14/S2MPS15/S2MPU02 Regulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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