Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2013 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //		http://www.samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/mfd/samsung/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/mfd/samsung/s2mpa01.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct s2mpa01_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	int ramp_delay24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	int ramp_delay3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	int ramp_delay5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	int ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	int ramp_delay7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	int ramp_delay8910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) static int get_ramp_delay(int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	unsigned char cnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	ramp_delay /= 6250;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	while (true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 		ramp_delay = ramp_delay >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 		if (ramp_delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	if (cnt > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		cnt = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	return cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static int s2mpa01_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				   unsigned int old_selector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				   unsigned int new_selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct s2mpa01_info *s2mpa01 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	unsigned int ramp_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int old_volt, new_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	switch (rdev_get_id(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	case S2MPA01_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	case S2MPA01_BUCK4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 		ramp_delay = s2mpa01->ramp_delay24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	case S2MPA01_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 		ramp_delay = s2mpa01->ramp_delay3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	case S2MPA01_BUCK5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 		ramp_delay = s2mpa01->ramp_delay5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	case S2MPA01_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	case S2MPA01_BUCK6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		ramp_delay = s2mpa01->ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	case S2MPA01_BUCK7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		ramp_delay = s2mpa01->ramp_delay7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	case S2MPA01_BUCK8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	case S2MPA01_BUCK9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	case S2MPA01_BUCK10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		ramp_delay = s2mpa01->ramp_delay8910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	if (ramp_delay == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		ramp_delay = rdev->desc->ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	old_volt = rdev->desc->min_uV + (rdev->desc->uV_step * old_selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	new_volt = rdev->desc->min_uV + (rdev->desc->uV_step * new_selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	return DIV_ROUND_UP(abs(new_volt - old_volt), ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int s2mpa01_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct s2mpa01_info *s2mpa01 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned int ramp_val, ramp_shift, ramp_reg = S2MPA01_REG_RAMP2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	unsigned int ramp_enable = 1, enable_shift = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	switch (rdev_get_id(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	case S2MPA01_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		enable_shift = S2MPA01_BUCK1_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		if (ramp_delay > s2mpa01->ramp_delay16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 			s2mpa01->ramp_delay16 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 			ramp_delay = s2mpa01->ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		ramp_shift = S2MPA01_BUCK16_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	case S2MPA01_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 		enable_shift = S2MPA01_BUCK2_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		if (ramp_delay > s2mpa01->ramp_delay24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			s2mpa01->ramp_delay24 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			ramp_delay = s2mpa01->ramp_delay24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		ramp_shift = S2MPA01_BUCK24_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		ramp_reg = S2MPA01_REG_RAMP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	case S2MPA01_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		enable_shift = S2MPA01_BUCK3_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		s2mpa01->ramp_delay3 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		ramp_shift = S2MPA01_BUCK3_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		ramp_reg = S2MPA01_REG_RAMP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	case S2MPA01_BUCK4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		enable_shift = S2MPA01_BUCK4_RAMP_EN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		if (!ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			ramp_enable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		if (ramp_delay > s2mpa01->ramp_delay24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			s2mpa01->ramp_delay24 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			ramp_delay = s2mpa01->ramp_delay24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		ramp_shift = S2MPA01_BUCK24_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		ramp_reg = S2MPA01_REG_RAMP1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case S2MPA01_BUCK5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		s2mpa01->ramp_delay5 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		ramp_shift = S2MPA01_BUCK5_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	case S2MPA01_BUCK6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		if (ramp_delay > s2mpa01->ramp_delay16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			s2mpa01->ramp_delay16 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			ramp_delay = s2mpa01->ramp_delay16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		ramp_shift = S2MPA01_BUCK16_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case S2MPA01_BUCK7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		s2mpa01->ramp_delay7 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		ramp_shift = S2MPA01_BUCK7_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	case S2MPA01_BUCK8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case S2MPA01_BUCK9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	case S2MPA01_BUCK10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		if (ramp_delay > s2mpa01->ramp_delay8910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			s2mpa01->ramp_delay8910 = ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			ramp_delay = s2mpa01->ramp_delay8910;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		ramp_shift = S2MPA01_BUCK8910_RAMP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (!ramp_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		goto ramp_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	/* Ramp delay can be enabled/disabled only for buck[1234] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (rdev_get_id(rdev) >= S2MPA01_BUCK1 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			rdev_get_id(rdev) <= S2MPA01_BUCK4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		ret = regmap_update_bits(rdev->regmap, S2MPA01_REG_RAMP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 					 1 << enable_shift, 1 << enable_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			dev_err(&rdev->dev, "failed to enable ramp rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	ramp_val = get_ramp_delay(ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return regmap_update_bits(rdev->regmap, ramp_reg, 0x3 << ramp_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 				  ramp_val << ramp_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ramp_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	return regmap_update_bits(rdev->regmap, S2MPA01_REG_RAMP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 				  1 << enable_shift, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const struct regulator_ops s2mpa01_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	.list_voltage		= regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	.map_voltage		= regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	.is_enabled		= regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	.enable			= regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	.disable		= regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static const struct regulator_ops s2mpa01_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	.list_voltage		= regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	.map_voltage		= regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	.is_enabled		= regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	.enable			= regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	.disable		= regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	.set_voltage_time_sel	= s2mpa01_regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.set_ramp_delay		= s2mpa01_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define regulator_desc_ldo(num, step) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.name		= "LDO"#num,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.of_match	= of_match_ptr("LDO"#num),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.regulators_node = of_match_ptr("regulators"),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.id		= S2MPA01_LDO##num,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.ops		= &s2mpa01_ldo_ops,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.type		= REGULATOR_VOLTAGE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.owner		= THIS_MODULE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.min_uV		= MIN_800_MV,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.uV_step	= step,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.n_voltages	= S2MPA01_LDO_N_VOLTAGES,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.vsel_reg	= S2MPA01_REG_L1CTRL + num - 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.vsel_mask	= S2MPA01_LDO_VSEL_MASK,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.enable_reg	= S2MPA01_REG_L1CTRL + num - 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.enable_mask	= S2MPA01_ENABLE_MASK		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define regulator_desc_buck1_4(num)	{			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.name		= "BUCK"#num,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.of_match	= of_match_ptr("BUCK"#num),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.regulators_node = of_match_ptr("regulators"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.id		= S2MPA01_BUCK##num,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.ops		= &s2mpa01_buck_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.type		= REGULATOR_VOLTAGE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.owner		= THIS_MODULE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.min_uV		= MIN_600_MV,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.uV_step	= STEP_6_25_MV,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.n_voltages	= S2MPA01_BUCK_N_VOLTAGES,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.ramp_delay	= S2MPA01_RAMP_DELAY,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.vsel_reg	= S2MPA01_REG_B1CTRL2 + (num - 1) * 2,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.vsel_mask	= S2MPA01_BUCK_VSEL_MASK,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.enable_reg	= S2MPA01_REG_B1CTRL1 + (num - 1) * 2,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.enable_mask	= S2MPA01_ENABLE_MASK			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define regulator_desc_buck5	{				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.name		= "BUCK5",				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.of_match	= of_match_ptr("BUCK5"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.regulators_node = of_match_ptr("regulators"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.id		= S2MPA01_BUCK5,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.ops		= &s2mpa01_buck_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.type		= REGULATOR_VOLTAGE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.owner		= THIS_MODULE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	.min_uV		= MIN_800_MV,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.uV_step	= STEP_6_25_MV,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.n_voltages	= S2MPA01_BUCK_N_VOLTAGES,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.ramp_delay	= S2MPA01_RAMP_DELAY,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.vsel_reg	= S2MPA01_REG_B5CTRL2,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.vsel_mask	= S2MPA01_BUCK_VSEL_MASK,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.enable_reg	= S2MPA01_REG_B5CTRL1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.enable_mask	= S2MPA01_ENABLE_MASK			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define regulator_desc_buck6_10(num, min, step) {			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.name		= "BUCK"#num,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	.of_match	= of_match_ptr("BUCK"#num),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	.regulators_node = of_match_ptr("regulators"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	.id		= S2MPA01_BUCK##num,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.ops		= &s2mpa01_buck_ops,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	.type		= REGULATOR_VOLTAGE,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	.owner		= THIS_MODULE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	.min_uV		= min,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	.uV_step	= step,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	.n_voltages	= S2MPA01_BUCK_N_VOLTAGES,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	.ramp_delay	= S2MPA01_RAMP_DELAY,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	.vsel_reg	= S2MPA01_REG_B6CTRL2 + (num - 6) * 2,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	.vsel_mask	= S2MPA01_BUCK_VSEL_MASK,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	.enable_reg	= S2MPA01_REG_B6CTRL1 + (num - 6) * 2,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	.enable_mask	= S2MPA01_ENABLE_MASK			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct regulator_desc regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	regulator_desc_ldo(1, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	regulator_desc_ldo(2, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	regulator_desc_ldo(3, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	regulator_desc_ldo(4, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	regulator_desc_ldo(5, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	regulator_desc_ldo(6, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	regulator_desc_ldo(7, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	regulator_desc_ldo(8, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	regulator_desc_ldo(9, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	regulator_desc_ldo(10, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	regulator_desc_ldo(11, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	regulator_desc_ldo(12, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	regulator_desc_ldo(13, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	regulator_desc_ldo(14, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	regulator_desc_ldo(15, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	regulator_desc_ldo(16, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	regulator_desc_ldo(17, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	regulator_desc_ldo(18, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	regulator_desc_ldo(19, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	regulator_desc_ldo(20, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	regulator_desc_ldo(21, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	regulator_desc_ldo(22, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	regulator_desc_ldo(23, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	regulator_desc_ldo(24, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	regulator_desc_ldo(25, STEP_50_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	regulator_desc_ldo(26, STEP_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	regulator_desc_buck1_4(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	regulator_desc_buck1_4(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	regulator_desc_buck1_4(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	regulator_desc_buck1_4(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	regulator_desc_buck5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	regulator_desc_buck6_10(6, MIN_600_MV, STEP_6_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	regulator_desc_buck6_10(7, MIN_600_MV, STEP_6_25_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	regulator_desc_buck6_10(8, MIN_800_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	regulator_desc_buck6_10(9, MIN_1500_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	regulator_desc_buck6_10(10, MIN_1000_MV, STEP_12_5_MV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int s2mpa01_pmic_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	struct sec_pmic_dev *iodev = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	struct sec_platform_data *pdata = dev_get_platdata(iodev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	struct s2mpa01_info *s2mpa01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	s2mpa01 = devm_kzalloc(&pdev->dev, sizeof(*s2mpa01), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	if (!s2mpa01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	config.dev = iodev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	config.regmap = iodev->regmap_pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	config.driver_data = s2mpa01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	for (i = 0; i < S2MPA01_REGULATOR_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			config.init_data = pdata->regulators[i].initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 						&regulators[i], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			dev_err(&pdev->dev, "regulator init failed for %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const struct platform_device_id s2mpa01_pmic_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	{ "s2mpa01-pmic", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) MODULE_DEVICE_TABLE(platform, s2mpa01_pmic_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static struct platform_driver s2mpa01_pmic_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		.name = "s2mpa01-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.probe = s2mpa01_pmic_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.id_table = s2mpa01_pmic_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) module_platform_driver(s2mpa01_pmic_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) MODULE_AUTHOR("Sangbeom Kim <sbkim73@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MODULE_AUTHOR("Sachin Kamat <sachin.kamat@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) MODULE_DESCRIPTION("Samsung S2MPA01 Regulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_LICENSE("GPL");