^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Regulator driver for Rockchip RK806
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Xu Shengfei <xsf@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/mfd/rk806.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static int dbg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) module_param_named(dbg_level, dbg_enable, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define REG_DBG(args...) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (dbg_enable) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) pr_info(args); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RK806_BUCK_MIN0 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define RK806_BUCK_MAX0 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define RK806_BUCK_MIN1 1500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define RK806_BUCK_MAX1 3400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define RK806_BUCK_STP0 6250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define RK806_BUCK_STP1 25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RK806_NLDO_MIN 500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define RK806_NLDO_MAX 3400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define RK806_NLDO_STP0 1250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RK806_NLDO_SEL ((RK806_NLDO_MAX - RK806_NLDO_MIN) / RK806_NLDO_STP0 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ENABLE_MASK(id) (BIT(id) | BIT(4 + (id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DISABLE_VAL(id) (BIT(4 + (id)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PWM_MODE_MSK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define FPWM_MODE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AUTO_PWM_MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define RK806_DCDC_SLP_REG_OFFSET 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define RK806_NLDO_SLP_REG_OFFSET 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RK806_PLDO_SLP_REG_OFFSET 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define RK806_BUCK_SEL_CNT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RK806_LDO_SEL_CNT 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RK806_RAMP_RATE_4LSB_PER_1CLK 0x00/* LDO 100mV/uS buck 50mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RK806_RAMP_RATE_2LSB_PER_1CLK 0x01/* LDO 50mV/uS buck 25mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RK806_RAMP_RATE_1LSB_PER_1CLK 0x02/* LDO 25mV/uS buck 12.5mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RK806_RAMP_RATE_1LSB_PER_2CLK 0x03/* LDO 12.5mV/uS buck 6.25mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RK806_RAMP_RATE_1LSB_PER_4CLK 0x04/* LDO 6.28/2mV/uS buck 3.125mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RK806_RAMP_RATE_1LSB_PER_8CLK 0x05/* LDO 3.12mV/uS buck 1.56mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RK806_RAMP_RATE_1LSB_PER_13CLK 0x06/* LDO 1.9mV/uS buck 961mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define RK806_RAMP_RATE_1LSB_PER_32CLK 0x07/* LDO 0.78mV/uS buck 0.39mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int vsel_ctr_sel_id[RK806_ID_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) BUCK1_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) BUCK2_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) BUCK3_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) BUCK4_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) BUCK5_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) BUCK6_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BUCK7_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) BUCK8_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) BUCK9_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) BUCK10_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) NLDO1_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) NLDO2_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) NLDO3_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) NLDO4_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) NLDO5_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) PLDO1_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) PLDO2_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) PLDO3_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) PLDO4_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) PLDO5_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) PLDO6_VSEL_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static int start_dvs_id[RK806_ID_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) BUCK1_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) BUCK2_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) BUCK3_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) BUCK4_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) BUCK5_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) BUCK6_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) BUCK7_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) BUCK8_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) BUCK9_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) BUCK10_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) NLDO1_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) NLDO2_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) NLDO3_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) NLDO4_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) NLDO5_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) PLDO1_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) PLDO2_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) PLDO3_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) PLDO4_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PLDO5_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PLDO6_DVS_CTR_SEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const int rk806_buck_rate_config_field[10][2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { BUCK1_RATE, BUCK1_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { BUCK2_RATE, BUCK2_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { BUCK3_RATE, BUCK3_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { BUCK4_RATE, BUCK4_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { BUCK5_RATE, BUCK5_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { BUCK6_RATE, BUCK6_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { BUCK7_RATE, BUCK7_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { BUCK8_RATE, BUCK8_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { BUCK9_RATE, BUCK9_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { BUCK10_RATE, BUCK10_RATE2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct rk806_dvs_field {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int en_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int en_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int sleep_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int on_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int sleep_vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) int vsel_ctrl_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct rk806_dvs_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int en_reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int en_bit_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) int sleep_en_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int on_vsel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int sleep_vsel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int vsel_ctrl_sel_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) int dvs_gpio_level[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct rk806_regulator_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct device_node *dvs_dn[RK806_DVS_END][RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct rk806_dvs_field dvs_field[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct rk806_dvs_status dvs_mode[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct rk806_dvs_status sleep_mode[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int dvs_ctrl_mode_init[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) int dvs_ctrl_mode[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int dvs_ctrl_id[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) int vsel_ctrl_id[RK806_ID_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int dvs_flag[RK806_DVS_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int dvs_used[RK806_DVS_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) int dvs_count[RK806_DVS_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) int regulator_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int support_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct gpio_desc *dvs_gpios[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct rk806 *rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define INIT_DVS_FIELD(_en_reg, _en_bit, _sleep_en, _on_vsel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) _sleep_vsel, _vsel_ctrl_sel) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .en_reg = _en_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .en_bit = _en_bit, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .sleep_en = _sleep_en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .on_vsel = _on_vsel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .sleep_vsel = _sleep_vsel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .vsel_ctrl_sel = _vsel_ctrl_sel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const struct rk806_dvs_field rk806_dvs_fields[RK806_ID_END] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) INIT_DVS_FIELD(POWER_EN0, BIT(0), BUCK1_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BUCK1_ON_VSEL, BUCK1_SLP_VSEL, BUCK1_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) INIT_DVS_FIELD(POWER_EN0, BIT(1), BUCK2_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) BUCK2_ON_VSEL, BUCK2_SLP_VSEL, BUCK2_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) INIT_DVS_FIELD(POWER_EN0, BIT(2), BUCK3_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) BUCK3_ON_VSEL, BUCK3_SLP_VSEL, BUCK3_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) INIT_DVS_FIELD(POWER_EN0, BIT(3), BUCK4_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) BUCK4_ON_VSEL, BUCK4_SLP_VSEL, BUCK4_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) INIT_DVS_FIELD(POWER_EN1, BIT(0), BUCK5_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) BUCK5_ON_VSEL, BUCK5_SLP_VSEL, BUCK5_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) INIT_DVS_FIELD(POWER_EN1, BIT(1), BUCK6_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) BUCK6_ON_VSEL, BUCK6_SLP_VSEL, BUCK6_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) INIT_DVS_FIELD(POWER_EN1, BIT(2), BUCK7_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) BUCK7_ON_VSEL, BUCK7_SLP_VSEL, BUCK7_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) INIT_DVS_FIELD(POWER_EN1, BIT(3), BUCK8_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) BUCK8_ON_VSEL, BUCK8_SLP_VSEL, BUCK8_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) INIT_DVS_FIELD(POWER_EN2, BIT(0), BUCK9_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) BUCK9_ON_VSEL, BUCK9_SLP_VSEL, BUCK9_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) INIT_DVS_FIELD(POWER_EN2, BIT(1), BUCK10_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) BUCK10_ON_VSEL, BUCK10_SLP_VSEL, BUCK10_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) INIT_DVS_FIELD(POWER_EN3, BIT(0), NLDO1_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) NLDO1_ON_VSEL, NLDO1_SLP_VSEL, NLDO1_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) INIT_DVS_FIELD(POWER_EN3, BIT(1), NLDO2_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) NLDO2_ON_VSEL, NLDO2_SLP_VSEL, NLDO2_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) INIT_DVS_FIELD(POWER_EN3, BIT(2), NLDO3_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) NLDO3_ON_VSEL, NLDO3_SLP_VSEL, NLDO3_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) INIT_DVS_FIELD(POWER_EN3, BIT(3), NLDO4_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) NLDO4_ON_VSEL, NLDO4_SLP_VSEL, NLDO4_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) INIT_DVS_FIELD(POWER_EN5, BIT(2), NLDO5_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) NLDO5_ON_VSEL, NLDO5_SLP_VSEL, NLDO5_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) INIT_DVS_FIELD(POWER_EN4, BIT(1), PLDO1_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) PLDO1_ON_VSEL, PLDO1_SLP_VSEL, PLDO1_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) INIT_DVS_FIELD(POWER_EN4, BIT(2), PLDO2_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) PLDO2_ON_VSEL, PLDO2_SLP_VSEL, PLDO2_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) INIT_DVS_FIELD(POWER_EN4, BIT(3), PLDO3_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) PLDO3_ON_VSEL, PLDO3_SLP_VSEL, PLDO3_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) INIT_DVS_FIELD(POWER_EN5, BIT(0), PLDO4_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) PLDO4_ON_VSEL, PLDO4_SLP_VSEL, PLDO4_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) INIT_DVS_FIELD(POWER_EN5, BIT(1), PLDO5_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PLDO5_ON_VSEL, PLDO5_SLP_VSEL, PLDO5_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) INIT_DVS_FIELD(POWER_EN4, BIT(0), PLDO6_SLP_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PLDO6_ON_VSEL, PLDO6_SLP_VSEL, PLDO6_VSEL_CTR_SEL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct linear_range rk806_buck_voltage_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) REGULATOR_LINEAR_RANGE(500000, 0, 159, 6250), /* 500mV ~ 1500mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) REGULATOR_LINEAR_RANGE(1500000, 160, 236, 25000), /* 1500mV ~ 3400mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) REGULATOR_LINEAR_RANGE(3400000, 237, 255, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct linear_range rk806_ldo_voltage_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) REGULATOR_LINEAR_RANGE(500000, 0, 232, 12500), /* 500mV ~ 3400mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) REGULATOR_LINEAR_RANGE(3400000, 233, 255, 0), /* 500mV ~ 3400mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int get_count(int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) while (value != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (value % 2 == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) value >>= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void rk806_dvs_start_fun_init(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) pdata->dvs_ctrl_id[rid],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) pdata->dvs_ctrl_mode[rid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static void rk806_dvs_pwrctrl_fun_init(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* init dvs pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) offset = pdata->dvs_ctrl_mode[rid] - RK806_DVS_PWRCTRL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rk806_field_write(rk806, PWRCTRL1_FUN + offset, PWRCTRL_DVS_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) pdata->dvs_ctrl_id[rid],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) pdata->dvs_ctrl_mode[rid] - RK806_DVS_START3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static void rk806_dvs_start_pwrctrl_fun_init(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* init dvs pin function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) offset = pdata->dvs_ctrl_mode[rid] - RK806_DVS_START_PWRCTR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /*set pin polarity, active high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) rk806_field_write(rk806, PWRCTRL1_POL + offset, POL_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) rk806_field_write(rk806, PWRCTRL1_FUN + offset, PWRCTRL_DVS_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* enable start bit dvs function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) pdata->dvs_ctrl_id[rid],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) pdata->dvs_ctrl_mode[rid] - RK806_DVS_PWRCTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) pdata->vsel_ctrl_id[rid],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) pdata->dvs_ctrl_mode[rid] - RK806_DVS_PWRCTRL3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int rk806_dvs_mode_init(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int mode, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) for (mode = RK806_DVS_START1; mode < RK806_DVS_END; mode++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) for (j = 0; j < RK806_ID_END; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if ((pdata->dvs_dn[mode][j] == NULL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) (strcmp(pdata->dvs_dn[mode][j]->name, rdev->desc->name)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) pdata->dvs_ctrl_mode[rid] = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) pdata->dvs_ctrl_mode_init[rid] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) pdata->dvs_flag[mode] |= BIT(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* init dvs function, dvs-pin or start bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (mode <= RK806_DVS_START3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) rk806_dvs_start_fun_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) else if (mode <= RK806_DVS_PWRCTRL3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) rk806_dvs_pwrctrl_fun_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else if (mode <= RK806_DVS_START_PWRCTR3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) rk806_dvs_start_pwrctrl_fun_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return pdata->dvs_ctrl_mode[rid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return pdata->dvs_ctrl_mode[rid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int get_dvs_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (!pdata->support_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return RK806_DVS_NOT_SUPPORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (pdata->dvs_ctrl_mode_init[rid] || pdata->regulator_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return pdata->dvs_ctrl_mode[rid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return rk806_dvs_mode_init(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int get_gpio_id(int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int pid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if ((mode >= RK806_DVS_PWRCTRL1) && (mode <= RK806_DVS_PWRCTRL3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) pid = mode - RK806_DVS_PWRCTRL1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static int rk806_get_reg_offset(int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int reg_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (id >= RK806_ID_DCDC1 && id <= RK806_ID_DCDC10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg_offset = RK806_DCDC_SLP_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else if ((id >= RK806_ID_NLDO1 && id <= RK806_ID_NLDO4) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) (id == RK806_ID_NLDO5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) reg_offset = RK806_NLDO_SLP_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) else if (id >= RK806_ID_PLDO1 && id <= RK806_ID_PLDO6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) reg_offset = RK806_PLDO_SLP_REG_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int rk806_get_read_vsel_register(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int level, vsel_reg, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) vsel_reg = rdev->desc->vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!pdata->support_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) level = gpiod_get_value(pdata->dvs_gpios[pid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* level == 0, the Output high level, the SLP_VSEL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (level == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) vsel_reg = rdev->desc->vsel_reg + rk806_get_reg_offset(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int rk806_get_write_vsel_register(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int level, vsel_reg, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) vsel_reg = rdev->desc->vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (!pdata->support_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) level = gpiod_get_value(pdata->dvs_gpios[pid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* level == 1, output low level, the ON_VSEL output, next SLP_VSEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (level == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) vsel_reg = rdev->desc->vsel_reg + rk806_get_reg_offset(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static void rk806_do_gpio_dvs(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) char dvs_ctrl_name[10][32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) "dvs_default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "start_dvs1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) "start_dvs2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "start_dvs3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "dvs_pin1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "dvs_pin2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "dvs_pin3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "start_and_pwrctrl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "start_and_pwrctrl2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) "start_and_pwrctrl3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int gpio_level, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int mode, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) pdata->dvs_used[mode] |= BIT(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) count = get_count(pdata->dvs_used[mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if ((pdata->dvs_used[mode] != pdata->dvs_flag[mode]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) (count != pdata->dvs_count[mode]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) pdata->dvs_used[mode] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) gpio_level = gpiod_get_value(pdata->dvs_gpios[pid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (gpio_level == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) gpiod_set_value(pdata->dvs_gpios[pid], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) gpiod_set_value(pdata->dvs_gpios[pid], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) REG_DBG("pin: name: %s, %s\n", dvs_ctrl_name[mode], rdev->desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void rk806_do_soft_dvs(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) char dvs_ctrl_name[10][32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "dvs_default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "start_dvs1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "start_dvs2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) "start_dvs3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "dvs_pin1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "dvs_pin2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "dvs_pin3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "start_and_pwrctrl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "start_and_pwrctrl2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "start_and_pwrctrl3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int soft_mode, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) soft_mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) pdata->dvs_used[soft_mode] |= BIT(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) count = get_count(pdata->dvs_used[soft_mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if ((pdata->dvs_used[soft_mode] != pdata->dvs_flag[soft_mode]) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) (count != pdata->dvs_count[soft_mode]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) pdata->dvs_used[soft_mode] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (soft_mode < RK806_DVS_START_PWRCTR1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) offset = soft_mode - RK806_DVS_START1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) offset = soft_mode - RK806_DVS_START_PWRCTR1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) rk806_field_write(rk806, DVS_START1 + offset, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) REG_DBG("soft:%s, %s\n", dvs_ctrl_name[soft_mode], rdev->desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static void rk806_regulator_sync_voltage(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (mode == RK806_DVS_NOT_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if ((mode >= RK806_DVS_PWRCTRL1) && (mode <= RK806_DVS_PWRCTRL3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) rk806_do_gpio_dvs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) rk806_do_soft_dvs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static unsigned int rk806_regulator_of_map_mode(unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static int rk806_set_suspend_enable_ctrl(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) unsigned int en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (en)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if ((get_dvs_mode(rdev) < RK806_DVS_PWRCTRL1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) (get_dvs_mode(rdev) > RK806_DVS_PWRCTRL3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return rk806_field_write(rk806, pdata->dvs_field[rid].sleep_en, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pdata->sleep_mode[rid].sleep_en_val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int rk806_set_suspend_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return rk806_set_suspend_enable_ctrl(rdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static int rk806_set_suspend_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return rk806_set_suspend_enable_ctrl(rdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int rk806_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ctr_bit, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (rid > RK806_ID_DCDC10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) reg = RK806_POWER_FPWM_EN0 + rid / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ctr_bit = rid % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return regmap_update_bits(rdev->regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) PWM_MODE_MSK << ctr_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) FPWM_MODE << ctr_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return regmap_update_bits(rdev->regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) PWM_MODE_MSK << ctr_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) AUTO_PWM_MODE << ctr_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dev_err(&rdev->dev, "do not support this mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static unsigned int rk806_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int ctr_bit, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (rid > RK806_ID_DCDC10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) reg = RK806_POWER_FPWM_EN0 + rid / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ctr_bit = rid % 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) err = regmap_read(rdev->regmap, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if ((val >> ctr_bit) & FPWM_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int rk806_regulator_sleep2dvs_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int gpio_level, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* set slp_fun NULL*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (pdata->dvs_ctrl_mode[rid] == RK806_DVS_PWRCTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_DVS_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) else if (pdata->dvs_ctrl_mode[rid] == RK806_DVS_PWRCTRL2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) rk806_field_write(rk806, PWRCTRL2_FUN, PWRCTRL_DVS_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else if (pdata->dvs_ctrl_mode[rid] == RK806_DVS_PWRCTRL3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) rk806_field_write(rk806, PWRCTRL3_FUN, PWRCTRL_DVS_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* 3.check the used count 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) pdata->dvs_used[mode] |= BIT(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (pdata->dvs_used[mode] != pdata->dvs_flag[mode])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) pdata->dvs_used[mode] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /* 5.clear the SLP_CTRL_SEL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (j = 0; j < RK806_ID_END; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (pdata->dvs_ctrl_mode[j] == mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) pdata->dvs_field[j].vsel_ctrl_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pdata->dvs_ctrl_mode[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) gpio_level = pdata->dvs_mode[rid].dvs_gpio_level[pid];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (gpio_level == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) gpiod_set_value(pdata->dvs_gpios[pid], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pdata->dvs_field[rid].on_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pdata->dvs_mode[rid].on_vsel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pdata->dvs_field[rid].en_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) pdata->dvs_mode[rid].en_reg_val | (pdata->dvs_field[rid].en_bit << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int rk806_regulator_resume(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (!pdata->support_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (rid == RK806_ID_DCDC1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) for (j = 0; j < RK806_ID_END; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) pdata->dvs_field[j].vsel_ctrl_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pdata->dvs_field[j].sleep_vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) pdata->dvs_mode[j].sleep_vsel_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) pdata->dvs_field[j].sleep_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) pdata->dvs_mode[j].sleep_en_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if ((get_dvs_mode(rdev) >= RK806_DVS_PWRCTRL1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) (get_dvs_mode(rdev) <= RK806_DVS_PWRCTRL3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) rk806_regulator_sleep2dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int uv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int sel = regulator_map_voltage_linear_range(rdev, uv, uv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) reg_offset = rk806_get_reg_offset(rid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) reg = rdev->desc->vsel_reg + reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return regmap_update_bits(rk806->regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) rdev->desc->vsel_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) static int rk806_get_voltage_sel_regmap(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) int vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) vsel_reg = rk806_get_read_vsel_register(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = regmap_read(rdev->regmap, vsel_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) val &= rdev->desc->vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) val >>= ffs(rdev->desc->vsel_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int rk806_set_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int req_min_uV, int req_max_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) unsigned int *selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = regulator_map_voltage_linear_range(rdev, req_min_uV, req_max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) *selector = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) sel = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) vsel_reg = rk806_get_write_vsel_register(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) sel <<= ffs(rdev->desc->vsel_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = regmap_update_bits(rdev->regmap, vsel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) rdev->desc->vsel_mask, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (mode == RK806_DVS_NOT_SUPPORT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if ((mode >= RK806_DVS_PWRCTRL1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) (mode <= RK806_DVS_PWRCTRL3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) rk806_do_gpio_dvs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) rk806_do_soft_dvs(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int rk806_regulator_is_enabled_regmap(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int gpio_level, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) gpio_level = gpiod_get_value(pdata->dvs_gpios[pid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (gpio_level == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return rk806_field_read(rk806, pdata->dvs_field[rid].sleep_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) val = rk806_field_read(rk806, pdata->dvs_field[rid].en_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return (val & rdev->desc->enable_val) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int rk806_regulator_enable_regmap(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int gpio_level, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) gpio_level = gpiod_get_value(pdata->dvs_gpios[pid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (gpio_level == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) pdata->dvs_field[rid].sleep_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) pdata->dvs_field[rid].en_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) rdev->desc->enable_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int rk806_regulator_disable_regmap(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int gpio_level, pid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) mode = get_dvs_mode(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) pid = get_gpio_id(mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if ((pid >= 0) && (pdata->dvs_gpios[pid] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) gpio_level = gpiod_get_value(pdata->dvs_gpios[pid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (gpio_level == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pdata->dvs_field[rid].sleep_en,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pdata->dvs_field[rid].en_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) rdev->desc->disable_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) static int rk806_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) unsigned int ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct rk806_regulator_data *pdata = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct rk806 *rk806 = pdata->rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (rid <= RK806_ID_DCDC10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) switch (ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case 1 ... 390:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case 391 ... 961:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ramp_value = RK806_RAMP_RATE_1LSB_PER_13CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case 962 ... 1560:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ramp_value = RK806_RAMP_RATE_1LSB_PER_8CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case 1561 ... 3125:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ramp_value = RK806_RAMP_RATE_1LSB_PER_4CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) case 3126 ... 6250:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ramp_value = RK806_RAMP_RATE_1LSB_PER_2CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case 6251 ... 12500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ramp_value = RK806_RAMP_RATE_1LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) case 12501 ... 25000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) case 25001 ... 50000: /* 50mV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ramp_value = RK806_RAMP_RATE_4LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) pr_warn("%s ramp_delay: %d not supported, setting 10000\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) rdev->desc->name, ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) rk806_buck_rate_config_field[rid][0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ramp_value & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return rk806_field_write(rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) rk806_buck_rate_config_field[rid][1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) (ramp_value & 0x4) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) switch (ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) case 1 ... 780:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ramp_value = RK806_RAMP_RATE_1LSB_PER_32CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case 781 ... 1900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ramp_value = RK806_RAMP_RATE_1LSB_PER_13CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) case 1901 ... 3120:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ramp_value = RK806_RAMP_RATE_1LSB_PER_8CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case 3121 ... 6280:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ramp_value = RK806_RAMP_RATE_1LSB_PER_4CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case 6281 ... 12500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ramp_value = RK806_RAMP_RATE_1LSB_PER_2CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case 12501 ... 25000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ramp_value = RK806_RAMP_RATE_1LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case 25001 ... 50000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ramp_value = RK806_RAMP_RATE_2LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) case 50001 ... 100000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ramp_value = RK806_RAMP_RATE_4LSB_PER_1CLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) pr_warn("%s ramp_delay: %d not supported, setting 10000\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) rdev->desc->name, ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) return rk806_field_write(rk806, LDO_RATE, ramp_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static const struct regulator_ops rk806_ops_dcdc = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) .get_voltage_sel = rk806_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) .set_voltage = rk806_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .set_mode = rk806_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) .get_mode = rk806_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .enable = rk806_regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .disable = rk806_regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .is_enabled = rk806_regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .set_suspend_mode = rk806_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .set_ramp_delay = rk806_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .set_suspend_voltage = rk806_set_suspend_voltage_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .resume = rk806_regulator_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .set_suspend_enable = rk806_set_suspend_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .set_suspend_disable = rk806_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct regulator_ops rk806_ops_ldo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) .get_voltage_sel = rk806_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) .set_voltage = rk806_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) .enable = rk806_regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .disable = rk806_regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .is_enabled = rk806_regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .set_suspend_mode = rk806_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .set_ramp_delay = rk806_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) .set_suspend_voltage = rk806_set_suspend_voltage_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) .resume = rk806_regulator_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) .set_suspend_enable = rk806_set_suspend_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) .set_suspend_disable = rk806_set_suspend_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define RK806_REGULATOR(_name, _supply_name, _id, _ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) _n_voltages, _vr, _er, _lr, ctrl_bit)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) [_id] = {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) .name = _name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) .supply_name = _supply_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .of_match = of_match_ptr(_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) .id = _id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .ops = &_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .n_voltages = _n_voltages,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .linear_ranges = _lr,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .n_linear_ranges = ARRAY_SIZE(_lr),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .vsel_reg = _vr,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .vsel_mask = 0xff,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .enable_reg = _er,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) .enable_mask = ENABLE_MASK(ctrl_bit),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) .enable_val = ENABLE_MASK(ctrl_bit),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .disable_val = DISABLE_VAL(ctrl_bit),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .of_map_mode = rk806_regulator_of_map_mode,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const struct regulator_desc rk806_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) RK806_REGULATOR("DCDC_REG1", "vcc1", RK806_ID_DCDC1, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) RK806_BUCK_SEL_CNT, RK806_BUCK1_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) RK806_POWER_EN0, rk806_buck_voltage_ranges, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) RK806_REGULATOR("DCDC_REG2", "vcc2", RK806_ID_DCDC2, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) RK806_BUCK_SEL_CNT, RK806_BUCK2_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) RK806_POWER_EN0, rk806_buck_voltage_ranges, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) RK806_REGULATOR("DCDC_REG3", "vcc3", RK806_ID_DCDC3, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) RK806_BUCK_SEL_CNT, RK806_BUCK3_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) RK806_POWER_EN0, rk806_buck_voltage_ranges, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) RK806_REGULATOR("DCDC_REG4", "vcc4", RK806_ID_DCDC4, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) RK806_BUCK_SEL_CNT, RK806_BUCK4_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) RK806_POWER_EN0, rk806_buck_voltage_ranges, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) RK806_REGULATOR("DCDC_REG5", "vcc5", RK806_ID_DCDC5, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) RK806_BUCK_SEL_CNT, RK806_BUCK5_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) RK806_POWER_EN1, rk806_buck_voltage_ranges, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) RK806_REGULATOR("DCDC_REG6", "vcc6", RK806_ID_DCDC6, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) RK806_BUCK_SEL_CNT, RK806_BUCK6_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) RK806_POWER_EN1, rk806_buck_voltage_ranges, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) RK806_REGULATOR("DCDC_REG7", "vcc7", RK806_ID_DCDC7, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) RK806_BUCK_SEL_CNT, RK806_BUCK7_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) RK806_POWER_EN1, rk806_buck_voltage_ranges, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) RK806_REGULATOR("DCDC_REG8", "vcc8", RK806_ID_DCDC8, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) RK806_BUCK_SEL_CNT, RK806_BUCK8_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) RK806_POWER_EN1, rk806_buck_voltage_ranges, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) RK806_REGULATOR("DCDC_REG9", "vcc9", RK806_ID_DCDC9, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) RK806_BUCK_SEL_CNT, RK806_BUCK9_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) RK806_POWER_EN2, rk806_buck_voltage_ranges, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) RK806_REGULATOR("DCDC_REG10", "vcc10", RK806_ID_DCDC10, rk806_ops_dcdc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) RK806_BUCK_SEL_CNT, RK806_BUCK10_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) RK806_POWER_EN2, rk806_buck_voltage_ranges, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) RK806_REGULATOR("NLDO_REG1", "vcc13", RK806_ID_NLDO1, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) RK806_LDO_SEL_CNT, RK806_NLDO1_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) RK806_POWER_EN3, rk806_ldo_voltage_ranges, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) RK806_REGULATOR("NLDO_REG2", "vcc13", RK806_ID_NLDO2, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) RK806_LDO_SEL_CNT, RK806_NLDO2_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) RK806_POWER_EN3, rk806_ldo_voltage_ranges, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) RK806_REGULATOR("NLDO_REG3", "vcc13", RK806_ID_NLDO3, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) RK806_LDO_SEL_CNT, RK806_NLDO3_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) RK806_POWER_EN3, rk806_ldo_voltage_ranges, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) RK806_REGULATOR("NLDO_REG4", "vcc14", RK806_ID_NLDO4, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) RK806_LDO_SEL_CNT, RK806_NLDO4_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) RK806_POWER_EN3, rk806_ldo_voltage_ranges, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) RK806_REGULATOR("NLDO_REG5", "vcc14", RK806_ID_NLDO5, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) RK806_LDO_SEL_CNT, RK806_NLDO5_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) RK806_POWER_EN5, rk806_ldo_voltage_ranges, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) RK806_REGULATOR("PLDO_REG1", "vcc11", RK806_ID_PLDO1, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) RK806_LDO_SEL_CNT, RK806_PLDO1_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) RK806_POWER_EN4, rk806_ldo_voltage_ranges, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) RK806_REGULATOR("PLDO_REG2", "vcc11", RK806_ID_PLDO2, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) RK806_LDO_SEL_CNT, RK806_PLDO2_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) RK806_POWER_EN4, rk806_ldo_voltage_ranges, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) RK806_REGULATOR("PLDO_REG3", "vcc11", RK806_ID_PLDO3, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) RK806_LDO_SEL_CNT, RK806_PLDO3_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) RK806_POWER_EN4, rk806_ldo_voltage_ranges, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) RK806_REGULATOR("PLDO_REG4", "vcc12", RK806_ID_PLDO4, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) RK806_LDO_SEL_CNT, RK806_PLDO4_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) RK806_POWER_EN5, rk806_ldo_voltage_ranges, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) RK806_REGULATOR("PLDO_REG5", "vcc12", RK806_ID_PLDO5, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) RK806_LDO_SEL_CNT, RK806_PLDO5_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) RK806_POWER_EN5, rk806_ldo_voltage_ranges, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) RK806_REGULATOR("PLDO_REG6", "vcca", RK806_ID_PLDO6, rk806_ops_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) RK806_LDO_SEL_CNT, RK806_PLDO6_ON_VSEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) RK806_POWER_EN4, rk806_ldo_voltage_ranges, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static void rk806_regulator_dt_parse_pdata(struct rk806 *rk806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct regmap *map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct rk806_regulator_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) char dvs_ctrl_name[10][32] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "dvs_default",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "start_dvs1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "start_dvs2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "start_dvs3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "dvs_pin1_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "dvs_pin2_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "dvs_pin3_ctrl",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "start_and_pwrctrl1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) "start_and_pwrctrl2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "start_and_pwrctrl3"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) char dvs_pin_name[3][30] = { "rk806,pmic-dvs-gpio1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "rk806,pmic-dvs-gpio2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "rk806,pmic-dvs-gpio3" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct device_node *np = rk806->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) pdata->support_dvs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) for (i = 0; i < RK806_ID_END; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pdata->dvs_field[i] = rk806_dvs_fields[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pdata->dvs_ctrl_id[i] = start_dvs_id[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) pdata->vsel_ctrl_id[i] = vsel_ctr_sel_id[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) for (j = 1; j < RK806_DVS_END; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (device_property_present(rk806->dev, dvs_ctrl_name[j])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) REG_DBG("%s:\n", dvs_ctrl_name[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) for (i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) (dn = of_parse_phandle(np, dvs_ctrl_name[j], i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) REG_DBG("\t%s\n", dn->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pdata->support_dvs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) pdata->dvs_dn[j][i] = dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) pdata->dvs_count[j]++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) of_node_put(dn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (i >= RK806_ID_END)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (!pdata->support_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) pdata->dvs_gpios[i] = devm_gpiod_get_optional(rk806->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dvs_pin_name[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (IS_ERR(pdata->dvs_gpios[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) pdata->dvs_gpios[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_info(rk806->dev, "Failed to get %s\n", dvs_pin_name[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static int rk806_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct rk806 *rk806 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct rk806_regulator_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) rk806_regulator_dt_parse_pdata(rk806, rk806->regmap, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) pdata->rk806 = rk806;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) platform_set_drvdata(pdev, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) config.driver_data = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) config.dev->of_node = rk806->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) config.regmap = rk806->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) for (i = 0; i < ARRAY_SIZE(rk806_regulators); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) &rk806_regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_err(rk806->dev, "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) rk806_regulator_sync_voltage(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) pdata->regulator_init = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int __maybe_unused rk806_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct rk806 *rk806 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) rk806_field_write(rk806, PWRCTRL2_FUN, PWRCTRL_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) rk806_field_write(rk806, PWRCTRL3_FUN, PWRCTRL_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) rk806_field_write(rk806, BUCK1_VSEL_CTR_SEL + i, CTR_BY_NO_EFFECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_DVS_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) rk806_field_write(rk806, BUCK1_VSEL_CTR_SEL + i, CTR_BY_PWRCTRL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) static int __maybe_unused rk806_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct rk806 *rk806 = dev_get_drvdata(dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) for (i = RK806_ID_DCDC1; i < RK806_ID_END; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) rk806_field_write(rk806, BUCK1_VSEL_CTR_SEL + i, CTR_BY_NO_EFFECT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) rk806_field_write(rk806, PWRCTRL1_FUN, PWRCTRL_NULL_FUN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SIMPLE_DEV_PM_OPS(rk806_pm_ops, rk806_suspend, rk806_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) static void rk806_regulator_shutdown(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) struct rk806 *rk806 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (system_state == SYSTEM_POWER_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if ((rk806->pins->p) && (rk806->pins->power_off))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) pinctrl_select_state(rk806->pins->p, rk806->pins->power_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (system_state == SYSTEM_RESTART)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if ((rk806->pins->p) && (rk806->pins->reset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pinctrl_select_state(rk806->pins->p, rk806->pins->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const struct platform_device_id rk806_regulator_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) { "rk806-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) MODULE_DEVICE_TABLE(platform, rk806_regulator_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static struct platform_driver rk806_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .name = "rk806-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .pm = &rk806_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .probe = rk806_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .id_table = rk806_regulator_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .shutdown = rk806_regulator_shutdown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) module_platform_driver(rk806_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) MODULE_DESCRIPTION("rk806 voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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