Orange Pi5 kernel

Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards

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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * pv88090-regulator.h - Regulator definitions for PV88090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2015 Powerventure Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __PV88090_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __PV88090_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* System Control and Event Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define	PV88090_REG_EVENT_A			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define	PV88090_REG_MASK_A			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define	PV88090_REG_MASK_B			0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Regulator Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define	PV88090_REG_BUCK1_CONF0			0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define	PV88090_REG_BUCK1_CONF1			0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define	PV88090_REG_BUCK1_CONF2			0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define	PV88090_REG_BUCK2_CONF0			0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define	PV88090_REG_BUCK2_CONF1			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define	PV88090_REG_BUCK2_CONF2			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define	PV88090_REG_BUCK3_CONF0			0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define	PV88090_REG_BUCK3_CONF1			0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define	PV88090_REG_BUCK3_CONF2			0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define	PV88090_REG_LDO1_CONT			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define	PV88090_REG_LDO2_CONT			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define	PV88090_REG_LDO3_CONT			0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define	PV88090_REG_BUCK_FOLD_RANGE			0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* PV88090_REG_EVENT_A (addr=0x03) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define	PV88090_E_VDD_FLT				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define	PV88090_E_OVER_TEMP			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* PV88090_REG_MASK_A (addr=0x06) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	PV88090_M_VDD_FLT				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define	PV88090_M_OVER_TEMP			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* PV88090_REG_BUCK1_CONF0 (addr=0x18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define	PV88090_BUCK1_EN				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PV88090_VBUCK1_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* PV88090_REG_BUCK2_CONF0 (addr=0x1b) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	PV88090_BUCK2_EN				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PV88090_VBUCK2_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* PV88090_REG_BUCK3_CONF0 (addr=0x1d) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	PV88090_BUCK3_EN				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PV88090_VBUCK3_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* PV88090_REG_LDO1_CONT (addr=0x1f) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define	PV88090_LDO1_EN				0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PV88090_VLDO1_MASK			0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* PV88090_REG_LDO2_CONT (addr=0x20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define	PV88090_LDO2_EN				0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PV88090_VLDO2_MASK			0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* PV88090_REG_BUCK1_CONF1 (addr=0x19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PV88090_BUCK1_ILIM_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PV88090_BUCK1_ILIM_MASK			0x7C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PV88090_BUCK1_MODE_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* PV88090_REG_BUCK2_CONF1 (addr=0x1c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PV88090_BUCK2_ILIM_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PV88090_BUCK2_ILIM_MASK			0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PV88090_BUCK2_MODE_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* PV88090_REG_BUCK3_CONF1 (addr=0x1e) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PV88090_BUCK3_ILIM_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PV88090_BUCK3_ILIM_MASK			0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PV88090_BUCK3_MODE_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define	PV88090_BUCK_MODE_SLEEP			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define	PV88090_BUCK_MODE_AUTO			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define	PV88090_BUCK_MODE_SYNC			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* PV88090_REG_BUCK2_CONF2 (addr=0x58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PV88090_REG_BUCK3_CONF2 (addr=0x5c) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PV88090_BUCK_VDAC_RANGE_SHIFT			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PV88090_BUCK_VDAC_RANGE_MASK			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PV88090_BUCK_VDAC_RANGE_1			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PV88090_BUCK_VDAC_RANGE_2			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* PV88090_REG_BUCK_FOLD_RANGE (addr=0x61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PV88090_BUCK_VRANGE_GAIN_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PV88090_BUCK_VRANGE_GAIN_MASK			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PV88090_BUCK_VRANGE_GAIN_1			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PV88090_BUCK_VRANGE_GAIN_2			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif	/* __PV88090_REGISTERS_H__ */