Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // pv88090-regulator.c - Regulator device driver for PV88090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright (C) 2015  Powerventure Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include "pv88090-regulator.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PV88090_MAX_REGULATORS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* PV88090 REGULATOR IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	/* BUCKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	PV88090_ID_BUCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	PV88090_ID_BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	PV88090_ID_BUCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	/* LDOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	PV88090_ID_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	PV88090_ID_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) struct pv88090_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	unsigned int conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	unsigned int conf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) struct pv88090 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct regulator_dev *rdev[PV88090_MAX_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) struct pv88090_buck_voltage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	int min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int uV_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) static const struct regmap_config pv88090_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* Current limits array (in uA) for BUCK1, BUCK2, BUCK3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  *  Entry indexes corresponds to register values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static const unsigned int pv88090_buck1_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	 220000,  440000,  660000,  880000, 1100000, 1320000, 1540000, 1760000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	1980000, 2200000, 2420000, 2640000, 2860000, 3080000, 3300000, 3520000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	3740000, 3960000, 4180000, 4400000, 4620000, 4840000, 5060000, 5280000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	5500000, 5720000, 5940000, 6160000, 6380000, 6600000, 6820000, 7040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static const unsigned int pv88090_buck23_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	1496000, 2393000, 3291000, 4189000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const struct pv88090_buck_voltage pv88090_buck_vol[3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.min_uV = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.max_uV = 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.uV_step = 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.min_uV = 1400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.max_uV = 2193750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.uV_step = 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.min_uV = 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.max_uV = 2837500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.uV_step = 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static unsigned int pv88090_buck_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct pv88090_regulator *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int ret, mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	ret = regmap_read(rdev->regmap, info->conf, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	switch (data & PV88090_BUCK1_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	case PV88090_BUCK_MODE_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		mode = REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	case PV88090_BUCK_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		mode = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	case PV88090_BUCK_MODE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		mode = REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int pv88090_buck_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 					unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	struct pv88090_regulator *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		val = PV88090_BUCK_MODE_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		val = PV88090_BUCK_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		val = PV88090_BUCK_MODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	return regmap_update_bits(rdev->regmap, info->conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 					PV88090_BUCK1_MODE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static const struct regulator_ops pv88090_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	.get_mode = pv88090_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	.set_mode = pv88090_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.set_current_limit = regulator_set_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.get_current_limit = regulator_get_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regulator_ops pv88090_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PV88090_BUCK(chip, regl_name, min, step, max, limits_array) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.desc	=	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.id = chip##_ID_##regl_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.name = __stringify(chip##_##regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.of_match = of_match_ptr(#regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		.regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.ops = &pv88090_buck_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.n_voltages = ((max) - (min))/(step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.enable_reg = PV88090_REG_##regl_name##_CONF0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.enable_mask = PV88090_##regl_name##_EN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.vsel_reg = PV88090_REG_##regl_name##_CONF0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.vsel_mask = PV88090_V##regl_name##_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.curr_table = limits_array, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		.n_current_limits = ARRAY_SIZE(limits_array), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		.csel_reg = PV88090_REG_##regl_name##_CONF1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		.csel_mask = PV88090_##regl_name##_ILIM_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.conf = PV88090_REG_##regl_name##_CONF1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.conf2 = PV88090_REG_##regl_name##_CONF2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PV88090_LDO(chip, regl_name, min, step, max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.desc	=	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.id = chip##_ID_##regl_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		.name = __stringify(chip##_##regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		.of_match = of_match_ptr(#regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		.regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		.ops = &pv88090_ldo_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.n_voltages = ((max) - (min))/(step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.enable_reg = PV88090_REG_##regl_name##_CONT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.enable_mask = PV88090_##regl_name##_EN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.vsel_reg = PV88090_REG_##regl_name##_CONT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.vsel_mask = PV88090_V##regl_name##_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static struct pv88090_regulator pv88090_regulator_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	PV88090_BUCK(PV88090, BUCK1, 600000, 6250, 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		pv88090_buck1_limits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	PV88090_BUCK(PV88090, BUCK2, 600000, 6250, 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		pv88090_buck23_limits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	PV88090_BUCK(PV88090, BUCK3, 600000, 6250, 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		pv88090_buck23_limits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	PV88090_LDO(PV88090, LDO1, 1200000, 50000, 4350000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	PV88090_LDO(PV88090, LDO2,  650000, 25000, 2225000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static irqreturn_t pv88090_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct pv88090 *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	int i, reg_val, err, ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	err = regmap_read(chip->regmap, PV88090_REG_EVENT_A, &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (reg_val & PV88090_E_VDD_FLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		for (i = 0; i < PV88090_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 			if (chip->rdev[i] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 				regulator_notifier_call_chain(chip->rdev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					REGULATOR_EVENT_UNDER_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 					NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		err = regmap_write(chip->regmap, PV88090_REG_EVENT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			PV88090_E_VDD_FLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 			goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (reg_val & PV88090_E_OVER_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		for (i = 0; i < PV88090_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 			if (chip->rdev[i] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 				regulator_notifier_call_chain(chip->rdev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 					REGULATOR_EVENT_OVER_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 					NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		err = regmap_write(chip->regmap, PV88090_REG_EVENT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 			PV88090_E_OVER_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 			goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) error_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	dev_err(chip->dev, "I2C error : %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * I2C driver interface functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int pv88090_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct regulator_init_data *init_data = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct pv88090 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	int error, i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	unsigned int conf2, range, index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	chip = devm_kzalloc(&i2c->dev, sizeof(struct pv88090), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	chip->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	chip->regmap = devm_regmap_init_i2c(i2c, &pv88090_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	if (IS_ERR(chip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		error = PTR_ERR(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		dev_err(chip->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 			error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	i2c_set_clientdata(i2c, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (i2c->irq != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		ret = regmap_write(chip->regmap, PV88090_REG_MASK_A, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				"Failed to mask A reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		ret = regmap_write(chip->regmap, PV88090_REG_MASK_B, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 				"Failed to mask B reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 					pv88090_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 					IRQF_TRIGGER_LOW|IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 					"pv88090", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 			dev_err(chip->dev, "Failed to request IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 				i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		ret = regmap_update_bits(chip->regmap, PV88090_REG_MASK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 			PV88090_M_VDD_FLT | PV88090_M_OVER_TEMP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 				"Failed to update mask reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		dev_warn(chip->dev, "No IRQ configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	config.dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	config.regmap = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	for (i = 0; i < PV88090_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		if (init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			config.init_data = &init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (i == PV88090_ID_BUCK2 || i == PV88090_ID_BUCK3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				pv88090_regulator_info[i].conf2, &conf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			conf2 = (conf2 >> PV88090_BUCK_VDAC_RANGE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				PV88090_BUCK_VDAC_RANGE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 			ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 				PV88090_REG_BUCK_FOLD_RANGE, &range);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 				return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 			range = (range >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 				 (PV88090_BUCK_VRANGE_GAIN_SHIFT + i - 1)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				PV88090_BUCK_VRANGE_GAIN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			index = ((range << 1) | conf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 			if (index > PV88090_ID_BUCK3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 				dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 					"Invalid index(%d)\n", index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			pv88090_regulator_info[i].desc.min_uV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 				= pv88090_buck_vol[index].min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			pv88090_regulator_info[i].desc.uV_step
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 				= pv88090_buck_vol[index].uV_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			pv88090_regulator_info[i].desc.n_voltages
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 				= ((pv88090_buck_vol[index].max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 				- (pv88090_buck_vol[index].min_uV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 				/(pv88090_buck_vol[index].uV_step) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		config.driver_data = (void *)&pv88090_regulator_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		chip->rdev[i] = devm_regulator_register(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			&pv88090_regulator_info[i].desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		if (IS_ERR(chip->rdev[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 				"Failed to register PV88090 regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			return PTR_ERR(chip->rdev[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct i2c_device_id pv88090_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	{"pv88090", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) MODULE_DEVICE_TABLE(i2c, pv88090_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct of_device_id pv88090_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	{ .compatible = "pvs,pv88090", .data = &pv88090_i2c_id[0] },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MODULE_DEVICE_TABLE(of, pv88090_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct i2c_driver pv88090_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.name = "pv88090",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		.of_match_table = of_match_ptr(pv88090_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	.probe_new = pv88090_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	.id_table = pv88090_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) module_i2c_driver(pv88090_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) MODULE_AUTHOR("James Ban <James.Ban.opensource@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MODULE_DESCRIPTION("Regulator device driver for Powerventure PV88090");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MODULE_LICENSE("GPL");