Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // pv88080-regulator.c - Regulator device driver for PV88080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Copyright (C) 2016  Powerventure Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "pv88080-regulator.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PV88080_MAX_REGULATORS	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* PV88080 REGULATOR IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 	/* BUCKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	PV88080_ID_BUCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	PV88080_ID_BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	PV88080_ID_BUCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	PV88080_ID_HVBUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) enum pv88080_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	TYPE_PV88080_AA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	TYPE_PV88080_BA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct pv88080_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	unsigned int mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	unsigned int conf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	unsigned int conf5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct pv88080 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	struct regulator_dev *rdev[PV88080_MAX_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	unsigned long type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	const struct pv88080_compatible_regmap *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) struct pv88080_buck_voltage {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	int min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int uV_step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct pv88080_buck_regmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	/* REGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int buck_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int buck_vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	int buck_mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int buck_limit_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int buck_vdac_range_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int buck_vrange_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	/* MASKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	int buck_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	int buck_vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int buck_limit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct pv88080_compatible_regmap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	/* BUCK1, 2, 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct pv88080_buck_regmap buck_regmap[PV88080_MAX_REGULATORS-1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	/* HVBUCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	int hvbuck_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int hvbuck_vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int hvbuck_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int hvbuck_vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static const struct regmap_config pv88080_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Current limits array (in uA) for BUCK1, BUCK2, BUCK3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87)  * Entry indexes corresponds to register values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static const unsigned int pv88080_buck1_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	3230000, 5130000, 6960000, 8790000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static const unsigned int pv88080_buck23_limits[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	1496000, 2393000, 3291000, 4189000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static const struct pv88080_buck_voltage pv88080_buck_vol[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.min_uV = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.max_uV = 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.uV_step = 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.min_uV = 1400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.max_uV = 2193750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.uV_step = 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct pv88080_compatible_regmap pv88080_aa_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* BUCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.buck_regmap[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 		.buck_enable_reg      = PV88080AA_REG_BUCK1_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		.buck_vsel_reg        = PV88080AA_REG_BUCK1_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 		.buck_mode_reg        = PV88080AA_REG_BUCK1_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		.buck_limit_reg       = PV88080AA_REG_BUCK1_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 		.buck_vdac_range_reg  = PV88080AA_REG_BUCK1_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 		.buck_vrange_gain_reg = PV88080AA_REG_BUCK1_CONF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		.buck_enable_mask     = PV88080_BUCK1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		.buck_vsel_mask       = PV88080_VBUCK1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		.buck_limit_mask      = PV88080_BUCK1_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	/* BUCK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.buck_regmap[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.buck_enable_reg      = PV88080AA_REG_BUCK2_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.buck_vsel_reg        = PV88080AA_REG_BUCK2_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.buck_mode_reg        = PV88080AA_REG_BUCK2_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.buck_limit_reg	      = PV88080AA_REG_BUCK2_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.buck_vdac_range_reg  = PV88080AA_REG_BUCK2_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.buck_vrange_gain_reg = PV88080AA_REG_BUCK2_CONF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.buck_enable_mask	  = PV88080_BUCK2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.buck_vsel_mask       = PV88080_VBUCK2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.buck_limit_mask      = PV88080_BUCK2_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	/* BUCK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.buck_regmap[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		.buck_enable_reg	  = PV88080AA_REG_BUCK3_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		.buck_vsel_reg        = PV88080AA_REG_BUCK3_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 		.buck_mode_reg        = PV88080AA_REG_BUCK3_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		.buck_limit_reg	      = PV88080AA_REG_BUCK3_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		.buck_vdac_range_reg  = PV88080AA_REG_BUCK3_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		.buck_vrange_gain_reg = PV88080AA_REG_BUCK3_CONF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		.buck_enable_mask	  = PV88080_BUCK3_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		.buck_vsel_mask       = PV88080_VBUCK3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		.buck_limit_mask      = PV88080_BUCK3_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	/* HVBUCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.hvbuck_enable_reg	      = PV88080AA_REG_HVBUCK_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.hvbuck_vsel_reg          = PV88080AA_REG_HVBUCK_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.hvbuck_enable_mask       = PV88080_HVBUCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.hvbuck_vsel_mask         = PV88080_VHVBUCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct pv88080_compatible_regmap pv88080_ba_regs = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* BUCK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	.buck_regmap[0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		.buck_enable_reg	  = PV88080BA_REG_BUCK1_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		.buck_vsel_reg        = PV88080BA_REG_BUCK1_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		.buck_mode_reg        = PV88080BA_REG_BUCK1_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		.buck_limit_reg       = PV88080BA_REG_BUCK1_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		.buck_vdac_range_reg  = PV88080BA_REG_BUCK1_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		.buck_vrange_gain_reg = PV88080BA_REG_BUCK1_CONF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		.buck_enable_mask     = PV88080_BUCK1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		.buck_vsel_mask       = PV88080_VBUCK1_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		.buck_limit_mask	  = PV88080_BUCK1_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	/* BUCK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	.buck_regmap[1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		.buck_enable_reg	  = PV88080BA_REG_BUCK2_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		.buck_vsel_reg        = PV88080BA_REG_BUCK2_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		.buck_mode_reg        = PV88080BA_REG_BUCK2_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		.buck_limit_reg	      = PV88080BA_REG_BUCK2_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		.buck_vdac_range_reg  = PV88080BA_REG_BUCK2_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		.buck_vrange_gain_reg = PV88080BA_REG_BUCK2_CONF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 		.buck_enable_mask	  = PV88080_BUCK2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		.buck_vsel_mask       = PV88080_VBUCK2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		.buck_limit_mask	  = PV88080_BUCK2_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* BUCK3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.buck_regmap[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		.buck_enable_reg	  = PV88080BA_REG_BUCK3_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		.buck_vsel_reg        = PV88080BA_REG_BUCK3_CONF0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		.buck_mode_reg        = PV88080BA_REG_BUCK3_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		.buck_limit_reg	      = PV88080BA_REG_BUCK3_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		.buck_vdac_range_reg  = PV88080BA_REG_BUCK3_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		.buck_vrange_gain_reg = PV88080BA_REG_BUCK3_CONF5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		.buck_enable_mask	  = PV88080_BUCK3_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		.buck_vsel_mask       = PV88080_VBUCK3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		.buck_limit_mask	  = PV88080_BUCK3_ILIM_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	/* HVBUCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.hvbuck_enable_reg	      = PV88080BA_REG_HVBUCK_CONF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.hvbuck_vsel_reg          = PV88080BA_REG_HVBUCK_CONF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.hvbuck_enable_mask       = PV88080_HVBUCK_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.hvbuck_vsel_mask		  = PV88080_VHVBUCK_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static const struct of_device_id pv88080_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	{ .compatible = "pvs,pv88080",    .data = (void *)TYPE_PV88080_AA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	{ .compatible = "pvs,pv88080-aa", .data = (void *)TYPE_PV88080_AA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	{ .compatible = "pvs,pv88080-ba", .data = (void *)TYPE_PV88080_BA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_DEVICE_TABLE(of, pv88080_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static unsigned int pv88080_buck_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct pv88080_regulator *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int ret, mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ret = regmap_read(rdev->regmap, info->mode_reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	switch (data & PV88080_BUCK1_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	case PV88080_BUCK_MODE_SYNC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		mode = REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case PV88080_BUCK_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		mode = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case PV88080_BUCK_MODE_SLEEP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		mode = REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int pv88080_buck_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 					unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct pv88080_regulator *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		val = PV88080_BUCK_MODE_SYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		val = PV88080_BUCK_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		val = PV88080_BUCK_MODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return regmap_update_bits(rdev->regmap, info->mode_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 					PV88080_BUCK1_MODE_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static const struct regulator_ops pv88080_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.get_mode = pv88080_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.set_mode = pv88080_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.set_current_limit = regulator_set_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.get_current_limit = regulator_get_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static const struct regulator_ops pv88080_hvbuck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PV88080_BUCK(chip, regl_name, min, step, max, limits_array) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	.desc	=	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.id = chip##_ID_##regl_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.name = __stringify(chip##_##regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.of_match = of_match_ptr(#regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.ops = &pv88080_buck_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.n_voltages = ((max) - (min))/(step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.curr_table = limits_array, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.n_current_limits = ARRAY_SIZE(limits_array), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PV88080_HVBUCK(chip, regl_name, min, step, max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.desc	=	{\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.id = chip##_ID_##regl_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.name = __stringify(chip##_##regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		.of_match = of_match_ptr(#regl_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		.regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.ops = &pv88080_hvbuck_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.min_uV = min, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.uV_step = step, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.n_voltages = ((max) - (min))/(step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static struct pv88080_regulator pv88080_regulator_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	PV88080_BUCK(PV88080, BUCK1, 600000, 6250, 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		pv88080_buck1_limits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	PV88080_BUCK(PV88080, BUCK2, 600000, 6250, 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		pv88080_buck23_limits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	PV88080_BUCK(PV88080, BUCK3, 600000, 6250, 1393750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		pv88080_buck23_limits),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	PV88080_HVBUCK(PV88080, HVBUCK, 0, 5000, 1275000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static irqreturn_t pv88080_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	struct pv88080 *chip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	int i, reg_val, err, ret = IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	err = regmap_read(chip->regmap, PV88080_REG_EVENT_A, &reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (reg_val & PV88080_E_VDD_FLT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		for (i = 0; i < PV88080_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			if (chip->rdev[i] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 				regulator_notifier_call_chain(chip->rdev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 					REGULATOR_EVENT_UNDER_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 					NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 		err = regmap_write(chip->regmap, PV88080_REG_EVENT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			PV88080_E_VDD_FLT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	if (reg_val & PV88080_E_OVER_TEMP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		for (i = 0; i < PV88080_MAX_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			if (chip->rdev[i] != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				regulator_notifier_call_chain(chip->rdev[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 					REGULATOR_EVENT_OVER_TEMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 					NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		err = regmap_write(chip->regmap, PV88080_REG_EVENT_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 			PV88080_E_OVER_TEMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			goto error_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		ret = IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) error_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	dev_err(chip->dev, "I2C error : %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)  * I2C driver interface functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int pv88080_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	struct regulator_init_data *init_data = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	struct pv88080 *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	const struct pv88080_compatible_regmap *regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	int i, error, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	unsigned int conf2, conf5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	chip = devm_kzalloc(&i2c->dev, sizeof(struct pv88080), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	chip->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	chip->regmap = devm_regmap_init_i2c(i2c, &pv88080_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (IS_ERR(chip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		error = PTR_ERR(chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		dev_err(chip->dev, "Failed to allocate register map: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	if (i2c->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		match = of_match_node(pv88080_dt_ids, i2c->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 			dev_err(chip->dev, "Failed to get of_match_node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		chip->type = (unsigned long)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		chip->type = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	i2c_set_clientdata(i2c, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	if (i2c->irq != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		ret = regmap_write(chip->regmap, PV88080_REG_MASK_A, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 				"Failed to mask A reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		ret = regmap_write(chip->regmap, PV88080_REG_MASK_B, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 				"Failed to mask B reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		ret = regmap_write(chip->regmap, PV88080_REG_MASK_C, 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 				"Failed to mask C reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 					pv88080_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 					IRQF_TRIGGER_LOW|IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 					"pv88080", chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			dev_err(chip->dev, "Failed to request IRQ: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 				i2c->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		ret = regmap_update_bits(chip->regmap, PV88080_REG_MASK_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			PV88080_M_VDD_FLT | PV88080_M_OVER_TEMP, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 				"Failed to update mask reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		dev_warn(chip->dev, "No IRQ configured\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	switch (chip->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	case TYPE_PV88080_AA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		chip->regmap_config = &pv88080_aa_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	case TYPE_PV88080_BA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		chip->regmap_config = &pv88080_ba_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	regmap_config = chip->regmap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	config.dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	config.regmap = chip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	/* Registeration for BUCK1, 2, 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	for (i = 0; i < PV88080_MAX_REGULATORS-1; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		if (init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 			config.init_data = &init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		pv88080_regulator_info[i].desc.csel_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 			= regmap_config->buck_regmap[i].buck_limit_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 		pv88080_regulator_info[i].desc.csel_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 			= regmap_config->buck_regmap[i].buck_limit_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		pv88080_regulator_info[i].mode_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 			= regmap_config->buck_regmap[i].buck_mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		pv88080_regulator_info[i].conf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 			= regmap_config->buck_regmap[i].buck_vdac_range_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		pv88080_regulator_info[i].conf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 			= regmap_config->buck_regmap[i].buck_vrange_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		pv88080_regulator_info[i].desc.enable_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 			= regmap_config->buck_regmap[i].buck_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		pv88080_regulator_info[i].desc.enable_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 			= regmap_config->buck_regmap[i].buck_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		pv88080_regulator_info[i].desc.vsel_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 			= regmap_config->buck_regmap[i].buck_vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		pv88080_regulator_info[i].desc.vsel_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 			= regmap_config->buck_regmap[i].buck_vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 				pv88080_regulator_info[i].conf2, &conf2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		conf2 = ((conf2 >> PV88080_BUCK_VDAC_RANGE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 			PV88080_BUCK_VDAC_RANGE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		ret = regmap_read(chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 				pv88080_regulator_info[i].conf5, &conf5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		conf5 = ((conf5 >> PV88080_BUCK_VRANGE_GAIN_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 			PV88080_BUCK_VRANGE_GAIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 		pv88080_regulator_info[i].desc.min_uV =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 			pv88080_buck_vol[conf2].min_uV * (conf5+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		pv88080_regulator_info[i].desc.uV_step =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 			pv88080_buck_vol[conf2].uV_step * (conf5+1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		pv88080_regulator_info[i].desc.n_voltages =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 			((pv88080_buck_vol[conf2].max_uV * (conf5+1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 			- (pv88080_regulator_info[i].desc.min_uV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 			/(pv88080_regulator_info[i].desc.uV_step) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		config.driver_data = (void *)&pv88080_regulator_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		chip->rdev[i] = devm_regulator_register(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 			&pv88080_regulator_info[i].desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		if (IS_ERR(chip->rdev[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 			dev_err(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 				"Failed to register PV88080 regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 			return PTR_ERR(chip->rdev[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	pv88080_regulator_info[PV88080_ID_HVBUCK].desc.enable_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		= regmap_config->hvbuck_enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	pv88080_regulator_info[PV88080_ID_HVBUCK].desc.enable_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		= regmap_config->hvbuck_enable_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	pv88080_regulator_info[PV88080_ID_HVBUCK].desc.vsel_reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		= regmap_config->hvbuck_vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	pv88080_regulator_info[PV88080_ID_HVBUCK].desc.vsel_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 		= regmap_config->hvbuck_vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	/* Registeration for HVBUCK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 	if (init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 		config.init_data = &init_data[PV88080_ID_HVBUCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	config.driver_data = (void *)&pv88080_regulator_info[PV88080_ID_HVBUCK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	chip->rdev[PV88080_ID_HVBUCK] = devm_regulator_register(chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 		&pv88080_regulator_info[PV88080_ID_HVBUCK].desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	if (IS_ERR(chip->rdev[PV88080_ID_HVBUCK])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 		dev_err(chip->dev, "Failed to register PV88080 regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 		return PTR_ERR(chip->rdev[PV88080_ID_HVBUCK]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static const struct i2c_device_id pv88080_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	{ "pv88080",    TYPE_PV88080_AA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	{ "pv88080-aa", TYPE_PV88080_AA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	{ "pv88080-ba", TYPE_PV88080_BA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) MODULE_DEVICE_TABLE(i2c, pv88080_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct i2c_driver pv88080_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		.name = "pv88080",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		.of_match_table = of_match_ptr(pv88080_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	.probe = pv88080_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	.id_table = pv88080_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) module_i2c_driver(pv88080_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_AUTHOR("James Ban <James.Ban.opensource@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) MODULE_DESCRIPTION("Regulator device driver for Powerventure PV88080");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_LICENSE("GPL");