Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * pv88060-regulator.h - Regulator definitions for PV88060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Copyright (C) 2015 Powerventure Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __PV88060_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __PV88060_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* System Control and Event Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define	PV88060_REG_EVENT_A			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define	PV88060_REG_MASK_A			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define	PV88060_REG_MASK_B			0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define	PV88060_REG_MASK_C			0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Regulator Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define	PV88060_REG_BUCK1_CONF0			0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define	PV88060_REG_BUCK1_CONF1			0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define	PV88060_REG_LDO1_CONF			0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define	PV88060_REG_LDO2_CONF			0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define	PV88060_REG_LDO3_CONF			0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define	PV88060_REG_LDO4_CONF			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define	PV88060_REG_LDO5_CONF			0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define	PV88060_REG_LDO6_CONF			0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define	PV88060_REG_LDO7_CONF			0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define	PV88060_REG_SW1_CONF			0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define	PV88060_REG_SW2_CONF			0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define	PV88060_REG_SW3_CONF			0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define	PV88060_REG_SW4_CONF			0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define	PV88060_REG_SW5_CONF			0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define	PV88060_REG_SW6_CONF			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* PV88060_REG_EVENT_A (addr=0x04) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define	PV88060_E_VDD_FLT			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define	PV88060_E_OVER_TEMP			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* PV88060_REG_MASK_A (addr=0x08) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define	PV88060_M_VDD_FLT			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define	PV88060_M_OVER_TEMP			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* PV88060_REG_BUCK1_CONF0 (addr=0x1B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define	PV88060_BUCK_EN			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PV88060_VBUCK_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* PV88060_REG_LDO1/2/3/4/5/6/7_CONT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define	PV88060_LDO_EN			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PV88060_VLDO_MASK			0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* PV88060_REG_SW1/2/3/4/5_CONF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define	PV88060_SW_EN			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* PV88060_REG_BUCK1_CONF1 (addr=0x1C) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define	PV88060_BUCK_ILIM_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define	PV88060_BUCK_ILIM_MASK			0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define	PV88060_BUCK_MODE_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define	PV88060_BUCK_MODE_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define	PV88060_BUCK_MODE_SLEEP			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define	PV88060_BUCK_MODE_AUTO			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define	PV88060_BUCK_MODE_SYNC			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #endif	/* __PV88060_REGISTERS_H__ */