^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/pfuze100.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PFUZE_FLAG_DISABLE_SW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PFUZE_NUMREGS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PFUZE100_VOL_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PFUZE100_STANDBY_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PFUZE100_MODE_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PFUZE100_CONF_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PFUZE100_DEVICEID 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PFUZE100_REVID 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PFUZE100_FABID 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PFUZE100_COINVOL 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PFUZE100_SW1ABVOL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PFUZE100_SW1ABMODE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PFUZE100_SW1CVOL 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PFUZE100_SW1CMODE 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PFUZE100_SW2VOL 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PFUZE100_SW2MODE 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PFUZE100_SW3AVOL 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PFUZE100_SW3AMODE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PFUZE100_SW3BVOL 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PFUZE100_SW3BMODE 0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PFUZE100_SW4VOL 0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PFUZE100_SW4MODE 0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PFUZE100_SWBSTCON1 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PFUZE100_VREFDDRCON 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PFUZE100_VSNVSVOL 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PFUZE100_VGEN1VOL 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PFUZE100_VGEN2VOL 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PFUZE100_VGEN3VOL 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PFUZE100_VGEN4VOL 0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PFUZE100_VGEN5VOL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PFUZE100_VGEN6VOL 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PFUZE100_SWxMODE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PFUZE100_SWxMODE_APS_APS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PFUZE100_SWxMODE_APS_OFF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PFUZE100_VGENxLPWR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PFUZE100_VGENxSTBY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) enum chips { PFUZE100, PFUZE200, PFUZE3000 = 3, PFUZE3001 = 0x31, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct pfuze_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) unsigned char stby_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) unsigned char stby_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool sw_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct pfuze_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct pfuze_regulator regulator_descs[PFUZE100_MAX_REGULATOR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct regulator_dev *regulators[PFUZE100_MAX_REGULATOR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct pfuze_regulator *pfuze_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const int pfuze100_swbst[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 5000000, 5050000, 5100000, 5150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const int pfuze100_vsnvs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 1000000, 1100000, 1200000, 1300000, 1500000, 1800000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const int pfuze100_coin[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 2500000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const int pfuze3000_sw1a[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 700000, 725000, 750000, 775000, 800000, 825000, 850000, 875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) 900000, 925000, 950000, 975000, 1000000, 1025000, 1050000, 1075000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 1100000, 1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 1300000, 1325000, 1350000, 1375000, 1400000, 1425000, 1800000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const int pfuze3000_sw2lo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 1500000, 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const int pfuze3000_sw2hi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 2500000, 2800000, 2850000, 3000000, 3100000, 3150000, 3200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct i2c_device_id pfuze_device_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {.name = "pfuze100", .driver_data = PFUZE100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {.name = "pfuze200", .driver_data = PFUZE200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {.name = "pfuze3000", .driver_data = PFUZE3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {.name = "pfuze3001", .driver_data = PFUZE3001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) MODULE_DEVICE_TABLE(i2c, pfuze_device_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const struct of_device_id pfuze_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { .compatible = "fsl,pfuze100", .data = (void *)PFUZE100},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) { .compatible = "fsl,pfuze200", .data = (void *)PFUZE200},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) { .compatible = "fsl,pfuze3000", .data = (void *)PFUZE3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { .compatible = "fsl,pfuze3001", .data = (void *)PFUZE3001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_DEVICE_TABLE(of, pfuze_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int pfuze100_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct pfuze_chip *pfuze100 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) bool reg_has_ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int ramp_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) switch (pfuze100->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) case PFUZE3001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* no dynamic voltage scaling for PF3001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) reg_has_ramp_delay = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) case PFUZE3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) reg_has_ramp_delay = (id < PFUZE3000_SWBST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) case PFUZE200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) reg_has_ramp_delay = (id < PFUZE200_SWBST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) case PFUZE100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) reg_has_ramp_delay = (id < PFUZE100_SWBST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) if (reg_has_ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ramp_delay > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) ramp_delay = 12500 / ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) ramp_bits = (ramp_delay >> 1) - (ramp_delay >> 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = regmap_update_bits(pfuze100->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) rdev->desc->vsel_reg + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0xc0, ramp_bits << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(pfuze100->dev, "ramp failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ret = -EACCES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const struct regulator_ops pfuze100_ldo_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct regulator_ops pfuze100_fixed_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct regulator_ops pfuze100_sw_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .set_ramp_delay = pfuze100_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static const struct regulator_ops pfuze100_sw_disable_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .set_ramp_delay = pfuze100_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct regulator_ops pfuze100_swb_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const struct regulator_ops pfuze3000_sw_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .set_ramp_delay = pfuze100_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PFUZE100_FIXED_REG(_chip, _name, base, voltage) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) [_chip ## _ ## _name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .ops = &pfuze100_fixed_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .min_uV = (voltage), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .enable_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .enable_mask = 0x10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PFUZE100_SW_REG(_chip, _name, base, min, max, step) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) [_chip ## _ ## _name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .name = #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .n_voltages = ((max) - (min)) / (step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .ops = &pfuze100_sw_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .min_uV = (min), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .uV_step = (step), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .vsel_mask = 0x3f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .enable_mask = 0xf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .stby_mask = 0x3f, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .sw_reg = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PFUZE100_SWB_REG(_chip, _name, base, mask, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) [_chip ## _ ## _name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .n_voltages = ARRAY_SIZE(voltages), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .ops = &pfuze100_swb_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .volt_table = voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .vsel_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .vsel_mask = (mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .enable_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .enable_mask = 0x48, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PFUZE100_VGEN_REG(_chip, _name, base, min, max, step) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) [_chip ## _ ## _name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .n_voltages = ((max) - (min)) / (step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .ops = &pfuze100_ldo_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .min_uV = (min), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .uV_step = (step), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .vsel_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .vsel_mask = 0xf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .enable_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .enable_mask = 0x10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .stby_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .stby_mask = 0x20, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PFUZE100_COIN_REG(_chip, _name, base, mask, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) [_chip ## _ ## _name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .n_voltages = ARRAY_SIZE(voltages), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .ops = &pfuze100_swb_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .volt_table = voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .vsel_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .vsel_mask = (mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .enable_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .enable_mask = 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PFUZE3000_VCC_REG(_chip, _name, base, min, max, step) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .n_voltages = ((max) - (min)) / (step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .ops = &pfuze100_ldo_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .min_uV = (min), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .uV_step = (step), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .vsel_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .vsel_mask = 0x3, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .enable_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .enable_mask = 0x10, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .stby_reg = (base), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .stby_mask = 0x20, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* No linar case for the some switches of PFUZE3000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PFUZE3000_SW_REG(_chip, _name, base, mask, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) [_chip ## _ ## _name] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .n_voltages = ARRAY_SIZE(voltages), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .ops = &pfuze3000_sw_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .volt_table = voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .vsel_mask = (mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .enable_reg = (base) + PFUZE100_MODE_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .enable_mask = 0xf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .enable_val = 0x8, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .enable_time = 500, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .stby_mask = (mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .sw_reg = true, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define PFUZE3000_SW3_REG(_chip, _name, base, min, max, step) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .name = #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .n_voltages = ((max) - (min)) / (step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .ops = &pfuze100_sw_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) .id = _chip ## _ ## _name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .min_uV = (min), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .uV_step = (step), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .vsel_mask = 0xf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .stby_mask = 0xf, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* PFUZE100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct pfuze_regulator pfuze100_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) PFUZE100_SW_REG(PFUZE100, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) PFUZE100_SW_REG(PFUZE100, SW1C, PFUZE100_SW1CVOL, 300000, 1875000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) PFUZE100_SW_REG(PFUZE100, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) PFUZE100_SW_REG(PFUZE100, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) PFUZE100_SW_REG(PFUZE100, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) PFUZE100_SW_REG(PFUZE100, SW4, PFUZE100_SW4VOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) PFUZE100_SWB_REG(PFUZE100, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) PFUZE100_SWB_REG(PFUZE100, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) PFUZE100_FIXED_REG(PFUZE100, VREFDDR, PFUZE100_VREFDDRCON, 750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) PFUZE100_VGEN_REG(PFUZE100, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) PFUZE100_VGEN_REG(PFUZE100, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) PFUZE100_VGEN_REG(PFUZE100, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) PFUZE100_VGEN_REG(PFUZE100, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) PFUZE100_VGEN_REG(PFUZE100, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) PFUZE100_VGEN_REG(PFUZE100, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) PFUZE100_COIN_REG(PFUZE100, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static struct pfuze_regulator pfuze200_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) PFUZE100_SW_REG(PFUZE200, SW1AB, PFUZE100_SW1ABVOL, 300000, 1875000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) PFUZE100_SW_REG(PFUZE200, SW2, PFUZE100_SW2VOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) PFUZE100_SW_REG(PFUZE200, SW3A, PFUZE100_SW3AVOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) PFUZE100_SW_REG(PFUZE200, SW3B, PFUZE100_SW3BVOL, 400000, 1975000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) PFUZE100_SWB_REG(PFUZE200, SWBST, PFUZE100_SWBSTCON1, 0x3 , pfuze100_swbst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) PFUZE100_SWB_REG(PFUZE200, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) PFUZE100_FIXED_REG(PFUZE200, VREFDDR, PFUZE100_VREFDDRCON, 750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) PFUZE100_VGEN_REG(PFUZE200, VGEN1, PFUZE100_VGEN1VOL, 800000, 1550000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) PFUZE100_VGEN_REG(PFUZE200, VGEN2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) PFUZE100_VGEN_REG(PFUZE200, VGEN3, PFUZE100_VGEN3VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) PFUZE100_VGEN_REG(PFUZE200, VGEN4, PFUZE100_VGEN4VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) PFUZE100_VGEN_REG(PFUZE200, VGEN5, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) PFUZE100_VGEN_REG(PFUZE200, VGEN6, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) PFUZE100_COIN_REG(PFUZE200, COIN, PFUZE100_COINVOL, 0x7, pfuze100_coin),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static struct pfuze_regulator pfuze3000_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) PFUZE3000_SW_REG(PFUZE3000, SW1A, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) PFUZE100_SW_REG(PFUZE3000, SW1B, PFUZE100_SW1CVOL, 700000, 1475000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) PFUZE3000_SW_REG(PFUZE3000, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) PFUZE3000_SW3_REG(PFUZE3000, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) PFUZE100_SWB_REG(PFUZE3000, SWBST, PFUZE100_SWBSTCON1, 0x3, pfuze100_swbst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) PFUZE100_SWB_REG(PFUZE3000, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) PFUZE100_FIXED_REG(PFUZE3000, VREFDDR, PFUZE100_VREFDDRCON, 750000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) PFUZE100_VGEN_REG(PFUZE3000, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PFUZE100_VGEN_REG(PFUZE3000, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) PFUZE3000_VCC_REG(PFUZE3000, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) PFUZE3000_VCC_REG(PFUZE3000, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) PFUZE100_VGEN_REG(PFUZE3000, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) PFUZE100_VGEN_REG(PFUZE3000, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static struct pfuze_regulator pfuze3001_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PFUZE3000_SW_REG(PFUZE3001, SW1, PFUZE100_SW1ABVOL, 0x1f, pfuze3000_sw1a),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) PFUZE3000_SW_REG(PFUZE3001, SW2, PFUZE100_SW2VOL, 0x7, pfuze3000_sw2lo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) PFUZE3000_SW3_REG(PFUZE3001, SW3, PFUZE100_SW3AVOL, 900000, 1650000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) PFUZE100_SWB_REG(PFUZE3001, VSNVS, PFUZE100_VSNVSVOL, 0x7, pfuze100_vsnvs),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) PFUZE100_VGEN_REG(PFUZE3001, VLDO1, PFUZE100_VGEN1VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) PFUZE100_VGEN_REG(PFUZE3001, VLDO2, PFUZE100_VGEN2VOL, 800000, 1550000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) PFUZE3000_VCC_REG(PFUZE3001, VCCSD, PFUZE100_VGEN3VOL, 2850000, 3300000, 150000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) PFUZE3000_VCC_REG(PFUZE3001, V33, PFUZE100_VGEN4VOL, 2850000, 3300000, 150000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) PFUZE100_VGEN_REG(PFUZE3001, VLDO3, PFUZE100_VGEN5VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) PFUZE100_VGEN_REG(PFUZE3001, VLDO4, PFUZE100_VGEN6VOL, 1800000, 3300000, 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* PFUZE100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static struct of_regulator_match pfuze100_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .name = "sw1ab", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .name = "sw1c", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { .name = "sw2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { .name = "sw3a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { .name = "sw3b", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { .name = "sw4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { .name = "swbst", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { .name = "vsnvs", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { .name = "vrefddr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { .name = "vgen1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { .name = "vgen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { .name = "vgen3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { .name = "vgen4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { .name = "vgen5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { .name = "vgen6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { .name = "coin", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* PFUZE200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static struct of_regulator_match pfuze200_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { .name = "sw1ab", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { .name = "sw2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { .name = "sw3a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { .name = "sw3b", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { .name = "swbst", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { .name = "vsnvs", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { .name = "vrefddr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { .name = "vgen1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { .name = "vgen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { .name = "vgen3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { .name = "vgen4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { .name = "vgen5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { .name = "vgen6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { .name = "coin", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* PFUZE3000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static struct of_regulator_match pfuze3000_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { .name = "sw1a", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { .name = "sw1b", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { .name = "sw2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { .name = "sw3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { .name = "swbst", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { .name = "vsnvs", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { .name = "vrefddr", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { .name = "vldo1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { .name = "vldo2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { .name = "vccsd", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { .name = "v33", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { .name = "vldo3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { .name = "vldo4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* PFUZE3001 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static struct of_regulator_match pfuze3001_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { .name = "sw1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { .name = "sw2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { .name = "sw3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { .name = "vsnvs", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { .name = "vldo1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { .name = "vldo2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { .name = "vccsd", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { .name = "v33", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { .name = "vldo3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { .name = "vldo4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static struct of_regulator_match *pfuze_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct device *dev = chip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct device_node *np, *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) np = of_node_get(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (of_property_read_bool(np, "fsl,pfuze-support-disable-sw"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) chip->flags |= PFUZE_FLAG_DISABLE_SW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) parent = of_get_child_by_name(np, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) dev_err(dev, "regulators node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) switch (chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) case PFUZE3001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) pfuze_matches = pfuze3001_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ret = of_regulator_match(dev, parent, pfuze3001_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ARRAY_SIZE(pfuze3001_matches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) case PFUZE3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) pfuze_matches = pfuze3000_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) ret = of_regulator_match(dev, parent, pfuze3000_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) ARRAY_SIZE(pfuze3000_matches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) case PFUZE200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) pfuze_matches = pfuze200_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = of_regulator_match(dev, parent, pfuze200_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ARRAY_SIZE(pfuze200_matches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case PFUZE100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) pfuze_matches = pfuze100_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = of_regulator_match(dev, parent, pfuze100_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ARRAY_SIZE(pfuze100_matches));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) of_node_put(parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(dev, "Error parsing regulator init data: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static inline struct regulator_init_data *match_init_data(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return pfuze_matches[index].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static inline struct device_node *match_of_node(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return pfuze_matches[index].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int pfuze_parse_regulators_dt(struct pfuze_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static inline struct regulator_init_data *match_init_data(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) static inline struct device_node *match_of_node(int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static struct pfuze_chip *syspm_pfuze_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void pfuze_power_off_prepare(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_info(syspm_pfuze_chip->dev, "Configure standby mode for power off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) /* Switch from default mode: APS/APS to APS/Off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1ABMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW1CMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW2MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3AMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW3BMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_SW4MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) PFUZE100_SWxMODE_MASK, PFUZE100_SWxMODE_APS_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN1VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) PFUZE100_VGENxSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN2VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) PFUZE100_VGENxSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN3VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) PFUZE100_VGENxSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN4VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) PFUZE100_VGENxSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN5VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) PFUZE100_VGENxSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) regmap_update_bits(syspm_pfuze_chip->regmap, PFUZE100_VGEN6VOL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) PFUZE100_VGENxLPWR | PFUZE100_VGENxSTBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) PFUZE100_VGENxSTBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int pfuze_power_off_prepare_init(struct pfuze_chip *pfuze_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (pfuze_chip->chip_id != PFUZE100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_warn(pfuze_chip->dev, "Requested pm_power_off_prepare handler for not supported chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (pm_power_off_prepare) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_warn(pfuze_chip->dev, "pm_power_off_prepare is already registered.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (syspm_pfuze_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_warn(pfuze_chip->dev, "syspm_pfuze_chip is already set.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) syspm_pfuze_chip = pfuze_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pm_power_off_prepare = pfuze_power_off_prepare;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int pfuze_identify(struct pfuze_chip *pfuze_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) unsigned int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ret = regmap_read(pfuze_chip->regmap, PFUZE100_DEVICEID, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (((value & 0x0f) == 0x8) && (pfuze_chip->chip_id == PFUZE100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * Freescale misprogrammed 1-3% of parts prior to week 8 of 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * as ID=8 in PFUZE100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) dev_info(pfuze_chip->dev, "Assuming misprogrammed ID=0x8");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) } else if ((value & 0x0f) != pfuze_chip->chip_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) (value & 0xf0) >> 4 != pfuze_chip->chip_id &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (value != pfuze_chip->chip_id)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* device id NOT match with your setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev_info(pfuze_chip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "Full layer: %x, Metal layer: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) (value & 0xf0) >> 4, value & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = regmap_read(pfuze_chip->regmap, PFUZE100_FABID, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_info(pfuze_chip->dev, "FAB: %x, FIN: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) (value & 0xc) >> 2, value & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const struct regmap_config pfuze_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .max_register = PFUZE_NUMREGS - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int pfuze100_regulator_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct pfuze_chip *pfuze_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct pfuze_regulator_platform_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u32 regulator_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 sw_check_start, sw_check_end, sw_hi = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pfuze_chip = devm_kzalloc(&client->dev, sizeof(*pfuze_chip),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (!pfuze_chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) match = of_match_device(of_match_ptr(pfuze_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (!match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_err(&client->dev, "Error: No device match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pfuze_chip->chip_id = (int)(long)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) } else if (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pfuze_chip->chip_id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) dev_err(&client->dev, "No dts match or id table match found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) i2c_set_clientdata(client, pfuze_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) pfuze_chip->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) pfuze_chip->regmap = devm_regmap_init_i2c(client, &pfuze_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (IS_ERR(pfuze_chip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = PTR_ERR(pfuze_chip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "regmap allocation failed with err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = pfuze_identify(pfuze_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev_err(&client->dev, "unrecognized pfuze chip ID!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* use the right regulators after identify the right device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) switch (pfuze_chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case PFUZE3001:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) pfuze_chip->pfuze_regulators = pfuze3001_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) regulator_num = ARRAY_SIZE(pfuze3001_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) sw_check_start = PFUZE3001_SW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sw_check_end = PFUZE3001_SW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) sw_hi = 1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case PFUZE3000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pfuze_chip->pfuze_regulators = pfuze3000_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) regulator_num = ARRAY_SIZE(pfuze3000_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sw_check_start = PFUZE3000_SW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) sw_check_end = PFUZE3000_SW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) sw_hi = 1 << 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) case PFUZE200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pfuze_chip->pfuze_regulators = pfuze200_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) regulator_num = ARRAY_SIZE(pfuze200_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) sw_check_start = PFUZE200_SW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) sw_check_end = PFUZE200_SW3B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) case PFUZE100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) pfuze_chip->pfuze_regulators = pfuze100_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) regulator_num = ARRAY_SIZE(pfuze100_regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) sw_check_start = PFUZE100_SW2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) sw_check_end = PFUZE100_SW4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dev_info(&client->dev, "pfuze%s found.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) (pfuze_chip->chip_id == PFUZE100) ? "100" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) (((pfuze_chip->chip_id == PFUZE200) ? "200" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ((pfuze_chip->chip_id == PFUZE3000) ? "3000" : "3001"))));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) memcpy(pfuze_chip->regulator_descs, pfuze_chip->pfuze_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) sizeof(pfuze_chip->regulator_descs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = pfuze_parse_regulators_dt(pfuze_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) for (i = 0; i < regulator_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct regulator_init_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) desc = &pfuze_chip->regulator_descs[i].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) init_data = pdata->init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) init_data = match_init_data(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /* SW2~SW4 high bit check and modify the voltage value table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (i >= sw_check_start && i <= sw_check_end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = regmap_read(pfuze_chip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) desc->vsel_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_err(&client->dev, "Fails to read from the register.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (val & sw_hi) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (pfuze_chip->chip_id == PFUZE3000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) pfuze_chip->chip_id == PFUZE3001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) desc->volt_table = pfuze3000_sw2hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) desc->n_voltages = ARRAY_SIZE(pfuze3000_sw2hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) desc->min_uV = 800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) desc->uV_step = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) desc->n_voltages = 51;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * Allow SW regulators to turn off. Checking it trough a flag is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * a workaround to keep the backward compatibility with existing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * old dtb's which may relay on the fact that we didn't disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * the switched regulator till yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (pfuze_chip->flags & PFUZE_FLAG_DISABLE_SW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (pfuze_chip->chip_id == PFUZE100 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pfuze_chip->chip_id == PFUZE200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (pfuze_chip->regulator_descs[i].sw_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) desc->ops = &pfuze100_sw_disable_regulator_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) desc->enable_val = 0x8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) desc->disable_val = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) desc->enable_time = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) config.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) config.init_data = init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) config.driver_data = pfuze_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) config.of_node = match_of_node(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) pfuze_chip->regulators[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) devm_regulator_register(&client->dev, desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (IS_ERR(pfuze_chip->regulators[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev_err(&client->dev, "register regulator%s failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) pfuze_chip->pfuze_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return PTR_ERR(pfuze_chip->regulators[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (of_property_read_bool(client->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "fsl,pmic-stby-poweroff"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return pfuze_power_off_prepare_init(pfuze_chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int pfuze100_regulator_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (syspm_pfuze_chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) syspm_pfuze_chip = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pm_power_off_prepare = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static struct i2c_driver pfuze_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .id_table = pfuze_device_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .name = "pfuze100-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .of_match_table = pfuze_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .probe = pfuze100_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) .remove = pfuze100_regulator_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) module_i2c_driver(pfuze_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) MODULE_AUTHOR("Robin Gong <b38343@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) MODULE_DESCRIPTION("Regulator Driver for Freescale PFUZE100/200/3000/3001 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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