^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * PCAP2 Regulator Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2009 Daniel Ribeiro <drwyrm@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/ezx-pcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static const unsigned int V1_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 2775000, 1275000, 1600000, 1725000, 1825000, 1925000, 2075000, 2275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static const unsigned int V2_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 2500000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const unsigned int V3_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 1075000, 1275000, 1550000, 1725000, 1876000, 1950000, 2075000, 2275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) static const unsigned int V4_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 1275000, 1550000, 1725000, 1875000, 1950000, 2075000, 2275000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) static const unsigned int V5_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 1875000, 2275000, 2475000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static const unsigned int V6_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 2475000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const unsigned int V7_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 1875000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define V8_table V4_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static const unsigned int V9_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1575000, 1875000, 2475000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) static const unsigned int V10_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static const unsigned int VAUX1_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 1875000, 2475000, 2775000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VAUX2_table VAUX1_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static const unsigned int VAUX3_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 1200000, 1200000, 1200000, 1200000, 1400000, 1600000, 1800000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 2200000, 2400000, 2600000, 2800000, 3000000, 3200000, 3400000, 3600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static const unsigned int VAUX4_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 1800000, 1800000, 3000000, 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static const unsigned int VSIM_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 1875000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static const unsigned int VSIM2_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 1875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static const unsigned int VVIB_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 1300000, 1800000, 2000000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const unsigned int SW1_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 900000, 950000, 1000000, 1050000, 1100000, 1150000, 1200000, 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 1300000, 1350000, 1400000, 1450000, 1500000, 1600000, 1875000, 2250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SW2_table SW1_table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct pcap_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) const u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) const u8 en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) const u8 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) const u8 stby;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) const u8 lowpwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define NA 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define VREG_INFO(_vreg, _reg, _en, _index, _stby, _lowpwr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [_vreg] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .reg = _reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .en = _en, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .index = _index, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .stby = _stby, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .lowpwr = _lowpwr, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static struct pcap_regulator vreg_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) VREG_INFO(V1, PCAP_REG_VREG1, 1, 2, 18, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) VREG_INFO(V2, PCAP_REG_VREG1, 5, 6, 19, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) VREG_INFO(V3, PCAP_REG_VREG1, 7, 8, 20, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) VREG_INFO(V4, PCAP_REG_VREG1, 11, 12, 21, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* V5 STBY and LOWPWR are on PCAP_REG_VREG2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) VREG_INFO(V5, PCAP_REG_VREG1, 15, 16, 12, 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) VREG_INFO(V6, PCAP_REG_VREG2, 1, 2, 14, 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) VREG_INFO(V7, PCAP_REG_VREG2, 3, 4, 15, 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) VREG_INFO(V8, PCAP_REG_VREG2, 5, 6, 16, 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) VREG_INFO(V9, PCAP_REG_VREG2, 9, 10, 17, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) VREG_INFO(V10, PCAP_REG_VREG2, 10, NA, 18, 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) VREG_INFO(VAUX1, PCAP_REG_AUXVREG, 1, 2, 22, 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* VAUX2 ... VSIM2 STBY and LOWPWR are on PCAP_REG_LOWPWR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) VREG_INFO(VAUX2, PCAP_REG_AUXVREG, 4, 5, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) VREG_INFO(VAUX3, PCAP_REG_AUXVREG, 7, 8, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) VREG_INFO(VAUX4, PCAP_REG_AUXVREG, 12, 13, 4, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) VREG_INFO(VSIM, PCAP_REG_AUXVREG, 17, 18, NA, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) VREG_INFO(VSIM2, PCAP_REG_AUXVREG, 16, NA, NA, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) VREG_INFO(VVIB, PCAP_REG_AUXVREG, 19, 20, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) VREG_INFO(SW1, PCAP_REG_SWCTRL, 1, 2, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) VREG_INFO(SW2, PCAP_REG_SWCTRL, 6, 7, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* SW3 STBY is on PCAP_REG_AUXVREG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) VREG_INFO(SW3, PCAP_REG_SWCTRL, 11, 12, 24, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* SWxS used to control SWx voltage on standby */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* VREG_INFO(SW1S, PCAP_REG_LOWPWR, NA, 12, NA, NA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) VREG_INFO(SW2S, PCAP_REG_LOWPWR, NA, 20, NA, NA), */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static int pcap_regulator_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) void *pcap = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* the regulator doesn't support voltage switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (rdev->desc->n_voltages == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return ezx_pcap_set_bits(pcap, vreg->reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) (rdev->desc->n_voltages - 1) << vreg->index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) selector << vreg->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int pcap_regulator_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void *pcap = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (rdev->desc->n_voltages == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ezx_pcap_read(pcap, vreg->reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tmp = ((tmp >> vreg->index) & (rdev->desc->n_voltages - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int pcap_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) void *pcap = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (vreg->en == NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 1 << vreg->en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int pcap_regulator_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) void *pcap = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (vreg->en == NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return ezx_pcap_set_bits(pcap, vreg->reg, 1 << vreg->en, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static int pcap_regulator_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct pcap_regulator *vreg = &vreg_table[rdev_get_id(rdev)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void *pcap = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (vreg->en == NA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ezx_pcap_read(pcap, vreg->reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return (tmp >> vreg->en) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct regulator_ops pcap_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .set_voltage_sel = pcap_regulator_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .get_voltage_sel = pcap_regulator_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .enable = pcap_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .disable = pcap_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .is_enabled = pcap_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define VREG(_vreg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) [_vreg] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .name = #_vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .id = _vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .n_voltages = ARRAY_SIZE(_vreg##_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .volt_table = _vreg##_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ops = &pcap_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const struct regulator_desc pcap_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) VREG(V1), VREG(V2), VREG(V3), VREG(V4), VREG(V5), VREG(V6), VREG(V7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) VREG(V8), VREG(V9), VREG(V10), VREG(VAUX1), VREG(VAUX2), VREG(VAUX3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) VREG(VAUX4), VREG(VSIM), VREG(VSIM2), VREG(VVIB), VREG(SW1), VREG(SW2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int pcap_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) void *pcap = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) config.init_data = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) config.driver_data = pcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) rdev = devm_regulator_register(&pdev->dev, &pcap_regulators[pdev->id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (IS_ERR(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) platform_set_drvdata(pdev, rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static struct platform_driver pcap_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .name = "pcap-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .probe = pcap_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int __init pcap_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return platform_driver_register(&pcap_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static void __exit pcap_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) platform_driver_unregister(&pcap_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) subsys_initcall(pcap_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) module_exit(pcap_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MODULE_AUTHOR("Daniel Ribeiro <drwyrm@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MODULE_DESCRIPTION("PCAP2 Regulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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