^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Regulator part of Palmas PMIC Chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2011-2013 Texas Instruments Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Graeme Gregory <gg@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Ian Lartey <ian@slimlogic.co.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/palmas.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static const struct linear_range smps_low_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) REGULATOR_LINEAR_RANGE(500000, 0x1, 0x6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) REGULATOR_LINEAR_RANGE(510000, 0x7, 0x79, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) REGULATOR_LINEAR_RANGE(1650000, 0x7A, 0x7f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static const struct linear_range smps_high_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) REGULATOR_LINEAR_RANGE(0, 0x0, 0x0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) REGULATOR_LINEAR_RANGE(1000000, 0x1, 0x6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) REGULATOR_LINEAR_RANGE(1020000, 0x7, 0x79, 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) REGULATOR_LINEAR_RANGE(3300000, 0x7A, 0x7f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static struct palmas_regs_info palmas_generic_regs_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .name = "SMPS12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .sname = "smps1-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) .vsel_addr = PALMAS_SMPS12_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .ctrl_addr = PALMAS_SMPS12_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .tstep_addr = PALMAS_SMPS12_TSTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .name = "SMPS123",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .sname = "smps1-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) .vsel_addr = PALMAS_SMPS12_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .ctrl_addr = PALMAS_SMPS12_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .tstep_addr = PALMAS_SMPS12_TSTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) .name = "SMPS3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .sname = "smps3-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .vsel_addr = PALMAS_SMPS3_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .ctrl_addr = PALMAS_SMPS3_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .name = "SMPS45",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .sname = "smps4-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .vsel_addr = PALMAS_SMPS45_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) .ctrl_addr = PALMAS_SMPS45_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) .tstep_addr = PALMAS_SMPS45_TSTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .name = "SMPS457",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .sname = "smps4-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .vsel_addr = PALMAS_SMPS45_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .ctrl_addr = PALMAS_SMPS45_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .tstep_addr = PALMAS_SMPS45_TSTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .name = "SMPS6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .sname = "smps6-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .vsel_addr = PALMAS_SMPS6_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .ctrl_addr = PALMAS_SMPS6_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .tstep_addr = PALMAS_SMPS6_TSTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .name = "SMPS7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .sname = "smps7-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .vsel_addr = PALMAS_SMPS7_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .ctrl_addr = PALMAS_SMPS7_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .name = "SMPS8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .sname = "smps8-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .vsel_addr = PALMAS_SMPS8_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .ctrl_addr = PALMAS_SMPS8_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .tstep_addr = PALMAS_SMPS8_TSTEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .name = "SMPS9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .sname = "smps9-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .vsel_addr = PALMAS_SMPS9_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .ctrl_addr = PALMAS_SMPS9_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .name = "SMPS10_OUT2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .sname = "smps10-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .ctrl_addr = PALMAS_SMPS10_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "SMPS10_OUT1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .sname = "smps10-out2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .ctrl_addr = PALMAS_SMPS10_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .name = "LDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .sname = "ldo1-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .vsel_addr = PALMAS_LDO1_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .ctrl_addr = PALMAS_LDO1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .name = "LDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .sname = "ldo2-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .vsel_addr = PALMAS_LDO2_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .ctrl_addr = PALMAS_LDO2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .name = "LDO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .sname = "ldo3-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) .vsel_addr = PALMAS_LDO3_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .ctrl_addr = PALMAS_LDO3_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .name = "LDO4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .sname = "ldo4-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .vsel_addr = PALMAS_LDO4_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .ctrl_addr = PALMAS_LDO4_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .name = "LDO5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .sname = "ldo5-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .vsel_addr = PALMAS_LDO5_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .ctrl_addr = PALMAS_LDO5_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .name = "LDO6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .sname = "ldo6-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .vsel_addr = PALMAS_LDO6_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .ctrl_addr = PALMAS_LDO6_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .name = "LDO7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .sname = "ldo7-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .vsel_addr = PALMAS_LDO7_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .ctrl_addr = PALMAS_LDO7_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .name = "LDO8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .sname = "ldo8-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .vsel_addr = PALMAS_LDO8_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .ctrl_addr = PALMAS_LDO8_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .name = "LDO9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .sname = "ldo9-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .vsel_addr = PALMAS_LDO9_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .ctrl_addr = PALMAS_LDO9_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "LDOLN",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .sname = "ldoln-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .vsel_addr = PALMAS_LDOLN_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .ctrl_addr = PALMAS_LDOLN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .name = "LDOUSB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .sname = "ldousb-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .vsel_addr = PALMAS_LDOUSB_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .ctrl_addr = PALMAS_LDOUSB_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "REGEN1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .ctrl_addr = PALMAS_REGEN1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .name = "REGEN2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .ctrl_addr = PALMAS_REGEN2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .name = "REGEN3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .ctrl_addr = PALMAS_REGEN3_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .name = "SYSEN1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .ctrl_addr = PALMAS_SYSEN1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .name = "SYSEN2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .ctrl_addr = PALMAS_SYSEN2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .sleep_id = PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static struct palmas_regs_info tps65917_regs_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .name = "SMPS1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .sname = "smps1-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .vsel_addr = TPS65917_SMPS1_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .ctrl_addr = TPS65917_SMPS1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .name = "SMPS2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .sname = "smps2-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .vsel_addr = TPS65917_SMPS2_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .ctrl_addr = TPS65917_SMPS2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .name = "SMPS3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .sname = "smps3-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .vsel_addr = TPS65917_SMPS3_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .ctrl_addr = TPS65917_SMPS3_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .name = "SMPS4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .sname = "smps4-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .vsel_addr = TPS65917_SMPS4_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .ctrl_addr = TPS65917_SMPS4_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .name = "SMPS5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .sname = "smps5-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .vsel_addr = TPS65917_SMPS5_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .ctrl_addr = TPS65917_SMPS5_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .name = "SMPS12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .sname = "smps1-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .vsel_addr = TPS65917_SMPS1_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .ctrl_addr = TPS65917_SMPS1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_SMPS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .name = "LDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .sname = "ldo1-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .vsel_addr = TPS65917_LDO1_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .ctrl_addr = TPS65917_LDO1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = "LDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .sname = "ldo2-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .vsel_addr = TPS65917_LDO2_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .ctrl_addr = TPS65917_LDO2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .name = "LDO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .sname = "ldo3-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .vsel_addr = TPS65917_LDO3_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .ctrl_addr = TPS65917_LDO3_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .name = "LDO4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .sname = "ldo4-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .vsel_addr = TPS65917_LDO4_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .ctrl_addr = TPS65917_LDO4_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .name = "LDO5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .sname = "ldo5-in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .vsel_addr = TPS65917_LDO5_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .ctrl_addr = TPS65917_LDO5_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "REGEN1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .ctrl_addr = TPS65917_REGEN1_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .name = "REGEN2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .ctrl_addr = TPS65917_REGEN2_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .name = "REGEN3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .ctrl_addr = TPS65917_REGEN3_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .sleep_id = TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define EXTERNAL_REQUESTOR(_id, _offset, _pos) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) [PALMAS_EXTERNAL_REQSTR_ID_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .id = PALMAS_EXTERNAL_REQSTR_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .reg_offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .bit_pos = _pos, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static struct palmas_sleep_requestor_info palma_sleep_req_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) EXTERNAL_REQUESTOR(REGEN1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) EXTERNAL_REQUESTOR(REGEN2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) EXTERNAL_REQUESTOR(SYSEN1, 0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) EXTERNAL_REQUESTOR(SYSEN2, 0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) EXTERNAL_REQUESTOR(CLK32KG, 0, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) EXTERNAL_REQUESTOR(CLK32KGAUDIO, 0, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) EXTERNAL_REQUESTOR(REGEN3, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) EXTERNAL_REQUESTOR(SMPS12, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) EXTERNAL_REQUESTOR(SMPS3, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) EXTERNAL_REQUESTOR(SMPS45, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) EXTERNAL_REQUESTOR(SMPS6, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) EXTERNAL_REQUESTOR(SMPS7, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) EXTERNAL_REQUESTOR(SMPS8, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) EXTERNAL_REQUESTOR(SMPS9, 1, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) EXTERNAL_REQUESTOR(SMPS10, 1, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) EXTERNAL_REQUESTOR(LDO1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EXTERNAL_REQUESTOR(LDO2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) EXTERNAL_REQUESTOR(LDO3, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) EXTERNAL_REQUESTOR(LDO4, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) EXTERNAL_REQUESTOR(LDO5, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) EXTERNAL_REQUESTOR(LDO6, 2, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) EXTERNAL_REQUESTOR(LDO7, 2, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) EXTERNAL_REQUESTOR(LDO8, 2, 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) EXTERNAL_REQUESTOR(LDO9, 3, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) EXTERNAL_REQUESTOR(LDOLN, 3, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) EXTERNAL_REQUESTOR(LDOUSB, 3, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EXTERNAL_REQUESTOR_TPS65917(_id, _offset, _pos) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) [TPS65917_EXTERNAL_REQSTR_ID_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .id = TPS65917_EXTERNAL_REQSTR_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .reg_offset = _offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .bit_pos = _pos, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static struct palmas_sleep_requestor_info tps65917_sleep_req_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) EXTERNAL_REQUESTOR_TPS65917(REGEN1, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) EXTERNAL_REQUESTOR_TPS65917(REGEN2, 0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) EXTERNAL_REQUESTOR_TPS65917(REGEN3, 0, 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) EXTERNAL_REQUESTOR_TPS65917(SMPS1, 1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) EXTERNAL_REQUESTOR_TPS65917(SMPS2, 1, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) EXTERNAL_REQUESTOR_TPS65917(SMPS3, 1, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) EXTERNAL_REQUESTOR_TPS65917(SMPS4, 1, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) EXTERNAL_REQUESTOR_TPS65917(SMPS5, 1, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) EXTERNAL_REQUESTOR_TPS65917(SMPS12, 1, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) EXTERNAL_REQUESTOR_TPS65917(LDO1, 2, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) EXTERNAL_REQUESTOR_TPS65917(LDO2, 2, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) EXTERNAL_REQUESTOR_TPS65917(LDO3, 2, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) EXTERNAL_REQUESTOR_TPS65917(LDO4, 2, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) EXTERNAL_REQUESTOR_TPS65917(LDO5, 2, 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const unsigned int palmas_smps_ramp_delay[4] = {0, 10000, 5000, 2500};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SMPS_CTRL_MODE_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SMPS_CTRL_MODE_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SMPS_CTRL_MODE_ECO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SMPS_CTRL_MODE_PWM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define PALMAS_SMPS_NUM_VOLTAGES 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define PALMAS_SMPS10_NUM_VOLTAGES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define PALMAS_LDO_NUM_VOLTAGES 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SMPS10_VSEL (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SMPS10_BOOST_EN (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SMPS10_BYPASS_EN (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SMPS10_SWITCH_EN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define REGULATOR_SLAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int palmas_smps_read(struct palmas *palmas, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int *dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int palmas_smps_write(struct palmas *palmas, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) addr = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int palmas_ldo_read(struct palmas *palmas, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int *dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return regmap_read(palmas->regmap[REGULATOR_SLAVE], addr, dest);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static int palmas_ldo_write(struct palmas *palmas, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) addr = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return regmap_write(palmas->regmap[REGULATOR_SLAVE], addr, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int palmas_set_mode_smps(struct regulator_dev *dev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct palmas_pmic *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bool rail_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = palmas_smps_read(pmic->palmas, rinfo->ctrl_addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) reg &= ~PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (reg == SMPS_CTRL_MODE_OFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) rail_enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) reg |= SMPS_CTRL_MODE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) reg |= SMPS_CTRL_MODE_ECO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) reg |= SMPS_CTRL_MODE_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pmic->current_reg_mode[id] = reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (rail_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) palmas_smps_write(pmic->palmas, rinfo->ctrl_addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* Switch the enable value to ensure this is used for enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) pmic->desc[id].enable_val = pmic->current_reg_mode[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static unsigned int palmas_get_mode_smps(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct palmas_pmic *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) reg = pmic->current_reg_mode[id] & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case SMPS_CTRL_MODE_ON:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) case SMPS_CTRL_MODE_ECO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) case SMPS_CTRL_MODE_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int palmas_smps_set_ramp_delay(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct palmas_pmic *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned int reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* SMPS3 and SMPS7 do not have tstep_addr setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case PALMAS_REG_SMPS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) case PALMAS_REG_SMPS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (ramp_delay <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else if (ramp_delay <= 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) reg = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) else if (ramp_delay <= 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) reg = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) reg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ret = palmas_smps_write(pmic->palmas, rinfo->tstep_addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(pmic->palmas->dev, "TSTEP write failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pmic->ramp_delay[id] = palmas_smps_ramp_delay[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const struct regulator_ops palmas_ops_smps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .set_mode = palmas_set_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .get_mode = palmas_get_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .set_ramp_delay = palmas_smps_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static const struct regulator_ops palmas_ops_ext_control_smps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .set_mode = palmas_set_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .get_mode = palmas_get_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .set_ramp_delay = palmas_smps_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static const struct regulator_ops palmas_ops_smps10 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .set_bypass = regulator_set_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .get_bypass = regulator_get_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct regulator_ops tps65917_ops_smps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .set_mode = palmas_set_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .get_mode = palmas_get_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static const struct regulator_ops tps65917_ops_ext_control_smps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .set_mode = palmas_set_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .get_mode = palmas_get_mode_smps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int palmas_is_enabled_ldo(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) int id = rdev_get_id(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct palmas_pmic *pmic = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct palmas_pmic_driver_data *ddata = pmic->palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) palmas_ldo_read(pmic->palmas, rinfo->ctrl_addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reg &= PALMAS_LDO1_CTRL_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return !!(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const struct regulator_ops palmas_ops_ldo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .is_enabled = palmas_is_enabled_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const struct regulator_ops palmas_ops_ldo9 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .is_enabled = palmas_is_enabled_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .set_bypass = regulator_set_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .get_bypass = regulator_get_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static const struct regulator_ops palmas_ops_ext_control_ldo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static const struct regulator_ops palmas_ops_extreg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static const struct regulator_ops palmas_ops_ext_control_extreg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static const struct regulator_ops tps65917_ops_ldo = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .is_enabled = palmas_is_enabled_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static const struct regulator_ops tps65917_ops_ldo_1_2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .is_enabled = palmas_is_enabled_ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .set_bypass = regulator_set_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .get_bypass = regulator_get_bypass_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int palmas_regulator_config_external(struct palmas *palmas, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct palmas_reg_init *reg_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ret = palmas_ext_control_req_config(palmas, rinfo->sleep_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) reg_init->roof_floor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_err(palmas->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "Ext control config for regulator %d failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * setup the hardware based sleep configuration of the SMPS/LDO regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * from the platform data. This is different to the software based control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * supported by the regulator framework as it is controlled by toggling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * pins on the PMIC such as PREQ, SYSEN, ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int palmas_smps_init(struct palmas *palmas, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct palmas_reg_init *reg_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) unsigned int addr = rinfo->ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret = palmas_smps_read(palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case PALMAS_REG_SMPS10_OUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) case PALMAS_REG_SMPS10_OUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) reg &= ~PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (reg_init->mode_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) reg |= reg_init->mode_sleep <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (reg_init->warm_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) reg |= PALMAS_SMPS12_CTRL_WR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) reg &= ~PALMAS_SMPS12_CTRL_WR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) reg |= PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) reg &= ~PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) reg &= ~PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (reg_init->mode_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) reg |= reg_init->mode_sleep <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = palmas_smps_write(palmas, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (rinfo->vsel_addr && reg_init->vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) reg = reg_init->vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = palmas_smps_write(palmas, rinfo->vsel_addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (reg_init->roof_floor && (id != PALMAS_REG_SMPS10_OUT1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) (id != PALMAS_REG_SMPS10_OUT2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Enable externally controlled regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = palmas_smps_read(palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!(reg & PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) reg |= SMPS_CTRL_MODE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = palmas_smps_write(palmas, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return palmas_regulator_config_external(palmas, id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static int palmas_ldo_init(struct palmas *palmas, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct palmas_reg_init *reg_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) addr = rinfo->ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) ret = palmas_ldo_read(palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (reg_init->warm_reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) reg |= PALMAS_LDO1_CTRL_WR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) reg &= ~PALMAS_LDO1_CTRL_WR_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (reg_init->mode_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) reg |= PALMAS_LDO1_CTRL_MODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) reg &= ~PALMAS_LDO1_CTRL_MODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) ret = palmas_ldo_write(palmas, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (reg_init->roof_floor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Enable externally controlled regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = palmas_update_bits(palmas, PALMAS_LDO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) addr, PALMAS_LDO1_CTRL_MODE_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) PALMAS_LDO1_CTRL_MODE_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_err(palmas->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "LDO Register 0x%02x update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return palmas_regulator_config_external(palmas, id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int palmas_extreg_init(struct palmas *palmas, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct palmas_reg_init *reg_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct palmas_regs_info *rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) addr = rinfo->ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (reg_init->mode_sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val = PALMAS_REGEN1_CTRL_MODE_SLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) addr, PALMAS_REGEN1_CTRL_MODE_SLEEP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(palmas->dev, "Resource reg 0x%02x update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (reg_init->roof_floor) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Enable externally controlled regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = palmas_update_bits(palmas, PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) addr, PALMAS_REGEN1_CTRL_MODE_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) PALMAS_REGEN1_CTRL_MODE_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_err(palmas->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "Resource Register 0x%02x update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return palmas_regulator_config_external(palmas, id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) static void palmas_enable_ldo8_track(struct palmas *palmas)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) unsigned int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct palmas_pmic_driver_data *ddata = palmas->pmic_ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct palmas_regs_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) rinfo = &ddata->palmas_regs_info[PALMAS_REG_LDO8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) addr = rinfo->ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = palmas_ldo_read(palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev_err(palmas->dev, "Error in reading ldo8 control reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) reg |= PALMAS_LDO8_CTRL_LDO_TRACKING_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ret = palmas_ldo_write(palmas, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_err(palmas->dev, "Error in enabling tracking mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * When SMPS45 is set to off and LDO8 tracking is enabled, the LDO8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * output is defined by the LDO8_VOLTAGE.VSEL register divided by two,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * and can be set from 0.45 to 1.65 V.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) addr = rinfo->vsel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = palmas_ldo_read(palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_err(palmas->dev, "Error in reading ldo8 voltage reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) reg = (reg << 1) & PALMAS_LDO8_VOLTAGE_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = palmas_ldo_write(palmas, addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_err(palmas->dev, "Error in setting ldo8 voltage reg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int palmas_ldo_registration(struct palmas_pmic *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct palmas_pmic_driver_data *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct palmas_pmic_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) const char *pdev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct regulator_config config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct palmas_reg_init *reg_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct palmas_regs_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (pdata && pdata->reg_init[id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) reg_init = pdata->reg_init[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) reg_init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Miss out regulators which are not available due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * to alternate functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* Register the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) desc = &pmic->desc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) desc->name = rinfo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) desc->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) desc->type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (id < PALMAS_REG_REGEN1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (reg_init && reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) desc->ops = &palmas_ops_ext_control_ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) desc->ops = &palmas_ops_ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) desc->min_uV = 900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) desc->uV_step = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) desc->linear_min_sel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) desc->enable_time = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) rinfo->vsel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) rinfo->ctrl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Check if LDO8 is in tracking mode or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (pdata && (id == PALMAS_REG_LDO8) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) pdata->enable_ldo8_tracking) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) palmas_enable_ldo8_track(pmic->palmas);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) desc->min_uV = 450000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) desc->uV_step = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* LOD6 in vibrator mode will have enable time 2000us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (pdata && pdata->ldo6_vibrator &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) (id == PALMAS_REG_LDO6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) desc->enable_time = 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (id == PALMAS_REG_LDO9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) desc->ops = &palmas_ops_ldo9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) desc->bypass_reg = desc->enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) desc->bypass_val_on =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) desc->bypass_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) PALMAS_LDO9_CTRL_LDO_BYPASS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (!ddata->has_regen3 && id == PALMAS_REG_REGEN3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) desc->n_voltages = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (reg_init && reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) desc->ops = &palmas_ops_ext_control_extreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) desc->ops = &palmas_ops_extreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) desc->enable_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) rinfo->ctrl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) config.init_data = pdata->reg_data[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) config.init_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) desc->supply_name = rinfo->sname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) config.of_node = ddata->palmas_matches[id].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) rdev = devm_regulator_register(pmic->dev, desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev_err(pmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) pdev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) /* Initialise sleep/init values from platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) reg_init = pdata->reg_init[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (reg_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (id <= ddata->ldo_end)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = palmas_ldo_init(pmic->palmas, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ret = palmas_extreg_init(pmic->palmas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int tps65917_ldo_registration(struct palmas_pmic *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct palmas_pmic_driver_data *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct palmas_pmic_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) const char *pdev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) struct regulator_config config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct palmas_reg_init *reg_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct palmas_regs_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) for (id = ddata->ldo_begin; id < ddata->max_reg; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (pdata && pdata->reg_init[id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) reg_init = pdata->reg_init[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) reg_init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) /* Miss out regulators which are not available due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * to alternate functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* Register the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) desc = &pmic->desc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) desc->name = rinfo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) desc->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) desc->type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (id < TPS65917_REG_REGEN1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) desc->n_voltages = PALMAS_LDO_NUM_VOLTAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (reg_init && reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) desc->ops = &palmas_ops_ext_control_ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) desc->ops = &tps65917_ops_ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) desc->min_uV = 900000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) desc->uV_step = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) desc->linear_min_sel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) desc->enable_time = 500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) rinfo->vsel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) desc->vsel_mask = PALMAS_LDO1_VOLTAGE_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_LDO_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) rinfo->ctrl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) desc->enable_mask = PALMAS_LDO1_CTRL_MODE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * To be confirmed. Discussion on going with PMIC Team.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * It is of the order of ~60mV/uS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) desc->ramp_delay = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (id == TPS65917_REG_LDO1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) id == TPS65917_REG_LDO2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) desc->ops = &tps65917_ops_ldo_1_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) desc->bypass_reg = desc->enable_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) desc->bypass_val_on =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) TPS65917_LDO1_CTRL_BYPASS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) desc->bypass_mask =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) TPS65917_LDO1_CTRL_BYPASS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) desc->n_voltages = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (reg_init && reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) desc->ops = &palmas_ops_ext_control_extreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) desc->ops = &palmas_ops_extreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) desc->enable_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) PALMAS_BASE_TO_REG(PALMAS_RESOURCE_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) rinfo->ctrl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) desc->enable_mask = PALMAS_REGEN1_CTRL_MODE_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) config.init_data = pdata->reg_data[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) config.init_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) desc->supply_name = rinfo->sname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) config.of_node = ddata->palmas_matches[id].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) rdev = devm_regulator_register(pmic->dev, desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) dev_err(pmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) pdev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* Initialise sleep/init values from platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) reg_init = pdata->reg_init[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (reg_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (id < TPS65917_REG_REGEN1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = palmas_ldo_init(pmic->palmas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = palmas_extreg_init(pmic->palmas,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int palmas_smps_registration(struct palmas_pmic *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct palmas_pmic_driver_data *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct palmas_pmic_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) const char *pdev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct regulator_config config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) unsigned int addr, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct palmas_reg_init *reg_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct palmas_regs_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) bool ramp_delay_support = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * Miss out regulators which are not available due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * to slaving configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) case PALMAS_REG_SMPS12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case PALMAS_REG_SMPS3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (pmic->smps123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (id == PALMAS_REG_SMPS12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ramp_delay_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) case PALMAS_REG_SMPS123:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!pmic->smps123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ramp_delay_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case PALMAS_REG_SMPS45:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) case PALMAS_REG_SMPS7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (pmic->smps457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (id == PALMAS_REG_SMPS45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ramp_delay_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) case PALMAS_REG_SMPS457:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (!pmic->smps457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ramp_delay_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case PALMAS_REG_SMPS10_OUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) case PALMAS_REG_SMPS10_OUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (!PALMAS_PMIC_HAS(pmic->palmas, SMPS10_BOOST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) desc = &pmic->desc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ramp_delay_support = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ramp_delay_support) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) addr = rinfo->tstep_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret = palmas_smps_read(pmic->palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dev_err(pmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "reading TSTEP reg failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) desc->ramp_delay = palmas_smps_ramp_delay[reg & 0x3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pmic->ramp_delay[id] = desc->ramp_delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* Initialise sleep/init values from platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (pdata && pdata->reg_init[id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) reg_init = pdata->reg_init[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ret = palmas_smps_init(pmic->palmas, id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) reg_init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* Register the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) desc->name = rinfo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) desc->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) case PALMAS_REG_SMPS10_OUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) case PALMAS_REG_SMPS10_OUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) desc->n_voltages = PALMAS_SMPS10_NUM_VOLTAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) desc->ops = &palmas_ops_smps10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) PALMAS_SMPS10_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) desc->vsel_mask = SMPS10_VSEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) PALMAS_SMPS10_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (id == PALMAS_REG_SMPS10_OUT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) desc->enable_mask = SMPS10_SWITCH_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) desc->enable_mask = SMPS10_BOOST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) desc->bypass_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) PALMAS_SMPS10_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) desc->bypass_val_on = SMPS10_BYPASS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) desc->bypass_mask = SMPS10_BYPASS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) desc->min_uV = 3750000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) desc->uV_step = 1250000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * Read and store the RANGE bit for later use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * This must be done before regulator is probed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) * otherwise we error in probe with unsupportable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) * ranges. Read the current smps mode for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) addr = rinfo->vsel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) desc->n_linear_ranges = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = palmas_smps_read(pmic->palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (reg & PALMAS_SMPS12_VOLTAGE_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pmic->range[id] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (pmic->range[id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) desc->linear_ranges = smps_high_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) desc->linear_ranges = smps_low_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (reg_init && reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) desc->ops = &palmas_ops_ext_control_smps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) desc->ops = &palmas_ops_smps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) rinfo->vsel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) /* Read the smps mode for later use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) addr = rinfo->ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = palmas_smps_read(pmic->palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) pmic->current_reg_mode[id] = reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) rinfo->ctrl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* set_mode overrides this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) desc->enable_val = SMPS_CTRL_MODE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) desc->type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) config.init_data = pdata->reg_data[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) config.init_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) desc->supply_name = rinfo->sname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) config.of_node = ddata->palmas_matches[id].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) rdev = devm_regulator_register(pmic->dev, desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_err(pmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) pdev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int tps65917_smps_registration(struct palmas_pmic *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct palmas_pmic_driver_data *ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct palmas_pmic_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) const char *pdev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct regulator_config config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int id, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) unsigned int addr, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) struct palmas_reg_init *reg_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct palmas_regs_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) for (id = ddata->smps_start; id <= ddata->smps_end; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) * Miss out regulators which are not available due
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) * to slaving configurations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) desc = &pmic->desc[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) desc->n_linear_ranges = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if ((id == TPS65917_REG_SMPS2 || id == TPS65917_REG_SMPS1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) pmic->smps12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* Initialise sleep/init values from platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (pdata && pdata->reg_init[id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) reg_init = pdata->reg_init[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = palmas_smps_init(pmic->palmas, id, reg_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) reg_init = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) rinfo = &ddata->palmas_regs_info[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) /* Register the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) desc->name = rinfo->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) desc->id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * Read and store the RANGE bit for later use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * This must be done before regulator is probed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * otherwise we error in probe with unsupportable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * ranges. Read the current smps mode for later use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) addr = rinfo->vsel_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret = palmas_smps_read(pmic->palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (reg & TPS65917_SMPS1_VOLTAGE_RANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) pmic->range[id] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (pmic->range[id])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) desc->linear_ranges = smps_high_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) desc->linear_ranges = smps_low_ranges;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (reg_init && reg_init->roof_floor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) desc->ops = &tps65917_ops_ext_control_smps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) desc->ops = &tps65917_ops_smps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) desc->n_voltages = PALMAS_SMPS_NUM_VOLTAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) desc->vsel_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) rinfo->vsel_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) desc->vsel_mask = PALMAS_SMPS12_VOLTAGE_VSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) desc->ramp_delay = 2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* Read the smps mode for later use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) addr = rinfo->ctrl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret = palmas_smps_read(pmic->palmas, addr, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pmic->current_reg_mode[id] = reg &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) desc->enable_reg = PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) rinfo->ctrl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) desc->enable_mask = PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /* set_mode overrides this value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) desc->enable_val = SMPS_CTRL_MODE_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) desc->type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) desc->owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) config.init_data = pdata->reg_data[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) config.init_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) desc->supply_name = rinfo->sname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) config.of_node = ddata->palmas_matches[id].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) rdev = devm_regulator_register(pmic->dev, desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev_err(pmic->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pdev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static struct of_regulator_match palmas_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) { .name = "smps12", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) { .name = "smps123", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) { .name = "smps3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) { .name = "smps45", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) { .name = "smps457", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) { .name = "smps6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) { .name = "smps7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) { .name = "smps8", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) { .name = "smps9", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) { .name = "smps10_out2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) { .name = "smps10_out1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) { .name = "ldo1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) { .name = "ldo2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) { .name = "ldo3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) { .name = "ldo4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) { .name = "ldo5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) { .name = "ldo6", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) { .name = "ldo7", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) { .name = "ldo8", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) { .name = "ldo9", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) { .name = "ldoln", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) { .name = "ldousb", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) { .name = "regen1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) { .name = "regen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) { .name = "regen3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) { .name = "sysen1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) { .name = "sysen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static struct of_regulator_match tps65917_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) { .name = "smps1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) { .name = "smps2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) { .name = "smps3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) { .name = "smps4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) { .name = "smps5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) { .name = "smps12",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) { .name = "ldo1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) { .name = "ldo2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) { .name = "ldo3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) { .name = "ldo4", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) { .name = "ldo5", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) { .name = "regen1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) { .name = "regen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) { .name = "regen3", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) { .name = "sysen1", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) { .name = "sysen2", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) static struct palmas_pmic_driver_data palmas_ddata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .smps_start = PALMAS_REG_SMPS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .smps_end = PALMAS_REG_SMPS10_OUT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) .ldo_begin = PALMAS_REG_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) .ldo_end = PALMAS_REG_LDOUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .max_reg = PALMAS_NUM_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .has_regen3 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .palmas_regs_info = palmas_generic_regs_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .palmas_matches = palmas_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .sleep_req_info = palma_sleep_req_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .smps_register = palmas_smps_registration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .ldo_register = palmas_ldo_registration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) static struct palmas_pmic_driver_data tps65917_ddata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .smps_start = TPS65917_REG_SMPS1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) .smps_end = TPS65917_REG_SMPS12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) .ldo_begin = TPS65917_REG_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .ldo_end = TPS65917_REG_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .max_reg = TPS65917_NUM_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .has_regen3 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .palmas_regs_info = tps65917_regs_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .palmas_matches = tps65917_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .sleep_req_info = tps65917_sleep_req_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) .smps_register = tps65917_smps_registration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) .ldo_register = tps65917_ldo_registration,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static int palmas_dt_to_pdata(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct device_node *node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) struct palmas_pmic_platform_data *pdata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct palmas_pmic_driver_data *ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct device_node *regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) u32 prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) regulators = of_get_child_by_name(node, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (!regulators) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) dev_info(dev, "regulator node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ret = of_regulator_match(dev, regulators, ddata->palmas_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ddata->max_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) of_node_put(regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_err(dev, "Error parsing regulator init data: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) for (idx = 0; idx < ddata->max_reg; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct of_regulator_match *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) struct palmas_reg_init *rinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) match = &ddata->palmas_matches[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) np = match->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (!match->init_data || !np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) rinit = devm_kzalloc(dev, sizeof(*rinit), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (!rinit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) pdata->reg_data[idx] = match->init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pdata->reg_init[idx] = rinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) rinit->warm_reset = of_property_read_bool(np, "ti,warm-reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ret = of_property_read_u32(np, "ti,roof-floor", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* EINVAL: Property not found */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (ret != -EINVAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) int econtrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) /* use default value, when no value is specified */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) econtrol = PALMAS_EXT_CONTROL_NSLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) switch (prop) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) econtrol = PALMAS_EXT_CONTROL_ENABLE1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) econtrol = PALMAS_EXT_CONTROL_ENABLE2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) econtrol = PALMAS_EXT_CONTROL_NSLEEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dev_warn(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) "%s: Invalid roof-floor option: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) match->name, prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) rinit->roof_floor = econtrol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret = of_property_read_u32(np, "ti,mode-sleep", &prop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) rinit->mode_sleep = prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) ret = of_property_read_bool(np, "ti,smps-range");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) rinit->vsel = PALMAS_SMPS12_VOLTAGE_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (idx == PALMAS_REG_LDO8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) pdata->enable_ldo8_tracking = of_property_read_bool(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) np, "ti,enable-ldo8-tracking");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pdata->ldo6_vibrator = of_property_read_bool(node, "ti,ldo6-vibrator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static const struct of_device_id of_palmas_match_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .compatible = "ti,palmas-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .compatible = "ti,twl6035-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .compatible = "ti,twl6036-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .compatible = "ti,twl6037-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .compatible = "ti,tps65913-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .compatible = "ti,tps65914-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .compatible = "ti,tps80036-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .compatible = "ti,tps659038-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .data = &palmas_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .compatible = "ti,tps65917-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .data = &tps65917_ddata,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) { /* end */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) static int palmas_regulators_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct palmas *palmas = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) struct palmas_pmic_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) struct device_node *node = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct palmas_pmic_driver_data *driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) struct palmas_pmic *pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) const char *pdev_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) match = of_match_device(of_match_ptr(of_palmas_match_tbl), &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) driver_data = (struct palmas_pmic_driver_data *)match->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) pmic = devm_kzalloc(&pdev->dev, sizeof(*pmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (!pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (of_device_is_compatible(node, "ti,tps659038-pmic")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) palmas_generic_regs_info[PALMAS_REG_REGEN2].ctrl_addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) TPS659038_REGEN2_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) palmas_ddata.has_regen3 = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pmic->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) pmic->palmas = palmas;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) palmas->pmic = pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) platform_set_drvdata(pdev, pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) pmic->palmas->pmic_ddata = driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) ret = palmas_dt_to_pdata(&pdev->dev, node, pdata, driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ret = palmas_smps_read(palmas, PALMAS_SMPS_CTRL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (reg & PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) pmic->smps123 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) pmic->smps12 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (reg & PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) pmic->smps457 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) config.regmap = palmas->regmap[REGULATOR_SLAVE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) config.driver_data = pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) pdev_name = pdev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) ret = driver_data->smps_register(pmic, driver_data, pdata, pdev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = driver_data->ldo_register(pmic, driver_data, pdata, pdev_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static struct platform_driver palmas_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .name = "palmas-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .of_match_table = of_palmas_match_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .probe = palmas_regulators_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int __init palmas_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return platform_driver_register(&palmas_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) subsys_initcall(palmas_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static void __exit palmas_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) platform_driver_unregister(&palmas_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) module_exit(palmas_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) MODULE_DESCRIPTION("Palmas voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) MODULE_ALIAS("platform:palmas-pmic");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) MODULE_DEVICE_TABLE(of, of_palmas_match_tbl);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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