Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2014 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Flora Fu <flora.fu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/mt6397/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/mt6397-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <dt-bindings/regulator/mediatek,mt6397-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * MT6397 regulators' information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * @desc: standard fields of regulator description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * @qi: Mask for query enable signal status of regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * @vselon_reg: Register sections for hardware control mode of bucks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * @vselctrl_reg: Register for controlling the buck control mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * @vselctrl_mask: Mask for query buck's voltage control mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) struct mt6397_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32 qi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32 vselon_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 vselctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 vselctrl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 modeset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 modeset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 modeset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MT6397_BUCK(match, vreg, min, max, step, volt_ranges, enreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		vosel, vosel_mask, voselon, vosel_ctrl, _modeset_reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		_modeset_shift)					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) [MT6397_ID_##vreg] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.desc = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.name = #vreg,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.of_match = of_match_ptr(match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.ops = &mt6397_volt_range_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.id = MT6397_ID_##vreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.n_voltages = (max - min)/step + 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.linear_ranges = volt_ranges,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.n_linear_ranges = ARRAY_SIZE(volt_ranges),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.vsel_reg = vosel,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.vsel_mask = vosel_mask,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.enable_reg = enreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.enable_mask = BIT(0),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.of_map_mode = mt6397_map_mode,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.qi = BIT(13),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.vselon_reg = voselon,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.vselctrl_reg = vosel_ctrl,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.vselctrl_mask = BIT(1),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.modeset_reg = _modeset_reg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.modeset_mask = BIT(_modeset_shift),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.modeset_shift = _modeset_shift					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MT6397_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		vosel_mask)						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) [MT6397_ID_##vreg] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	.desc = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.name = #vreg,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.of_match = of_match_ptr(match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.ops = &mt6397_volt_table_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.id = MT6397_ID_##vreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.n_voltages = ARRAY_SIZE(ldo_volt_table),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.volt_table = ldo_volt_table,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.vsel_reg = vosel,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.vsel_mask = vosel_mask,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.enable_reg = enreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.enable_mask = BIT(enbit),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	.qi = BIT(15),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MT6397_REG_FIXED(match, vreg, enreg, enbit, volt)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) [MT6397_ID_##vreg] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.desc = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.name = #vreg,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.of_match = of_match_ptr(match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.ops = &mt6397_volt_fixed_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.id = MT6397_ID_##vreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.n_voltages = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.enable_reg = enreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.enable_mask = BIT(enbit),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		.min_uV = volt,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.qi = BIT(15),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const struct linear_range buck_volt_range1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const struct linear_range buck_volt_range2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	REGULATOR_LINEAR_RANGE(800000, 0, 0x7f, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct linear_range buck_volt_range3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	REGULATOR_LINEAR_RANGE(1500000, 0, 0x1f, 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const unsigned int ldo_volt_table1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	1500000, 1800000, 2500000, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const unsigned int ldo_volt_table2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	1800000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static const unsigned int ldo_volt_table3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) static const unsigned int ldo_volt_table4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	1220000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const unsigned int ldo_volt_table5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const unsigned int ldo_volt_table5_v2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	1200000, 1000000, 1500000, 1800000, 2500000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const unsigned int ldo_volt_table6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const unsigned int ldo_volt_table7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	1300000, 1500000, 1800000, 2000000, 2500000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static unsigned int mt6397_map_mode(unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	case MT6397_BUCK_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case MT6397_BUCK_MODE_FORCE_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return REGULATOR_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static int mt6397_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 				     unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	int ret, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		val = MT6397_BUCK_MODE_FORCE_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		val = MT6397_BUCK_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 		goto err_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	dev_dbg(&rdev->dev, "mt6397 buck set_mode %#x, %#x, %#x, %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		info->modeset_reg, info->modeset_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		info->modeset_shift, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	val <<= info->modeset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 				 info->modeset_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) err_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		dev_err(&rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 			"Failed to set mt6397 buck mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static unsigned int mt6397_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int ret, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		dev_err(&rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			"Failed to get mt6397 buck mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	switch ((regval & info->modeset_mask) >> info->modeset_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	case MT6397_BUCK_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	case MT6397_BUCK_MODE_FORCE_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int mt6397_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct mt6397_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct regulator_ops mt6397_volt_range_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	.get_status = mt6397_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	.set_mode = mt6397_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.get_mode = mt6397_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct regulator_ops mt6397_volt_table_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.map_voltage = regulator_map_voltage_iterate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	.get_status = mt6397_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static const struct regulator_ops mt6397_volt_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.get_status = mt6397_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* The array is indexed by id(MT6397_ID_XXX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct mt6397_regulator_info mt6397_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	MT6397_BUCK("buck_vpca15", VPCA15, 700000, 1493750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		buck_volt_range1, MT6397_VCA15_CON7, MT6397_VCA15_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		MT6397_VCA15_CON10, MT6397_VCA15_CON5, MT6397_VCA15_CON2, 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	MT6397_BUCK("buck_vpca7", VPCA7, 700000, 1493750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		buck_volt_range1, MT6397_VPCA7_CON7, MT6397_VPCA7_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		MT6397_VPCA7_CON10, MT6397_VPCA7_CON5, MT6397_VPCA7_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	MT6397_BUCK("buck_vsramca15", VSRAMCA15, 700000, 1493750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		buck_volt_range1, MT6397_VSRMCA15_CON7, MT6397_VSRMCA15_CON9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		0x7f, MT6397_VSRMCA15_CON10, MT6397_VSRMCA15_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		MT6397_VSRMCA15_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	MT6397_BUCK("buck_vsramca7", VSRAMCA7, 700000, 1493750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		buck_volt_range1, MT6397_VSRMCA7_CON7, MT6397_VSRMCA7_CON9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		0x7f, MT6397_VSRMCA7_CON10, MT6397_VSRMCA7_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		MT6397_VSRMCA7_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	MT6397_BUCK("buck_vcore", VCORE, 700000, 1493750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		buck_volt_range1, MT6397_VCORE_CON7, MT6397_VCORE_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		MT6397_VCORE_CON10, MT6397_VCORE_CON5, MT6397_VCORE_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	MT6397_BUCK("buck_vgpu", VGPU, 700000, 1493750, 6250, buck_volt_range1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		MT6397_VGPU_CON7, MT6397_VGPU_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		MT6397_VGPU_CON10, MT6397_VGPU_CON5, MT6397_VGPU_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	MT6397_BUCK("buck_vdrm", VDRM, 800000, 1593750, 6250, buck_volt_range2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		MT6397_VDRM_CON7, MT6397_VDRM_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		MT6397_VDRM_CON10, MT6397_VDRM_CON5, MT6397_VDRM_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	MT6397_BUCK("buck_vio18", VIO18, 1500000, 2120000, 20000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		buck_volt_range3, MT6397_VIO18_CON7, MT6397_VIO18_CON9, 0x1f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		MT6397_VIO18_CON10, MT6397_VIO18_CON5, MT6397_VIO18_CON2, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	MT6397_REG_FIXED("ldo_vtcxo", VTCXO, MT6397_ANALDO_CON0, 10, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	MT6397_REG_FIXED("ldo_va28", VA28, MT6397_ANALDO_CON1, 14, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	MT6397_LDO("ldo_vcama", VCAMA, ldo_volt_table1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		MT6397_ANALDO_CON2, 15, MT6397_ANALDO_CON6, 0xC0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	MT6397_REG_FIXED("ldo_vio28", VIO28, MT6397_DIGLDO_CON0, 14, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	MT6397_REG_FIXED("ldo_vusb", VUSB, MT6397_DIGLDO_CON1, 14, 3300000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	MT6397_LDO("ldo_vmc", VMC, ldo_volt_table2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		MT6397_DIGLDO_CON2, 12, MT6397_DIGLDO_CON29, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	MT6397_LDO("ldo_vmch", VMCH, ldo_volt_table3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		MT6397_DIGLDO_CON3, 14, MT6397_DIGLDO_CON17, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	MT6397_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		MT6397_DIGLDO_CON4, 14, MT6397_DIGLDO_CON18, 0x10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	MT6397_LDO("ldo_vgp1", VGP1, ldo_volt_table4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		MT6397_DIGLDO_CON5, 15, MT6397_DIGLDO_CON19, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	MT6397_LDO("ldo_vgp2", VGP2, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		MT6397_DIGLDO_CON6, 15, MT6397_DIGLDO_CON20, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	MT6397_LDO("ldo_vgp3", VGP3, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		MT6397_DIGLDO_CON7, 15, MT6397_DIGLDO_CON21, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	MT6397_LDO("ldo_vgp4", VGP4, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		MT6397_DIGLDO_CON8, 15, MT6397_DIGLDO_CON22, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	MT6397_LDO("ldo_vgp5", VGP5, ldo_volt_table6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		MT6397_DIGLDO_CON9, 15, MT6397_DIGLDO_CON23, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	MT6397_LDO("ldo_vgp6", VGP6, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		MT6397_DIGLDO_CON10, 15, MT6397_DIGLDO_CON33, 0xE0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	MT6397_LDO("ldo_vibr", VIBR, ldo_volt_table7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		MT6397_DIGLDO_CON24, 15, MT6397_DIGLDO_CON25, 0xE00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static int mt6397_set_buck_vosel_reg(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if (mt6397_regulators[i].vselctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 			if (regmap_read(mt6397->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 				mt6397_regulators[i].vselctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 				&regval) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 					"Failed to read buck ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 				return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			if (regval & mt6397_regulators[i].vselctrl_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				mt6397_regulators[i].desc.vsel_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 				mt6397_regulators[i].vselon_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static int mt6397_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	u32 reg_value, version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	/* Query buck controller to select activated voltage register part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	if (mt6397_set_buck_vosel_reg(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	/* Read PMIC chip revision to update constraints and voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (regmap_read(mt6397->regmap, MT6397_CID, &reg_value) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(&pdev->dev, "Failed to read Chip ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	version = (reg_value & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	switch (version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	case MT6397_REGULATOR_ID91:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		mt6397_regulators[MT6397_ID_VGP2].desc.volt_table =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		ldo_volt_table5_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	for (i = 0; i < MT6397_MAX_REGULATOR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		config.driver_data = &mt6397_regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 		config.regmap = mt6397->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 		rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 				&mt6397_regulators[i].desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			dev_err(&pdev->dev, "failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 				mt6397_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct platform_device_id mt6397_platform_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	{"mt6397-regulator", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) MODULE_DEVICE_TABLE(platform, mt6397_platform_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const struct of_device_id mt6397_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	{ .compatible = "mediatek,mt6397-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_DEVICE_TABLE(of, mt6397_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static struct platform_driver mt6397_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.name = "mt6397-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.of_match_table = of_match_ptr(mt6397_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.probe = mt6397_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	.id_table = mt6397_platform_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) module_platform_driver(mt6397_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MODULE_AUTHOR("Flora Fu <flora.fu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6397 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MODULE_LICENSE("GPL");