^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (c) 2017 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Author: Chenglin Xu <chenglin.xu@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regulator/mt6380-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* PMIC Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT6380_ALDO_CON_0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT6380_BTLDO_CON_0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT6380_COMP_CON_0 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT6380_CPUBUCK_CON_0 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT6380_CPUBUCK_CON_1 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT6380_CPUBUCK_CON_2 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT6380_DDRLDO_CON_0 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT6380_MLDO_CON_0 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT6380_PALDO_CON_0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT6380_PHYLDO_CON_0 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT6380_SIDO_CON_0 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT6380_SIDO_CON_1 0x002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT6380_SIDO_CON_2 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MT6380_SLDO_CON_0 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT6380_TLDO_CON_0 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT6380_STARTUP_CON_0 0x003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT6380_STARTUP_CON_1 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT6380_SMPS_TOP_CON_0 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT6380_SMPS_TOP_CON_1 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT6380_ANA_CTRL_0 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT6380_ANA_CTRL_1 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT6380_ANA_CTRL_2 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT6380_ANA_CTRL_3 0x005C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT6380_ANA_CTRL_4 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MT6380_SPK_CON9 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT6380_SPK_CON11 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT6380_SPK_CON12 0x006A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT6380_CLK_CTRL 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MT6380_PINMUX_CTRL 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT6380_IO_CTRL 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT6380_SLP_MODE_CTRL_0 0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT6380_SLP_MODE_CTRL_1 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT6380_SLP_MODE_CTRL_2 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT6380_SLP_MODE_CTRL_3 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT6380_SLP_MODE_CTRL_4 0x008C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT6380_SLP_MODE_CTRL_5 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT6380_SLP_MODE_CTRL_6 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT6380_SLP_MODE_CTRL_7 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MT6380_SLP_MODE_CTRL_8 0x009C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT6380_FCAL_CTRL_0 0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MT6380_FCAL_CTRL_1 0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT6380_LDO_CTRL_0 0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MT6380_LDO_CTRL_1 0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MT6380_LDO_CTRL_2 0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MT6380_LDO_CTRL_3 0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT6380_LDO_CTRL_4 0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT6380_DEBUG_CTRL_0 0x00BC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MT6380_EFU_CTRL_0 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MT6380_EFU_CTRL_1 0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MT6380_EFU_CTRL_2 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MT6380_EFU_CTRL_3 0x0203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MT6380_EFU_CTRL_4 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MT6380_EFU_CTRL_5 0x0205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MT6380_EFU_CTRL_6 0x0206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MT6380_EFU_CTRL_7 0x0207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MT6380_EFU_CTRL_8 0x0208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MT6380_REGULATOR_MODE_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MT6380_REGULATOR_MODE_FORCE_PWM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * mt6380 regulators' information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @desc: standard fields of regulator description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @vselon_reg: Register sections for hardware control mode of bucks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @modeset_reg: Register for controlling the buck/LDO control mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @modeset_mask: Mask for controlling the buck/LDO control mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct mt6380_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 vselon_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 modeset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 modeset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MT6380_BUCK(match, vreg, min, max, step, volt_ranges, enreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) vosel, vosel_mask, enbit, voselon, _modeset_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) _modeset_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) [MT6380_ID_##vreg] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .name = #vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .of_match = of_match_ptr(match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .ops = &mt6380_volt_range_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) .id = MT6380_ID_##vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .n_voltages = ((max) - (min)) / (step) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .linear_ranges = volt_ranges, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .n_linear_ranges = ARRAY_SIZE(volt_ranges), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .vsel_reg = vosel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .vsel_mask = vosel_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .enable_reg = enreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .enable_mask = BIT(enbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .vselon_reg = voselon, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .modeset_reg = _modeset_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .modeset_mask = _modeset_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MT6380_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) vosel_mask, _modeset_reg, _modeset_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) [MT6380_ID_##vreg] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .name = #vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .of_match = of_match_ptr(match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .ops = &mt6380_volt_table_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .id = MT6380_ID_##vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .n_voltages = ARRAY_SIZE(ldo_volt_table), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .volt_table = ldo_volt_table, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .vsel_reg = vosel, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .vsel_mask = vosel_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .enable_reg = enreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .enable_mask = BIT(enbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) .modeset_reg = _modeset_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .modeset_mask = _modeset_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MT6380_REG_FIXED(match, vreg, enreg, enbit, volt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) _modeset_reg, _modeset_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) [MT6380_ID_##vreg] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .name = #vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) .of_match = of_match_ptr(match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .ops = &mt6380_volt_fixed_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .id = MT6380_ID_##vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .enable_reg = enreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .enable_mask = BIT(enbit), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .min_uV = volt, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .modeset_reg = _modeset_reg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .modeset_mask = _modeset_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const struct linear_range buck_volt_range1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct linear_range buck_volt_range2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) REGULATOR_LINEAR_RANGE(600000, 0, 0xfe, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct linear_range buck_volt_range3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) REGULATOR_LINEAR_RANGE(1200000, 0, 0x3c, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const unsigned int ldo_volt_table1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 1400000, 1350000, 1300000, 1250000, 1200000, 1150000, 1100000, 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const unsigned int ldo_volt_table2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 2200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static const unsigned int ldo_volt_table3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 1240000, 1390000, 1540000, 1840000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned int ldo_volt_table4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 2200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static int mt6380_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int ret, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) val = MT6380_REGULATOR_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) val = MT6380_REGULATOR_MODE_FORCE_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) val <<= ffs(info->modeset_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) info->modeset_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static unsigned int mt6380_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct mt6380_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) val &= info->modeset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) val >>= ffs(info->modeset_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) case MT6380_REGULATOR_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) mode = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) case MT6380_REGULATOR_MODE_FORCE_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mode = REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static const struct regulator_ops mt6380_volt_range_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .set_mode = mt6380_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .get_mode = mt6380_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static const struct regulator_ops mt6380_volt_table_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .map_voltage = regulator_map_voltage_iterate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .set_mode = mt6380_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .get_mode = mt6380_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const struct regulator_ops mt6380_volt_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .set_mode = mt6380_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .get_mode = mt6380_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* The array is indexed by id(MT6380_ID_XXX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static struct mt6380_regulator_info mt6380_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MT6380_BUCK("buck-vcore1", VCPU, 600000, 1393750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) buck_volt_range1, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 0xfe, 3, MT6380_ANA_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MT6380_CPUBUCK_CON_0, 0x8000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MT6380_BUCK("buck-vcore", VCORE, 600000, 1393750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) buck_volt_range2, MT6380_ANA_CTRL_3, MT6380_ANA_CTRL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0xfe, 2, MT6380_ANA_CTRL_2, MT6380_SIDO_CON_0, 0x1000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MT6380_BUCK("buck-vrf", VRF, 1200000, 1575000, 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) buck_volt_range3, MT6380_ANA_CTRL_3, MT6380_SIDO_CON_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x78, 1, MT6380_SIDO_CON_0, MT6380_SIDO_CON_0, 0x8000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MT6380_LDO("ldo-vm", VMLDO, ldo_volt_table1, MT6380_LDO_CTRL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 1, MT6380_MLDO_CON_0, 0xE000, MT6380_ANA_CTRL_1, 0x4000000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MT6380_LDO("ldo-va", VALDO, ldo_volt_table2, MT6380_LDO_CTRL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 2, MT6380_ALDO_CON_0, 0x400, MT6380_ALDO_CON_0, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MT6380_REG_FIXED("ldo-vphy", VPHYLDO, MT6380_LDO_CTRL_0, 7, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MT6380_PHYLDO_CON_0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MT6380_LDO("ldo-vddr", VDDRLDO, ldo_volt_table3, MT6380_LDO_CTRL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 8, MT6380_DDRLDO_CON_0, 0x3000, MT6380_DDRLDO_CON_0, 0x80),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MT6380_LDO("ldo-vt", VTLDO, ldo_volt_table4, MT6380_LDO_CTRL_0, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MT6380_TLDO_CON_0, 0x400, MT6380_TLDO_CON_0, 0x20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mt6380_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct regmap *regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) for (i = 0; i < MT6380_MAX_REGULATOR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) config.driver_data = &mt6380_regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) config.regmap = regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) &mt6380_regulators[i].desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(&pdev->dev, "failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mt6380_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const struct platform_device_id mt6380_platform_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {"mt6380-regulator", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) MODULE_DEVICE_TABLE(platform, mt6380_platform_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct of_device_id mt6380_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { .compatible = "mediatek,mt6380-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MODULE_DEVICE_TABLE(of, mt6380_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct platform_driver mt6380_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .name = "mt6380-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .of_match_table = of_match_ptr(mt6380_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .probe = mt6380_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .id_table = mt6380_platform_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) module_platform_driver(mt6380_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MODULE_AUTHOR("Chenglin Xu <chenglin.xu@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6380 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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