^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Copyright (C) 2020 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Author: Gene Chen <gene_chen@richtek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) MT6360_REGULATOR_BUCK1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) MT6360_REGULATOR_BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) MT6360_REGULATOR_LDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) MT6360_REGULATOR_LDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) MT6360_REGULATOR_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) MT6360_REGULATOR_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) MT6360_REGULATOR_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) MT6360_REGULATOR_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MT6360_REGULATOR_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct mt6360_irq_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) irq_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct mt6360_regulator_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) const struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned int mode_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) unsigned int mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) unsigned int state_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) unsigned int state_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) const struct mt6360_irq_mapping *irq_tables;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) int irq_table_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct mt6360_regulator_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static irqreturn_t mt6360_pgb_event_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct regulator_dev *rdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regulator_notifier_call_chain(rdev, REGULATOR_EVENT_FAIL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static irqreturn_t mt6360_oc_event_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct regulator_dev *rdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regulator_notifier_call_chain(rdev, REGULATOR_EVENT_OVER_CURRENT, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static irqreturn_t mt6360_ov_event_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct regulator_dev *rdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regulator_notifier_call_chain(rdev, REGULATOR_EVENT_REGULATION_OUT, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static irqreturn_t mt6360_uv_event_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct regulator_dev *rdev = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regulator_notifier_call_chain(rdev, REGULATOR_EVENT_UNDER_VOLTAGE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const struct mt6360_irq_mapping buck1_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) { "buck1_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { "buck1_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { "buck1_ov_evt", mt6360_ov_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { "buck1_uv_evt", mt6360_uv_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct mt6360_irq_mapping buck2_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { "buck2_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) { "buck2_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) { "buck2_ov_evt", mt6360_ov_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) { "buck2_uv_evt", mt6360_uv_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static const struct mt6360_irq_mapping ldo6_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { "ldo6_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { "ldo6_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const struct mt6360_irq_mapping ldo7_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) { "ldo7_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { "ldo7_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct mt6360_irq_mapping ldo1_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { "ldo1_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { "ldo1_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct mt6360_irq_mapping ldo2_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { "ldo2_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { "ldo2_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const struct mt6360_irq_mapping ldo3_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { "ldo3_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) { "ldo3_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct mt6360_irq_mapping ldo5_irq_tbls[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { "ldo5_pgb_evt", mt6360_pgb_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { "ldo5_oc_evt", mt6360_oc_event_handler },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const struct linear_range buck_vout_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) REGULATOR_LINEAR_RANGE(300000, 0x00, 0xc7, 5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) REGULATOR_LINEAR_RANGE(1300000, 0xc8, 0xff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct linear_range ldo_vout_ranges1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) REGULATOR_LINEAR_RANGE(500000, 0x00, 0x09, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) REGULATOR_LINEAR_RANGE(600000, 0x0a, 0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) REGULATOR_LINEAR_RANGE(610000, 0x11, 0x19, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) REGULATOR_LINEAR_RANGE(700000, 0x1a, 0x20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) REGULATOR_LINEAR_RANGE(710000, 0x21, 0x29, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) REGULATOR_LINEAR_RANGE(800000, 0x2a, 0x30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) REGULATOR_LINEAR_RANGE(810000, 0x31, 0x39, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) REGULATOR_LINEAR_RANGE(900000, 0x3a, 0x40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) REGULATOR_LINEAR_RANGE(910000, 0x41, 0x49, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) REGULATOR_LINEAR_RANGE(1000000, 0x4a, 0x50, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) REGULATOR_LINEAR_RANGE(1010000, 0x51, 0x59, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) REGULATOR_LINEAR_RANGE(1100000, 0x5a, 0x60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) REGULATOR_LINEAR_RANGE(1110000, 0x61, 0x69, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) REGULATOR_LINEAR_RANGE(1200000, 0x6a, 0x70, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) REGULATOR_LINEAR_RANGE(1210000, 0x71, 0x79, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) REGULATOR_LINEAR_RANGE(1300000, 0x7a, 0x80, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) REGULATOR_LINEAR_RANGE(1310000, 0x81, 0x89, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) REGULATOR_LINEAR_RANGE(1400000, 0x8a, 0x90, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) REGULATOR_LINEAR_RANGE(1410000, 0x91, 0x99, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) REGULATOR_LINEAR_RANGE(1500000, 0x9a, 0xa0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) REGULATOR_LINEAR_RANGE(1510000, 0xa1, 0xa9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) REGULATOR_LINEAR_RANGE(1600000, 0xaa, 0xb0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) REGULATOR_LINEAR_RANGE(1610000, 0xb1, 0xb9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) REGULATOR_LINEAR_RANGE(1700000, 0xba, 0xc0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) REGULATOR_LINEAR_RANGE(1710000, 0xc1, 0xc9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) REGULATOR_LINEAR_RANGE(1800000, 0xca, 0xd0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) REGULATOR_LINEAR_RANGE(1810000, 0xd1, 0xd9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) REGULATOR_LINEAR_RANGE(1900000, 0xda, 0xe0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) REGULATOR_LINEAR_RANGE(1910000, 0xe1, 0xe9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) REGULATOR_LINEAR_RANGE(2000000, 0xea, 0xf0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) REGULATOR_LINEAR_RANGE(2010000, 0xf1, 0xf9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) REGULATOR_LINEAR_RANGE(2100000, 0xfa, 0xff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct linear_range ldo_vout_ranges2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) REGULATOR_LINEAR_RANGE(1200000, 0x00, 0x09, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) REGULATOR_LINEAR_RANGE(1300000, 0x0a, 0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) REGULATOR_LINEAR_RANGE(1310000, 0x11, 0x19, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) REGULATOR_LINEAR_RANGE(1400000, 0x1a, 0x1f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) REGULATOR_LINEAR_RANGE(1500000, 0x20, 0x29, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) REGULATOR_LINEAR_RANGE(1600000, 0x2a, 0x2f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) REGULATOR_LINEAR_RANGE(1700000, 0x30, 0x39, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) REGULATOR_LINEAR_RANGE(1800000, 0x3a, 0x40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) REGULATOR_LINEAR_RANGE(1810000, 0x41, 0x49, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) REGULATOR_LINEAR_RANGE(1900000, 0x4a, 0x4f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) REGULATOR_LINEAR_RANGE(2000000, 0x50, 0x59, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) REGULATOR_LINEAR_RANGE(2100000, 0x5a, 0x60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) REGULATOR_LINEAR_RANGE(2110000, 0x61, 0x69, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) REGULATOR_LINEAR_RANGE(2200000, 0x6a, 0x6f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) REGULATOR_LINEAR_RANGE(2500000, 0x70, 0x79, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) REGULATOR_LINEAR_RANGE(2600000, 0x7a, 0x7f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) REGULATOR_LINEAR_RANGE(2700000, 0x80, 0x89, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) REGULATOR_LINEAR_RANGE(2800000, 0x8a, 0x90, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) REGULATOR_LINEAR_RANGE(2810000, 0x91, 0x99, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) REGULATOR_LINEAR_RANGE(2900000, 0x9a, 0xa0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) REGULATOR_LINEAR_RANGE(2910000, 0xa1, 0xa9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) REGULATOR_LINEAR_RANGE(3000000, 0xaa, 0xb0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) REGULATOR_LINEAR_RANGE(3010000, 0xb1, 0xb9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) REGULATOR_LINEAR_RANGE(3100000, 0xba, 0xc0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) REGULATOR_LINEAR_RANGE(3110000, 0xc1, 0xc9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) REGULATOR_LINEAR_RANGE(3200000, 0xca, 0xcf, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) REGULATOR_LINEAR_RANGE(3300000, 0xd0, 0xd9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) REGULATOR_LINEAR_RANGE(3400000, 0xda, 0xe0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) REGULATOR_LINEAR_RANGE(3410000, 0xe1, 0xe9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) REGULATOR_LINEAR_RANGE(3500000, 0xea, 0xf0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) REGULATOR_LINEAR_RANGE(3510000, 0xf1, 0xf9, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) REGULATOR_LINEAR_RANGE(3600000, 0xfa, 0xff, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static const struct linear_range ldo_vout_ranges3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) REGULATOR_LINEAR_RANGE(2700000, 0x00, 0x09, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) REGULATOR_LINEAR_RANGE(2800000, 0x0a, 0x10, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) REGULATOR_LINEAR_RANGE(2810000, 0x11, 0x19, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) REGULATOR_LINEAR_RANGE(2900000, 0x1a, 0x20, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) REGULATOR_LINEAR_RANGE(2910000, 0x21, 0x29, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) REGULATOR_LINEAR_RANGE(3000000, 0x2a, 0x30, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) REGULATOR_LINEAR_RANGE(3010000, 0x31, 0x39, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) REGULATOR_LINEAR_RANGE(3100000, 0x3a, 0x40, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) REGULATOR_LINEAR_RANGE(3110000, 0x41, 0x49, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) REGULATOR_LINEAR_RANGE(3200000, 0x4a, 0x4f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) REGULATOR_LINEAR_RANGE(3300000, 0x50, 0x59, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) REGULATOR_LINEAR_RANGE(3400000, 0x5a, 0x60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) REGULATOR_LINEAR_RANGE(3410000, 0x61, 0x69, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) REGULATOR_LINEAR_RANGE(3500000, 0x6a, 0x70, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) REGULATOR_LINEAR_RANGE(3510000, 0x71, 0x79, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) REGULATOR_LINEAR_RANGE(3600000, 0x7a, 0x7f, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static int mt6360_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) const struct mt6360_regulator_desc *rdesc = (struct mt6360_regulator_desc *)rdev->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct regmap *regmap = rdev_get_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int shift = ffs(rdesc->mode_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) val = MT6360_OPMODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) val = MT6360_OPMODE_ULP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) val = MT6360_OPMODE_LP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = regmap_update_bits(regmap, rdesc->mode_reg, rdesc->mode_mask, val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(&rdev->dev, "%s: fail (%d)\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static unsigned int mt6360_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) const struct mt6360_regulator_desc *rdesc = (struct mt6360_regulator_desc *)rdev->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct regmap *regmap = rdev_get_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int shift = ffs(rdesc->mode_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = regmap_read(regmap, rdesc->mode_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) val &= rdesc->mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) val >>= shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case MT6360_OPMODE_LP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) case MT6360_OPMODE_ULP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) case MT6360_OPMODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int mt6360_regulator_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) const struct mt6360_regulator_desc *rdesc = (struct mt6360_regulator_desc *)rdev->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct regmap *regmap = rdev_get_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) ret = regmap_read(regmap, rdesc->state_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (val & rdesc->state_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return REGULATOR_STATUS_ON;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) return REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct regulator_ops mt6360_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .set_mode = mt6360_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .get_mode = mt6360_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .get_status = mt6360_regulator_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static unsigned int mt6360_regulator_of_map_mode(unsigned int hw_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) switch (hw_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) case MT6360_OPMODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case MT6360_OPMODE_LP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) case MT6360_OPMODE_ULP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return REGULATOR_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MT6360_REGULATOR_DESC(_name, _sname, ereg, emask, vreg, vmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mreg, mmask, streg, stmask, vranges, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) vcnts, offon_delay, irq_tbls) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .name = #_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .supply_name = #_sname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .id = MT6360_REGULATOR_##_name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .of_match = of_match_ptr(#_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .regulators_node = of_match_ptr("regulator"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .of_map_mode = mt6360_regulator_of_map_mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .ops = &mt6360_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .vsel_reg = vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .vsel_mask = vmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .enable_reg = ereg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .enable_mask = emask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .linear_ranges = vranges, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .n_linear_ranges = ARRAY_SIZE(vranges), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .n_voltages = vcnts, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .off_on_delay = offon_delay, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .mode_reg = mreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .mode_mask = mmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .state_reg = streg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .state_mask = stmask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .irq_tables = irq_tbls, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .irq_table_size = ARRAY_SIZE(irq_tbls), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct mt6360_regulator_desc mt6360_regulator_descs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) MT6360_REGULATOR_DESC(BUCK1, BUCK1_VIN, 0x117, 0x40, 0x110, 0xff, 0x117, 0x30, 0x117, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) buck_vout_ranges, 256, 0, buck1_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) MT6360_REGULATOR_DESC(BUCK2, BUCK2_VIN, 0x127, 0x40, 0x120, 0xff, 0x127, 0x30, 0x127, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) buck_vout_ranges, 256, 0, buck2_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) MT6360_REGULATOR_DESC(LDO6, LDO_VIN3, 0x137, 0x40, 0x13B, 0xff, 0x137, 0x30, 0x137, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ldo_vout_ranges1, 256, 0, ldo6_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MT6360_REGULATOR_DESC(LDO7, LDO_VIN3, 0x131, 0x40, 0x135, 0xff, 0x131, 0x30, 0x131, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ldo_vout_ranges1, 256, 0, ldo7_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) MT6360_REGULATOR_DESC(LDO1, LDO_VIN1, 0x217, 0x40, 0x21B, 0xff, 0x217, 0x30, 0x217, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ldo_vout_ranges2, 256, 0, ldo1_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) MT6360_REGULATOR_DESC(LDO2, LDO_VIN1, 0x211, 0x40, 0x215, 0xff, 0x211, 0x30, 0x211, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) ldo_vout_ranges2, 256, 0, ldo2_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) MT6360_REGULATOR_DESC(LDO3, LDO_VIN1, 0x205, 0x40, 0x209, 0xff, 0x205, 0x30, 0x205, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) ldo_vout_ranges2, 256, 100, ldo3_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MT6360_REGULATOR_DESC(LDO5, LDO_VIN2, 0x20B, 0x40, 0x20F, 0x7f, 0x20B, 0x30, 0x20B, 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ldo_vout_ranges3, 128, 100, ldo5_irq_tbls),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int mt6360_regulator_irq_register(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) const struct mt6360_irq_mapping *tbls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int tbl_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int i, irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (i = 0; i < tbl_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) const struct mt6360_irq_mapping *irq_desc = tbls + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) irq = platform_get_irq_byname(pdev, irq_desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) dev_err(&pdev->dev, "Fail to get %s irq\n", irq_desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, irq_desc->handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) irq_desc->name, rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dev_err(&pdev->dev, "Fail to request %s irq\n", irq_desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int mt6360_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct mt6360_regulator_data *mrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mrd = devm_kzalloc(&pdev->dev, sizeof(*mrd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!mrd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mrd->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mrd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!mrd->regmap) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_err(&pdev->dev, "Failed to get parent regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) config.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) config.driver_data = mrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) config.regmap = mrd->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) for (i = 0; i < ARRAY_SIZE(mt6360_regulator_descs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) const struct mt6360_regulator_desc *rdesc = mt6360_regulator_descs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) rdev = devm_regulator_register(&pdev->dev, &rdesc->desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) dev_err(&pdev->dev, "Failed to register %d regulator\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret = mt6360_regulator_irq_register(pdev, rdev, rdesc->irq_tables,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) rdesc->irq_table_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_err(&pdev->dev, "Failed to register %d regulator irqs\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct platform_device_id mt6360_regulator_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { "mt6360-regulator", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) MODULE_DEVICE_TABLE(platform, mt6360_regulator_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static struct platform_driver mt6360_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .name = "mt6360-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .probe = mt6360_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .id_table = mt6360_regulator_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) module_platform_driver(mt6360_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_AUTHOR("Gene Chen <gene_chen@richtek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_DESCRIPTION("MT6360 Regulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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