Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/mfd/mt6358/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/mt6358-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MT6358_BUCK_MODE_AUTO	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MT6358_BUCK_MODE_FORCE_PWM	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * MT6358 regulators' information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * @desc: standard fields of regulator description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * @qi: Mask for query enable signal status of regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct mt6358_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32 status_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32 qi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	const u32 *index_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	unsigned int n_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 vsel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 da_vsel_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 da_vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 da_vsel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 modeset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 modeset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u32 modeset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MT6358_BUCK(match, vreg, min, max, step,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	volt_ranges, vosel_mask, _da_vsel_reg, _da_vsel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	_da_vsel_shift, _modeset_reg, _modeset_shift)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) [MT6358_ID_##vreg] = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	.desc = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.name = #vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.of_match = of_match_ptr(match),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.ops = &mt6358_volt_range_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.type = REGULATOR_VOLTAGE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.id = MT6358_ID_##vreg,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.owner = THIS_MODULE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.n_voltages = ((max) - (min)) / (step) + 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.linear_ranges = volt_ranges,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.n_linear_ranges = ARRAY_SIZE(volt_ranges),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.vsel_reg = MT6358_BUCK_##vreg##_ELR0,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.vsel_mask = vosel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 		.enable_reg = MT6358_BUCK_##vreg##_CON0,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 		.enable_mask = BIT(0),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 		.of_map_mode = mt6358_map_mode,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	},	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.status_reg = MT6358_BUCK_##vreg##_DBG1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	.qi = BIT(0),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	.da_vsel_reg = _da_vsel_reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	.da_vsel_mask = _da_vsel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	.da_vsel_shift = _da_vsel_shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	.modeset_reg = _modeset_reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.modeset_mask = BIT(_modeset_shift),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	.modeset_shift = _modeset_shift	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MT6358_LDO(match, vreg, ldo_volt_table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	ldo_index_table, enreg, enbit, vosel,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	vosel_mask, vosel_shift)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) [MT6358_ID_##vreg] = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	.desc = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.name = #vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.of_match = of_match_ptr(match),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.ops = &mt6358_volt_table_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.type = REGULATOR_VOLTAGE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		.id = MT6358_ID_##vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		.owner = THIS_MODULE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		.n_voltages = ARRAY_SIZE(ldo_volt_table),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 		.volt_table = ldo_volt_table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		.vsel_reg = vosel,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		.vsel_mask = vosel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		.enable_reg = enreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		.enable_mask = BIT(enbit),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	},	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.status_reg = MT6358_LDO_##vreg##_CON1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	.qi = BIT(15),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	.index_table = ldo_index_table,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	.n_table = ARRAY_SIZE(ldo_index_table),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	.vsel_shift = vosel_shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define MT6358_LDO1(match, vreg, min, max, step,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	volt_ranges, _da_vsel_reg, _da_vsel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	_da_vsel_shift, vosel, vosel_mask)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) [MT6358_ID_##vreg] = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	.desc = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		.name = #vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 		.of_match = of_match_ptr(match),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		.ops = &mt6358_volt_range_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		.type = REGULATOR_VOLTAGE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		.id = MT6358_ID_##vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		.owner = THIS_MODULE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		.n_voltages = ((max) - (min)) / (step) + 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		.linear_ranges = volt_ranges,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		.n_linear_ranges = ARRAY_SIZE(volt_ranges),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		.vsel_reg = vosel,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		.vsel_mask = vosel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		.enable_reg = MT6358_LDO_##vreg##_CON0,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 		.enable_mask = BIT(0),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	},	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.da_vsel_reg = _da_vsel_reg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.da_vsel_mask = _da_vsel_mask,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.da_vsel_shift = _da_vsel_shift,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.status_reg = MT6358_LDO_##vreg##_DBG1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.qi = BIT(0),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MT6358_REG_FIXED(match, vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	enreg, enbit, volt)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) [MT6358_ID_##vreg] = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.desc = {	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		.name = #vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		.of_match = of_match_ptr(match),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		.ops = &mt6358_volt_fixed_ops,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		.type = REGULATOR_VOLTAGE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		.id = MT6358_ID_##vreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		.owner = THIS_MODULE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		.n_voltages = 1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		.enable_reg = enreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		.enable_mask = BIT(enbit),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		.min_uV = volt,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	},	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	.status_reg = MT6358_LDO_##vreg##_CON1,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	.qi = BIT(15),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct linear_range buck_volt_range1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct linear_range buck_volt_range2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	REGULATOR_LINEAR_RANGE(500000, 0, 0x7f, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct linear_range buck_volt_range3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct linear_range buck_volt_range4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	REGULATOR_LINEAR_RANGE(1000000, 0, 0x7f, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static const u32 vdram2_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	600000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const u32 vsim_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	1700000, 1800000, 2700000, 3000000, 3100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const u32 vibr_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	1200000, 1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	2000000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static const u32 vusb_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	3000000, 3100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const u32 vcamd_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	900000, 1000000, 1100000, 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const u32 vefuse_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	1700000, 1800000, 1900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const u32 vmch_vemc_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	2900000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const u32 vcama_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	1800000, 2500000, 2700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	2800000, 2900000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const u32 vcn33_bt_wifi_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	3300000, 3400000, 3500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const u32 vmc_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	1800000, 2900000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const u32 vldo28_voltages[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	2800000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static const u32 vdram2_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	0, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static const u32 vsim_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	3, 4, 8, 11, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const u32 vibr_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	0, 1, 2, 4, 5, 9, 11, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static const u32 vusb_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	3, 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const u32 vcamd_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	3, 4, 5, 6, 7, 9, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static const u32 vefuse_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	11, 12, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static const u32 vmch_vemc_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	2, 3, 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static const u32 vcama_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	0, 7, 9, 10, 11, 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const u32 vcn33_bt_wifi_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	1, 2, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const u32 vmc_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	4, 10, 11, 13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static const u32 vldo28_idx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	1, 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static unsigned int mt6358_map_mode(unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return mode == MT6358_BUCK_MODE_AUTO ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		REGULATOR_MODE_NORMAL : REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int mt6358_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				  unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	const u32 *pvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	pvol = info->index_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	idx = pvol[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	ret = regmap_update_bits(rdev->regmap, info->desc.vsel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				 info->desc.vsel_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 				 idx << info->vsel_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static int mt6358_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	int idx, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	u32 selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	const u32 *pvol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	ret = regmap_read(rdev->regmap, info->desc.vsel_reg, &selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		dev_info(&rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			 "Failed to get mt6358 %s vsel reg: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			 info->desc.name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	selector = (selector & info->desc.vsel_mask) >> info->vsel_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	pvol = info->index_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	for (idx = 0; idx < info->desc.n_voltages; idx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		if (pvol[idx] == selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 			return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mt6358_get_buck_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	int ret, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	ret = regmap_read(rdev->regmap, info->da_vsel_reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		dev_err(&rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			"Failed to get mt6358 Buck %s vsel reg: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			info->desc.name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	ret = (regval >> info->da_vsel_shift) & info->da_vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int mt6358_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = regmap_read(rdev->regmap, info->status_reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		dev_info(&rdev->dev, "Failed to get enable reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int mt6358_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 				     unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		val = MT6358_BUCK_MODE_FORCE_PWM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		val = MT6358_BUCK_MODE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	dev_dbg(&rdev->dev, "mt6358 buck set_mode %#x, %#x, %#x, %#x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		info->modeset_reg, info->modeset_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		info->modeset_shift, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	val <<= info->modeset_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	return regmap_update_bits(rdev->regmap, info->modeset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				  info->modeset_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static unsigned int mt6358_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	struct mt6358_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	int ret, regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		dev_err(&rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 			"Failed to get mt6358 buck mode: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	switch ((regval & info->modeset_mask) >> info->modeset_shift) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	case MT6358_BUCK_MODE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	case MT6358_BUCK_MODE_FORCE_PWM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static const struct regulator_ops mt6358_volt_range_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	.list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	.map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	.get_voltage_sel = mt6358_get_buck_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.get_status = mt6358_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.set_mode = mt6358_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.get_mode = mt6358_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static const struct regulator_ops mt6358_volt_table_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	.map_voltage = regulator_map_voltage_iterate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.set_voltage_sel = mt6358_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.get_voltage_sel = mt6358_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	.get_status = mt6358_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct regulator_ops mt6358_volt_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	.get_status = mt6358_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* The array is indexed by id(MT6358_ID_XXX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct mt6358_regulator_info mt6358_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	MT6358_BUCK("buck_vdram1", VDRAM1, 500000, 2087500, 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		    buck_volt_range2, 0x7f, MT6358_BUCK_VDRAM1_DBG0, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		    0, MT6358_VDRAM1_ANA_CON0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	MT6358_BUCK("buck_vcore", VCORE, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		    buck_volt_range1, 0x7f, MT6358_BUCK_VCORE_DBG0, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		    0, MT6358_VCORE_VGPU_ANA_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	MT6358_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		    buck_volt_range3, 0x3f, MT6358_BUCK_VPA_DBG0, 0x3f, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		    MT6358_VPA_ANA_CON0, 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	MT6358_BUCK("buck_vproc11", VPROC11, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		    buck_volt_range1, 0x7f, MT6358_BUCK_VPROC11_DBG0, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		    0, MT6358_VPROC_ANA_CON0, 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	MT6358_BUCK("buck_vproc12", VPROC12, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		    buck_volt_range1, 0x7f, MT6358_BUCK_VPROC12_DBG0, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		    0, MT6358_VPROC_ANA_CON0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	MT6358_BUCK("buck_vgpu", VGPU, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		    buck_volt_range1, 0x7f, MT6358_BUCK_VGPU_ELR0, 0x7f, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		    MT6358_VCORE_VGPU_ANA_CON0, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	MT6358_BUCK("buck_vs2", VS2, 500000, 2087500, 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		    buck_volt_range2, 0x7f, MT6358_BUCK_VS2_DBG0, 0x7f, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		    MT6358_VS2_ANA_CON0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	MT6358_BUCK("buck_vmodem", VMODEM, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		    buck_volt_range1, 0x7f, MT6358_BUCK_VMODEM_DBG0, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		    0, MT6358_VMODEM_ANA_CON0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	MT6358_BUCK("buck_vs1", VS1, 1000000, 2587500, 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		    buck_volt_range4, 0x7f, MT6358_BUCK_VS1_DBG0, 0x7f, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		    MT6358_VS1_ANA_CON0, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	MT6358_REG_FIXED("ldo_vrf12", VRF12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 			 MT6358_LDO_VRF12_CON0, 0, 1200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	MT6358_REG_FIXED("ldo_vio18", VIO18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 			 MT6358_LDO_VIO18_CON0, 0, 1800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	MT6358_REG_FIXED("ldo_vcamio", VCAMIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			 MT6358_LDO_VCAMIO_CON0, 0, 1800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	MT6358_REG_FIXED("ldo_vcn18", VCN18, MT6358_LDO_VCN18_CON0, 0, 1800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	MT6358_REG_FIXED("ldo_vfe28", VFE28, MT6358_LDO_VFE28_CON0, 0, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	MT6358_REG_FIXED("ldo_vcn28", VCN28, MT6358_LDO_VCN28_CON0, 0, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	MT6358_REG_FIXED("ldo_vxo22", VXO22, MT6358_LDO_VXO22_CON0, 0, 2200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	MT6358_REG_FIXED("ldo_vaux18", VAUX18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			 MT6358_LDO_VAUX18_CON0, 0, 1800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	MT6358_REG_FIXED("ldo_vbif28", VBIF28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 			 MT6358_LDO_VBIF28_CON0, 0, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	MT6358_REG_FIXED("ldo_vio28", VIO28, MT6358_LDO_VIO28_CON0, 0, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	MT6358_REG_FIXED("ldo_va12", VA12, MT6358_LDO_VA12_CON0, 0, 1200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 	MT6358_REG_FIXED("ldo_vrf18", VRF18, MT6358_LDO_VRF18_CON0, 0, 1800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	MT6358_REG_FIXED("ldo_vaud28", VAUD28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			 MT6358_LDO_VAUD28_CON0, 0, 2800000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	MT6358_LDO("ldo_vdram2", VDRAM2, vdram2_voltages, vdram2_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		   MT6358_LDO_VDRAM2_CON0, 0, MT6358_LDO_VDRAM2_ELR0, 0xf, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	MT6358_LDO("ldo_vsim1", VSIM1, vsim_voltages, vsim_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		   MT6358_LDO_VSIM1_CON0, 0, MT6358_VSIM1_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	MT6358_LDO("ldo_vibr", VIBR, vibr_voltages, vibr_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		   MT6358_LDO_VIBR_CON0, 0, MT6358_VIBR_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	MT6358_LDO("ldo_vusb", VUSB, vusb_voltages, vusb_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		   MT6358_LDO_VUSB_CON0_0, 0, MT6358_VUSB_ANA_CON0, 0x700, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	MT6358_LDO("ldo_vcamd", VCAMD, vcamd_voltages, vcamd_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 		   MT6358_LDO_VCAMD_CON0, 0, MT6358_VCAMD_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	MT6358_LDO("ldo_vefuse", VEFUSE, vefuse_voltages, vefuse_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		   MT6358_LDO_VEFUSE_CON0, 0, MT6358_VEFUSE_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	MT6358_LDO("ldo_vmch", VMCH, vmch_vemc_voltages, vmch_vemc_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 		   MT6358_LDO_VMCH_CON0, 0, MT6358_VMCH_ANA_CON0, 0x700, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	MT6358_LDO("ldo_vcama1", VCAMA1, vcama_voltages, vcama_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		   MT6358_LDO_VCAMA1_CON0, 0, MT6358_VCAMA1_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	MT6358_LDO("ldo_vemc", VEMC, vmch_vemc_voltages, vmch_vemc_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		   MT6358_LDO_VEMC_CON0, 0, MT6358_VEMC_ANA_CON0, 0x700, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	MT6358_LDO("ldo_vcn33_bt", VCN33_BT, vcn33_bt_wifi_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		   vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		   0, MT6358_VCN33_ANA_CON0, 0x300, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	MT6358_LDO("ldo_vcn33_wifi", VCN33_WIFI, vcn33_bt_wifi_voltages,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		   vcn33_bt_wifi_idx, MT6358_LDO_VCN33_CON0_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		   0, MT6358_VCN33_ANA_CON0, 0x300, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	MT6358_LDO("ldo_vcama2", VCAMA2, vcama_voltages, vcama_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		   MT6358_LDO_VCAMA2_CON0, 0, MT6358_VCAMA2_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	MT6358_LDO("ldo_vmc", VMC, vmc_voltages, vmc_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		   MT6358_LDO_VMC_CON0, 0, MT6358_VMC_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	MT6358_LDO("ldo_vldo28", VLDO28, vldo28_voltages, vldo28_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		   MT6358_LDO_VLDO28_CON0_0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		   MT6358_VLDO28_ANA_CON0, 0x300, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	MT6358_LDO("ldo_vsim2", VSIM2, vsim_voltages, vsim_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		   MT6358_LDO_VSIM2_CON0, 0, MT6358_VSIM2_ANA_CON0, 0xf00, 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	MT6358_LDO1("ldo_vsram_proc11", VSRAM_PROC11, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 		    buck_volt_range1, MT6358_LDO_VSRAM_PROC11_DBG0, 0x7f, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 		    MT6358_LDO_VSRAM_CON0, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	MT6358_LDO1("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 		    buck_volt_range1, MT6358_LDO_VSRAM_OTHERS_DBG0, 0x7f, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		    MT6358_LDO_VSRAM_CON2, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	MT6358_LDO1("ldo_vsram_gpu", VSRAM_GPU, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 		    buck_volt_range1, MT6358_LDO_VSRAM_GPU_DBG0, 0x7f, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 		    MT6358_LDO_VSRAM_CON3, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	MT6358_LDO1("ldo_vsram_proc12", VSRAM_PROC12, 500000, 1293750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 		    buck_volt_range1, MT6358_LDO_VSRAM_PROC12_DBG0, 0x7f, 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		    MT6358_LDO_VSRAM_CON1, 0x7f),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static int mt6358_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	for (i = 0; i < MT6358_MAX_REGULATOR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 		config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 		config.driver_data = &mt6358_regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 		config.regmap = mt6397->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 					       &mt6358_regulators[i].desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 					       &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 			dev_err(&pdev->dev, "failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 				mt6358_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static const struct platform_device_id mt6358_platform_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	{"mt6358-regulator", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MODULE_DEVICE_TABLE(platform, mt6358_platform_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct platform_driver mt6358_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 		.name = "mt6358-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	.probe = mt6358_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	.id_table = mt6358_platform_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) module_platform_driver(mt6358_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6358 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_LICENSE("GPL");