Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) // Author: Chen Zhong <chen.zhong@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/mfd/mt6397/core.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/mfd/mt6323/registers.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/mt6323-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MT6323_LDO_MODE_NORMAL	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MT6323_LDO_MODE_LP	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  * MT6323 regulators' information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * @desc: standard fields of regulator description.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * @qi: Mask for query enable signal status of regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * @vselon_reg: Register sections for hardware control mode of bucks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * @vselctrl_reg: Register for controlling the buck control mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * @vselctrl_mask: Mask for query buck's voltage control mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) struct mt6323_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	u32 qi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32 vselon_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	u32 vselctrl_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 	u32 vselctrl_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u32 modeset_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u32 modeset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MT6323_BUCK(match, vreg, min, max, step, volt_ranges, enreg,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		vosel, vosel_mask, voselon, vosel_ctrl)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) [MT6323_ID_##vreg] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	.desc = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 		.name = #vreg,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 		.of_match = of_match_ptr(match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 		.ops = &mt6323_volt_range_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 		.id = MT6323_ID_##vreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 		.n_voltages = (max - min)/step + 1,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 		.linear_ranges = volt_ranges,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 		.n_linear_ranges = ARRAY_SIZE(volt_ranges),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 		.vsel_reg = vosel,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 		.vsel_mask = vosel_mask,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 		.enable_reg = enreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 		.enable_mask = BIT(0),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	.qi = BIT(13),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	.vselon_reg = voselon,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	.vselctrl_reg = vosel_ctrl,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	.vselctrl_mask = BIT(1),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MT6323_LDO(match, vreg, ldo_volt_table, enreg, enbit, vosel,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 		vosel_mask, _modeset_reg, _modeset_mask)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) [MT6323_ID_##vreg] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	.desc = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 		.name = #vreg,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 		.of_match = of_match_ptr(match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 		.ops = &mt6323_volt_table_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 		.id = MT6323_ID_##vreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		.n_voltages = ARRAY_SIZE(ldo_volt_table),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		.volt_table = ldo_volt_table,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		.vsel_reg = vosel,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		.vsel_mask = vosel_mask,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		.enable_reg = enreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		.enable_mask = BIT(enbit),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	.qi = BIT(15),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	.modeset_reg = _modeset_reg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	.modeset_mask = _modeset_mask,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define MT6323_REG_FIXED(match, vreg, enreg, enbit, volt,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		_modeset_reg, _modeset_mask)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) [MT6323_ID_##vreg] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	.desc = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		.name = #vreg,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		.of_match = of_match_ptr(match),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		.ops = &mt6323_volt_fixed_ops,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		.id = MT6323_ID_##vreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		.n_voltages = 1,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		.enable_reg = enreg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		.enable_mask = BIT(enbit),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		.min_uV = volt,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	},								\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	.qi = BIT(15),							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	.modeset_reg = _modeset_reg,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	.modeset_mask = _modeset_mask,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const struct linear_range buck_volt_range1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	REGULATOR_LINEAR_RANGE(700000, 0, 0x7f, 6250),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static const struct linear_range buck_volt_range2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	REGULATOR_LINEAR_RANGE(1400000, 0, 0x7f, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static const struct linear_range buck_volt_range3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	REGULATOR_LINEAR_RANGE(500000, 0, 0x3f, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static const unsigned int ldo_volt_table1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	3300000, 3400000, 3500000, 3600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const unsigned int ldo_volt_table2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	1500000, 1800000, 2500000, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const unsigned int ldo_volt_table3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	1800000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const unsigned int ldo_volt_table4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static const unsigned int ldo_volt_table5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	1200000, 1300000, 1500000, 1800000, 2000000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const unsigned int ldo_volt_table6[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	1200000, 1300000, 1500000, 1800000, 2500000, 2800000, 3000000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const unsigned int ldo_volt_table7[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	1200000, 1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const unsigned int ldo_volt_table8[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	1800000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const unsigned int ldo_volt_table9[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	1200000, 1350000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const unsigned int ldo_volt_table10[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	1200000, 1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static int mt6323_get_status(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	ret = regmap_read(rdev->regmap, info->desc.enable_reg, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if (ret != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return (regval & info->qi) ? REGULATOR_STATUS_ON : REGULATOR_STATUS_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int mt6323_ldo_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret, val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (!info->modeset_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		dev_err(&rdev->dev, "regulator %s doesn't support set_mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 			info->desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		val = MT6323_LDO_MODE_LP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		val = MT6323_LDO_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	val <<= ffs(info->modeset_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	ret = regmap_update_bits(rdev->regmap, info->modeset_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 				  info->modeset_mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static unsigned int mt6323_ldo_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct mt6323_regulator_info *info = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	if (!info->modeset_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		dev_err(&rdev->dev, "regulator %s doesn't support get_mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			info->desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	ret = regmap_read(rdev->regmap, info->modeset_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	val &= info->modeset_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	val >>= ffs(info->modeset_mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	if (val & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		mode = REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		mode = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static const struct regulator_ops mt6323_volt_range_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	.map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.get_status = mt6323_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct regulator_ops mt6323_volt_table_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.map_voltage = regulator_map_voltage_iterate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	.get_status = mt6323_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	.set_mode = mt6323_ldo_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	.get_mode = mt6323_ldo_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static const struct regulator_ops mt6323_volt_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.get_status = mt6323_get_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.set_mode = mt6323_ldo_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.get_mode = mt6323_ldo_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* The array is indexed by id(MT6323_ID_XXX) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static struct mt6323_regulator_info mt6323_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	MT6323_BUCK("buck_vproc", VPROC, 700000, 1493750, 6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		buck_volt_range1, MT6323_VPROC_CON7, MT6323_VPROC_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		MT6323_VPROC_CON10, MT6323_VPROC_CON5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	MT6323_BUCK("buck_vsys", VSYS, 1400000, 2987500, 12500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		buck_volt_range2, MT6323_VSYS_CON7, MT6323_VSYS_CON9, 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		MT6323_VSYS_CON10, MT6323_VSYS_CON5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	MT6323_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		buck_volt_range3, MT6323_VPA_CON7, MT6323_VPA_CON9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		0x3f, MT6323_VPA_CON10, MT6323_VPA_CON5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	MT6323_REG_FIXED("ldo_vtcxo", VTCXO, MT6323_ANALDO_CON1, 10, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		MT6323_ANALDO_CON1, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	MT6323_REG_FIXED("ldo_vcn28", VCN28, MT6323_ANALDO_CON19, 12, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		MT6323_ANALDO_CON20, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	MT6323_LDO("ldo_vcn33_bt", VCN33_BT, ldo_volt_table1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		MT6323_ANALDO_CON16, 7, MT6323_ANALDO_CON16, 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		MT6323_ANALDO_CON21, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	MT6323_LDO("ldo_vcn33_wifi", VCN33_WIFI, ldo_volt_table1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		MT6323_ANALDO_CON17, 12, MT6323_ANALDO_CON16, 0xC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		MT6323_ANALDO_CON21, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	MT6323_REG_FIXED("ldo_va", VA, MT6323_ANALDO_CON2, 14, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		MT6323_ANALDO_CON2, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	MT6323_LDO("ldo_vcama", VCAMA, ldo_volt_table2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		MT6323_ANALDO_CON4, 15, MT6323_ANALDO_CON10, 0x60, -1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	MT6323_REG_FIXED("ldo_vio28", VIO28, MT6323_DIGLDO_CON0, 14, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		MT6323_DIGLDO_CON0, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	MT6323_REG_FIXED("ldo_vusb", VUSB, MT6323_DIGLDO_CON2, 14, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		MT6323_DIGLDO_CON2, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	MT6323_LDO("ldo_vmc", VMC, ldo_volt_table3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		MT6323_DIGLDO_CON3, 12, MT6323_DIGLDO_CON24, 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		MT6323_DIGLDO_CON3, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	MT6323_LDO("ldo_vmch", VMCH, ldo_volt_table4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		MT6323_DIGLDO_CON5, 14, MT6323_DIGLDO_CON26, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		MT6323_DIGLDO_CON5, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	MT6323_LDO("ldo_vemc3v3", VEMC3V3, ldo_volt_table4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		MT6323_DIGLDO_CON6, 14, MT6323_DIGLDO_CON27, 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		MT6323_DIGLDO_CON6, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	MT6323_LDO("ldo_vgp1", VGP1, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		MT6323_DIGLDO_CON7, 15, MT6323_DIGLDO_CON28, 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		MT6323_DIGLDO_CON7, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	MT6323_LDO("ldo_vgp2", VGP2, ldo_volt_table6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		MT6323_DIGLDO_CON8, 15, MT6323_DIGLDO_CON29, 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		MT6323_DIGLDO_CON8, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	MT6323_LDO("ldo_vgp3", VGP3, ldo_volt_table7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		MT6323_DIGLDO_CON9, 15, MT6323_DIGLDO_CON30, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		MT6323_DIGLDO_CON9, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	MT6323_REG_FIXED("ldo_vcn18", VCN18, MT6323_DIGLDO_CON11, 14, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		MT6323_DIGLDO_CON11, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	MT6323_LDO("ldo_vsim1", VSIM1, ldo_volt_table8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		MT6323_DIGLDO_CON13, 15, MT6323_DIGLDO_CON34, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		MT6323_DIGLDO_CON13, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	MT6323_LDO("ldo_vsim2", VSIM2, ldo_volt_table8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		MT6323_DIGLDO_CON14, 15, MT6323_DIGLDO_CON35, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		MT6323_DIGLDO_CON14, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	MT6323_REG_FIXED("ldo_vrtc", VRTC, MT6323_DIGLDO_CON15, 8, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		-1, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	MT6323_LDO("ldo_vcamaf", VCAMAF, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		MT6323_DIGLDO_CON31, 15, MT6323_DIGLDO_CON32, 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		MT6323_DIGLDO_CON31, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	MT6323_LDO("ldo_vibr", VIBR, ldo_volt_table5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		MT6323_DIGLDO_CON39, 15, MT6323_DIGLDO_CON40, 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		MT6323_DIGLDO_CON39, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	MT6323_REG_FIXED("ldo_vrf18", VRF18, MT6323_DIGLDO_CON45, 15, 1825000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		MT6323_DIGLDO_CON45, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	MT6323_LDO("ldo_vm", VM, ldo_volt_table9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		MT6323_DIGLDO_CON47, 14, MT6323_DIGLDO_CON48, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		MT6323_DIGLDO_CON47, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	MT6323_REG_FIXED("ldo_vio18", VIO18, MT6323_DIGLDO_CON49, 14, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		MT6323_DIGLDO_CON49, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	MT6323_LDO("ldo_vcamd", VCAMD, ldo_volt_table10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		MT6323_DIGLDO_CON51, 14, MT6323_DIGLDO_CON52, 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		MT6323_DIGLDO_CON51, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	MT6323_REG_FIXED("ldo_vcamio", VCAMIO, MT6323_DIGLDO_CON53, 14, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		MT6323_DIGLDO_CON53, 0x2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int mt6323_set_buck_vosel_reg(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	struct mt6397_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	u32 regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (mt6323_regulators[i].vselctrl_reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			if (regmap_read(mt6323->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 				mt6323_regulators[i].vselctrl_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 				&regval) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 				dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 					"Failed to read buck ctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 				return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			if (regval & mt6323_regulators[i].vselctrl_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 				mt6323_regulators[i].desc.vsel_reg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 				mt6323_regulators[i].vselon_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int mt6323_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	struct mt6397_chip *mt6323 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	struct regulator_config config = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	/* Query buck controller to select activated voltage register part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (mt6323_set_buck_vosel_reg(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	/* Read PMIC chip revision to update constraints and voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	if (regmap_read(mt6323->regmap, MT6323_CID, &reg_value) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		dev_err(&pdev->dev, "Failed to read Chip ID\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	dev_info(&pdev->dev, "Chip ID = 0x%x\n", reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	for (i = 0; i < MT6323_MAX_REGULATOR; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		config.driver_data = &mt6323_regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		config.regmap = mt6323->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 				&mt6323_regulators[i].desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 			dev_err(&pdev->dev, "failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 				mt6323_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static const struct platform_device_id mt6323_platform_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	{"mt6323-regulator", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	{ /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) MODULE_DEVICE_TABLE(platform, mt6323_platform_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static struct platform_driver mt6323_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.name = "mt6323-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	.probe = mt6323_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	.id_table = mt6323_platform_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) module_platform_driver(mt6323_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MODULE_AUTHOR("Chen Zhong <chen.zhong@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6323 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) MODULE_LICENSE("GPL v2");