Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2015 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Henry Chen <henryc.chen@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef __MT6311_REGULATOR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define __MT6311_REGULATOR_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MT6311_SWCID              0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT6311_TOP_INT_CON        0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MT6311_TOP_INT_MON        0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MT6311_VDVFS11_CON0       0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MT6311_VDVFS11_CON7       0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MT6311_VDVFS11_CON8       0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MT6311_VDVFS11_CON9       0x8A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MT6311_VDVFS11_CON10      0x8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MT6311_VDVFS11_CON11      0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MT6311_VDVFS11_CON12      0x8D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MT6311_VDVFS11_CON13      0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MT6311_VDVFS11_CON14      0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MT6311_VDVFS11_CON15      0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MT6311_VDVFS11_CON16      0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MT6311_VDVFS11_CON17      0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MT6311_VDVFS11_CON18      0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MT6311_VDVFS11_CON19      0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MT6311_LDO_CON0           0xCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MT6311_LDO_OCFB0          0xCD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT6311_LDO_CON2           0xCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MT6311_LDO_CON3           0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MT6311_LDO_CON4           0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MT6311_FQMTR_CON0         0xD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MT6311_FQMTR_CON1         0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MT6311_FQMTR_CON2         0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MT6311_FQMTR_CON3         0xD4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MT6311_FQMTR_CON4         0xD5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MT6311_PMIC_RG_INT_POL_MASK                      0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MT6311_PMIC_RG_INT_EN_MASK                       0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MT6311_PMIC_RG_BUCK_OC_INT_STATUS_MASK           0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MT6311_PMIC_VDVFS11_EN_CTRL_MASK                 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT6311_PMIC_VDVFS11_VOSEL_CTRL_MASK              0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT6311_PMIC_VDVFS11_EN_SEL_MASK                  0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT6311_PMIC_VDVFS11_VOSEL_SEL_MASK               0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT6311_PMIC_VDVFS11_EN_MASK                      0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT6311_PMIC_VDVFS11_VOSEL_MASK                   0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT6311_PMIC_VDVFS11_VOSEL_ON_MASK                0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MT6311_PMIC_VDVFS11_VOSEL_SLEEP_MASK             0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT6311_PMIC_NI_VDVFS11_VOSEL_MASK                0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT6311_PMIC_RG_VBIASN_EN_MASK                    0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif