Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * mpq7920.h  -  Regulator definitions for mpq7920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright 2019 Monolithic Power Systems, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef __MPQ7920_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __MPQ7920_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MPQ7920_REG_CTL0		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MPQ7920_REG_CTL1		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MPQ7920_REG_CTL2		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define MPQ7920_BUCK1_REG_A		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MPQ7920_BUCK1_REG_B		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MPQ7920_BUCK1_REG_C		0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MPQ7920_BUCK1_REG_D		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MPQ7920_BUCK2_REG_A		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MPQ7920_BUCK2_REG_B		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MPQ7920_BUCK2_REG_C		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPQ7920_BUCK2_REG_D		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MPQ7920_BUCK3_REG_A		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MPQ7920_BUCK3_REG_B		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MPQ7920_BUCK3_REG_C		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPQ7920_BUCK3_REG_D		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MPQ7920_BUCK4_REG_A		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MPQ7920_BUCK4_REG_B		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MPQ7920_BUCK4_REG_C		0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MPQ7920_BUCK4_REG_D		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MPQ7920_LDO1_REG_A		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MPQ7920_LDO1_REG_B		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MPQ7920_LDO2_REG_A		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MPQ7920_LDO2_REG_B		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MPQ7920_LDO2_REG_C		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MPQ7920_LDO3_REG_A		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MPQ7920_LDO3_REG_B		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MPQ7920_LDO3_REG_C		0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MPQ7920_LDO4_REG_A		0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MPQ7920_LDO4_REG_B		0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MPQ7920_LDO4_REG_C		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MPQ7920_LDO5_REG_A		0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MPQ7920_LDO5_REG_B		0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MPQ7920_LDO5_REG_C		0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MPQ7920_REG_MODE		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MPQ7920_REG_REGULATOR_EN	0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MPQ7920_MASK_VREF		0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MPQ7920_MASK_BUCK_ILIM		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MPQ7920_MASK_LDO_ILIM		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MPQ7920_MASK_DISCHARGE		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MPQ7920_MASK_MODE		0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MPQ7920_MASK_SOFTSTART		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MPQ7920_MASK_SWITCH_FREQ	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MPQ7920_MASK_BUCK_PHASE_DEALY	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MPQ7920_MASK_DVS_SLEWRATE	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MPQ7920_MASK_OVP		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MPQ7920_OVP_DISABLE		~(0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MPQ7920_DISCHARGE_ON		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MPQ7920_REGULATOR_EN_OFFSET	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* values in mV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MPQ7920_BUCK_VOLT_MIN		400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MPQ7920_LDO_VOLT_MIN		650000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MPQ7920_VOLT_MAX		3587500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MPQ7920_VOLT_STEP		12500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #endif /* __MPQ7920_H__ */