^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Regulator Driver for Freescale MC13892 PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2010 Yong Shen <yong.shen@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Based on draft driver from Arnaud Patard <arnaud.patard@rtp-net.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/mc13892.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mc13xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MC13892_REVISION 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MC13892_POWERCTL0 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MC13892_POWERCTL0_USEROFFSPI 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MC13892_POWERCTL0_VCOINCELLVSEL 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MC13892_POWERCTL0_VCOINCELLVSEL_M (7<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MC13892_POWERCTL0_VCOINCELLEN (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MC13892_SWITCHERS0_SWxHI (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MC13892_SWITCHERS0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MC13892_SWITCHERS0_SW1VSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MC13892_SWITCHERS0_SW1VSEL_M (0x1f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MC13892_SWITCHERS0_SW1HI (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MC13892_SWITCHERS0_SW1EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MC13892_SWITCHERS1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MC13892_SWITCHERS1_SW2VSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC13892_SWITCHERS1_SW2VSEL_M (0x1f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MC13892_SWITCHERS1_SW2HI (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MC13892_SWITCHERS1_SW2EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MC13892_SWITCHERS2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MC13892_SWITCHERS2_SW3VSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MC13892_SWITCHERS2_SW3VSEL_M (0x1f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MC13892_SWITCHERS2_SW3HI (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MC13892_SWITCHERS2_SW3EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MC13892_SWITCHERS3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MC13892_SWITCHERS3_SW4VSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MC13892_SWITCHERS3_SW4VSEL_M (0x1f<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MC13892_SWITCHERS3_SW4HI (1<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MC13892_SWITCHERS3_SW4EN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MC13892_SWITCHERS4 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MC13892_SWITCHERS4_SW1MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MC13892_SWITCHERS4_SW1MODE_AUTO (8<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MC13892_SWITCHERS4_SW1MODE_M (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MC13892_SWITCHERS4_SW2MODE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MC13892_SWITCHERS4_SW2MODE_AUTO (8<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MC13892_SWITCHERS4_SW2MODE_M (0xf<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MC13892_SWITCHERS5 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MC13892_SWITCHERS5_SW3MODE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MC13892_SWITCHERS5_SW3MODE_AUTO (8<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MC13892_SWITCHERS5_SW3MODE_M (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MC13892_SWITCHERS5_SW4MODE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MC13892_SWITCHERS5_SW4MODE_AUTO (8<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MC13892_SWITCHERS5_SW4MODE_M (0xf<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MC13892_SWITCHERS5_SWBSTEN (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MC13892_REGULATORSETTING0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MC13892_REGULATORSETTING0_VGEN1VSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MC13892_REGULATORSETTING0_VDIGVSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MC13892_REGULATORSETTING0_VGEN2VSEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MC13892_REGULATORSETTING0_VPLLVSEL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MC13892_REGULATORSETTING0_VUSB2VSEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MC13892_REGULATORSETTING0_VGEN3VSEL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MC13892_REGULATORSETTING0_VCAMVSEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MC13892_REGULATORSETTING0_VGEN1VSEL_M (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MC13892_REGULATORSETTING0_VDIGVSEL_M (3<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MC13892_REGULATORSETTING0_VGEN2VSEL_M (7<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MC13892_REGULATORSETTING0_VPLLVSEL_M (3<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MC13892_REGULATORSETTING0_VUSB2VSEL_M (3<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MC13892_REGULATORSETTING0_VGEN3VSEL_M (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MC13892_REGULATORSETTING0_VCAMVSEL_M (3<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MC13892_REGULATORSETTING1 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MC13892_REGULATORSETTING1_VVIDEOVSEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MC13892_REGULATORSETTING1_VAUDIOVSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MC13892_REGULATORSETTING1_VSDVSEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MC13892_REGULATORSETTING1_VVIDEOVSEL_M (3<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MC13892_REGULATORSETTING1_VAUDIOVSEL_M (3<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MC13892_REGULATORSETTING1_VSDVSEL_M (7<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MC13892_REGULATORMODE0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MC13892_REGULATORMODE0_VGEN1EN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MC13892_REGULATORMODE0_VGEN1STDBY (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MC13892_REGULATORMODE0_VGEN1MODE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MC13892_REGULATORMODE0_VIOHIEN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MC13892_REGULATORMODE0_VIOHISTDBY (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MC13892_REGULATORMODE0_VIOHIMODE (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MC13892_REGULATORMODE0_VDIGEN (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MC13892_REGULATORMODE0_VDIGSTDBY (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MC13892_REGULATORMODE0_VDIGMODE (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MC13892_REGULATORMODE0_VGEN2EN (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MC13892_REGULATORMODE0_VGEN2STDBY (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MC13892_REGULATORMODE0_VGEN2MODE (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MC13892_REGULATORMODE0_VPLLEN (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MC13892_REGULATORMODE0_VPLLSTDBY (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MC13892_REGULATORMODE0_VPLLMODE (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MC13892_REGULATORMODE0_VUSB2EN (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MC13892_REGULATORMODE0_VUSB2STDBY (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MC13892_REGULATORMODE0_VUSB2MODE (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MC13892_REGULATORMODE1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MC13892_REGULATORMODE1_VGEN3EN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MC13892_REGULATORMODE1_VGEN3STDBY (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MC13892_REGULATORMODE1_VGEN3MODE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MC13892_REGULATORMODE1_VCAMEN (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MC13892_REGULATORMODE1_VCAMSTDBY (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MC13892_REGULATORMODE1_VCAMMODE (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MC13892_REGULATORMODE1_VCAMCONFIGEN (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MC13892_REGULATORMODE1_VVIDEOEN (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MC13892_REGULATORMODE1_VVIDEOSTDBY (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MC13892_REGULATORMODE1_VVIDEOMODE (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MC13892_REGULATORMODE1_VAUDIOEN (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MC13892_REGULATORMODE1_VAUDIOSTDBY (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MC13892_REGULATORMODE1_VAUDIOMODE (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MC13892_REGULATORMODE1_VSDEN (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MC13892_REGULATORMODE1_VSDSTDBY (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MC13892_REGULATORMODE1_VSDMODE (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MC13892_POWERMISC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MC13892_POWERMISC_GPO1EN (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MC13892_POWERMISC_GPO2EN (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MC13892_POWERMISC_GPO3EN (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MC13892_POWERMISC_GPO4EN (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MC13892_POWERMISC_PWGT1SPIEN (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MC13892_POWERMISC_PWGT2SPIEN (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MC13892_POWERMISC_GPO4ADINEN (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MC13892_POWERMISC_PWGTSPI_M (3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MC13892_USB1 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MC13892_USB1_VUSBEN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const unsigned int mc13892_vcoincell[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 2500000, 2700000, 2800000, 2900000, 3000000, 3100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 3200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const unsigned int mc13892_sw1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 600000, 625000, 650000, 675000, 700000, 725000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 750000, 775000, 800000, 825000, 850000, 875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 900000, 925000, 950000, 975000, 1000000, 1025000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 1350000, 1375000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * Note: this table is used to derive SWxVSEL by index into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * the array. Offset the values by the index of 1100000uV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * to get the actual register value for that voltage selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * if the HI bit is to be set as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MC13892_SWxHI_SEL_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const unsigned int mc13892_sw[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 600000, 625000, 650000, 675000, 700000, 725000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 750000, 775000, 800000, 825000, 850000, 875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 900000, 925000, 950000, 975000, 1000000, 1025000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 1050000, 1075000, 1100000, 1125000, 1150000, 1175000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 1200000, 1225000, 1250000, 1275000, 1300000, 1325000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 1350000, 1375000, 1400000, 1425000, 1450000, 1475000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 1500000, 1525000, 1550000, 1575000, 1600000, 1625000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 1650000, 1675000, 1700000, 1725000, 1750000, 1775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 1800000, 1825000, 1850000, 1875000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned int mc13892_swbst[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int mc13892_viohi[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int mc13892_vpll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 1050000, 1250000, 1650000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned int mc13892_vdig[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 1050000, 1250000, 1650000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned int mc13892_vsd[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 1800000, 2000000, 2600000, 2700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 2800000, 2900000, 3000000, 3150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const unsigned int mc13892_vusb2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 2400000, 2600000, 2700000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const unsigned int mc13892_vvideo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 2700000, 2775000, 2500000, 2600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned int mc13892_vaudio[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 2300000, 2500000, 2775000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static const unsigned int mc13892_vcam[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 2500000, 2600000, 2750000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const unsigned int mc13892_vgen1[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 1200000, 1500000, 2775000, 3150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const unsigned int mc13892_vgen2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 1200000, 1500000, 1600000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 2700000, 2800000, 3000000, 3150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const unsigned int mc13892_vgen3[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 1800000, 2900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) static const unsigned int mc13892_vusb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const unsigned int mc13892_gpo[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 2750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const unsigned int mc13892_pwgtdrv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static const struct regulator_ops mc13892_gpo_regulator_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const struct regulator_ops mc13892_sw_regulator_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MC13892_FIXED_DEFINE(name, node, reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MC13xxx_FIXED_DEFINE(MC13892_, name, node, reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) mc13xxx_fixed_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MC13892_GPO_DEFINE(name, node, reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) MC13xxx_GPO_DEFINE(MC13892_, name, node, reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) mc13892_gpo_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MC13892_SW_DEFINE(name, node, reg, vsel_reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mc13892_sw_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MC13892_DEFINE_REGU(name, node, reg, vsel_reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MC13xxx_DEFINE(MC13892_, name, node, reg, vsel_reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) mc13xxx_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static struct mc13xxx_regulator mc13892_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) MC13892_DEFINE_REGU(VCOINCELL, vcoincell, POWERCTL0, POWERCTL0, mc13892_vcoincell),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MC13892_SW_DEFINE(SW1, sw1, SWITCHERS0, SWITCHERS0, mc13892_sw1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) MC13892_SW_DEFINE(SW2, sw2, SWITCHERS1, SWITCHERS1, mc13892_sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MC13892_SW_DEFINE(SW3, sw3, SWITCHERS2, SWITCHERS2, mc13892_sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) MC13892_SW_DEFINE(SW4, sw4, SWITCHERS3, SWITCHERS3, mc13892_sw),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MC13892_FIXED_DEFINE(SWBST, swbst, SWITCHERS5, mc13892_swbst),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) MC13892_FIXED_DEFINE(VIOHI, viohi, REGULATORMODE0, mc13892_viohi),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mc13892_vpll),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MC13892_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) mc13892_vdig),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) MC13892_DEFINE_REGU(VSD, vsd, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) mc13892_vsd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) MC13892_DEFINE_REGU(VUSB2, vusb2, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mc13892_vusb2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) MC13892_DEFINE_REGU(VVIDEO, vvideo, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) mc13892_vvideo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) MC13892_DEFINE_REGU(VAUDIO, vaudio, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) mc13892_vaudio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) MC13892_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) mc13892_vcam),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MC13892_DEFINE_REGU(VGEN1, vgen1, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) mc13892_vgen1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MC13892_DEFINE_REGU(VGEN2, vgen2, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) mc13892_vgen2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MC13892_DEFINE_REGU(VGEN3, vgen3, REGULATORMODE1, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) mc13892_vgen3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) MC13892_FIXED_DEFINE(VUSB, vusb, USB1, mc13892_vusb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) MC13892_GPO_DEFINE(GPO1, gpo1, POWERMISC, mc13892_gpo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MC13892_GPO_DEFINE(GPO2, gpo2, POWERMISC, mc13892_gpo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) MC13892_GPO_DEFINE(GPO3, gpo3, POWERMISC, mc13892_gpo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) MC13892_GPO_DEFINE(GPO4, gpo4, POWERMISC, mc13892_gpo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) MC13892_GPO_DEFINE(PWGT1SPI, pwgt1spi, POWERMISC, mc13892_pwgtdrv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) MC13892_GPO_DEFINE(PWGT2SPI, pwgt2spi, POWERMISC, mc13892_pwgtdrv),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int mc13892_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct mc13xxx *mc13892 = priv->mc13xxx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 valread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) BUG_ON(val & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) ret = mc13xxx_reg_read(mc13892, MC13892_POWERMISC, &valread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* Update the stored state for Power Gates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) priv->powermisc_pwgt_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) (priv->powermisc_pwgt_state & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) priv->powermisc_pwgt_state &= MC13892_POWERMISC_PWGTSPI_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Construct the new register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) valread = (valread & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* Overwrite the PWGTxEN with the stored version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) valread = (valread & ~MC13892_POWERMISC_PWGTSPI_M) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) priv->powermisc_pwgt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ret = mc13xxx_reg_write(mc13892, MC13892_POWERMISC, valread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int mc13892_gpo_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u32 en_val = mc13892_regulators[id].enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 mask = mc13892_regulators[id].enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Power Gate enable value is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) en_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (id == MC13892_GPO4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) mask |= MC13892_POWERMISC_GPO4ADINEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return mc13892_powermisc_rmw(priv, mask, en_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int mc13892_gpo_regulator_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u32 dis_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Power Gate disable value is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (id == MC13892_PWGT1SPI || id == MC13892_PWGT2SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) dis_val = mc13892_regulators[id].enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dis_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int mc13892_gpo_regulator_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int ret, id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Power Gates state is stored in powermisc_pwgt_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * where the meaning of bits is negated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) val = (val & ~MC13892_POWERMISC_PWGTSPI_M) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) (priv->powermisc_pwgt_state ^ MC13892_POWERMISC_PWGTSPI_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return (val & mc13892_regulators[id].enable_bit) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct regulator_ops mc13892_gpo_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .enable = mc13892_gpo_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .disable = mc13892_gpo_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .is_enabled = mc13892_gpo_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .set_voltage = mc13xxx_fixed_regulator_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int mc13892_sw_regulator_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int ret, id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) unsigned int val, selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = mc13xxx_reg_read(priv->mc13xxx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mc13892_regulators[id].vsel_reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Figure out if the HI bit is set inside the switcher mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * since this means the selector value we return is at a different
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * offset into the selector table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * According to the MC13892 documentation note 59 (Table 47) the SW1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * buck switcher does not support output range programming therefore
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * the HI bit must always remain 0. So do not do anything strange if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * our register is MC13892_SWITCHERS0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) selector = val & mc13892_regulators[id].vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) if ((mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) (val & MC13892_SWITCHERS0_SWxHI)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) selector += MC13892_SWxHI_SEL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) dev_dbg(rdev_get_dev(rdev), "%s id: %d val: 0x%08x selector: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) __func__, id, val, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) return selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static int mc13892_sw_regulator_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) int volt, mask, id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) u32 reg_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) volt = rdev->desc->volt_table[selector];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mask = mc13892_regulators[id].vsel_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) reg_value = selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Don't mess with the HI bit or support HI voltage offsets for SW1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * Since the get_voltage_sel callback has given a fudged value for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * the selector offset, we need to back out that offset if HI is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * to be set so we write the correct value to the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) * The HI bit addition and selector offset handling COULD be more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * complicated by shifting and masking off the voltage selector part
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * of the register then logical OR it back in, but since the selector
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * is at bits 4:0 there is very little point. This makes the whole
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) * thing more readable and we do far less work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (mc13892_regulators[id].vsel_reg != MC13892_SWITCHERS0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mask |= MC13892_SWITCHERS0_SWxHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (volt > 1375000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) reg_value -= MC13892_SWxHI_SEL_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) reg_value |= MC13892_SWITCHERS0_SWxHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) reg_value &= ~MC13892_SWITCHERS0_SWxHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].vsel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mask, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static const struct regulator_ops mc13892_sw_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .set_voltage_sel = mc13892_sw_regulator_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .get_voltage_sel = mc13892_sw_regulator_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int mc13892_vcam_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) unsigned int en_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int ret, id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (mode == REGULATOR_MODE_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) en_val = MC13892_REGULATORMODE1_VCAMCONFIGEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret = mc13xxx_reg_rmw(priv->mc13xxx, mc13892_regulators[id].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MC13892_REGULATORMODE1_VCAMCONFIGEN, en_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static unsigned int mc13892_vcam_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) int ret, id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) ret = mc13xxx_reg_read(priv->mc13xxx, mc13892_regulators[id].reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (val & MC13892_REGULATORMODE1_VCAMCONFIGEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static struct regulator_ops mc13892_vcam_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int mc13892_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct mc13xxx_regulator_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct mc13xxx *mc13892 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct mc13xxx_regulator_platform_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mc13xxx_regulator_init_data *mc13xxx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int num_regulators = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) num_regulators = mc13xxx_get_num_regulators_dt(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (num_regulators <= 0 && pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) num_regulators = pdata->num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (num_regulators <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) priv = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct_size(priv, regulators, num_regulators),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) priv->num_regulators = num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) priv->mc13xxx_regulators = mc13892_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) priv->mc13xxx = mc13892;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mc13xxx_lock(mc13892);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = mc13xxx_reg_read(mc13892, MC13892_REVISION, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* enable switch auto mode (on 2.0A silicon only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if ((val & 0x0000FFFF) == 0x45d0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) MC13892_SWITCHERS4_SW1MODE_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MC13892_SWITCHERS4_SW2MODE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MC13892_SWITCHERS4_SW1MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MC13892_SWITCHERS4_SW2MODE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = mc13xxx_reg_rmw(mc13892, MC13892_SWITCHERS5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MC13892_SWITCHERS5_SW3MODE_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) MC13892_SWITCHERS5_SW4MODE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) MC13892_SWITCHERS5_SW3MODE_AUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MC13892_SWITCHERS5_SW4MODE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mc13xxx_unlock(mc13892);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* update mc13892_vcam ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) memcpy(&mc13892_vcam_ops, mc13892_regulators[MC13892_VCAM].desc.ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) sizeof(struct regulator_ops));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mc13892_vcam_ops.set_mode = mc13892_vcam_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mc13892_vcam_ops.get_mode = mc13892_vcam_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) mc13892_regulators[MC13892_VCAM].desc.ops = &mc13892_vcam_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13892_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) ARRAY_SIZE(mc13892_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < priv->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct regulator_init_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct device_node *node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (mc13xxx_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) id = mc13xxx_data[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) init_data = mc13xxx_data[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) node = mc13xxx_data[i].node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) id = pdata->regulators[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) init_data = pdata->regulators[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) desc = &mc13892_regulators[id].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) config.init_data = init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) config.driver_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) config.of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (IS_ERR(priv->regulators[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(&pdev->dev, "failed to register regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mc13892_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return PTR_ERR(priv->regulators[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) mc13xxx_unlock(mc13892);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static struct platform_driver mc13892_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .name = "mc13892-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .probe = mc13892_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int __init mc13892_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return platform_driver_register(&mc13892_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) subsys_initcall(mc13892_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static void __exit mc13892_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) platform_driver_unregister(&mc13892_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) module_exit(mc13892_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) MODULE_AUTHOR("Yong Shen <yong.shen@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) MODULE_DESCRIPTION("Regulator Driver for Freescale MC13892 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MODULE_ALIAS("platform:mc13892-regulator");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags