^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // Regulator Driver for Freescale MC13783 PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // Copyright 2010 Yong Shen <yong.shen@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mfd/mc13783.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "mc13xxx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MC13783_REG_SWITCHERS0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* Enable does not exist for SW1A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MC13783_REG_SWITCHERS0_SW1AEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MC13783_REG_SWITCHERS0_SW1AVSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MC13783_REG_SWITCHERS0_SW1AVSEL_M (63 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MC13783_REG_SWITCHERS1 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Enable does not exist for SW1B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MC13783_REG_SWITCHERS1_SW1BEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MC13783_REG_SWITCHERS1_SW1BVSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MC13783_REG_SWITCHERS1_SW1BVSEL_M (63 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MC13783_REG_SWITCHERS2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Enable does not exist for SW2A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MC13783_REG_SWITCHERS2_SW2AEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MC13783_REG_SWITCHERS2_SW2AVSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MC13783_REG_SWITCHERS2_SW2AVSEL_M (63 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MC13783_REG_SWITCHERS3 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Enable does not exist for SW2B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MC13783_REG_SWITCHERS3_SW2BEN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MC13783_REG_SWITCHERS3_SW2BVSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MC13783_REG_SWITCHERS3_SW2BVSEL_M (63 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MC13783_REG_SWITCHERS5 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MC13783_REG_SWITCHERS5_SW3EN (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MC13783_REG_SWITCHERS5_SW3VSEL 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MC13783_REG_SWITCHERS5_SW3VSEL_M (3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MC13783_REG_REGULATORSETTING0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MC13783_REG_REGULATORSETTING0_VDIGVSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MC13783_REG_REGULATORSETTING0_VGENVSEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MC13783_REG_REGULATORSETTING0_VSIMVSEL 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MC13783_REG_REGULATORSETTING0_VESIMVSEL 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MC13783_REG_REGULATORSETTING0_VCAMVSEL 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MC13783_REG_REGULATORSETTING0_VIOLOVSEL_M (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MC13783_REG_REGULATORSETTING0_VDIGVSEL_M (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MC13783_REG_REGULATORSETTING0_VGENVSEL_M (7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MC13783_REG_REGULATORSETTING0_VRFDIGVSEL_M (3 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MC13783_REG_REGULATORSETTING0_VRFREFVSEL_M (3 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MC13783_REG_REGULATORSETTING0_VRFCPVSEL_M (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MC13783_REG_REGULATORSETTING0_VSIMVSEL_M (1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MC13783_REG_REGULATORSETTING0_VESIMVSEL_M (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MC13783_REG_REGULATORSETTING0_VCAMVSEL_M (7 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MC13783_REG_REGULATORSETTING1 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MC13783_REG_REGULATORSETTING1_VVIBVSEL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MC13783_REG_REGULATORSETTING1_VRF1VSEL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MC13783_REG_REGULATORSETTING1_VRF2VSEL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MC13783_REG_REGULATORSETTING1_VVIBVSEL_M (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MC13783_REG_REGULATORSETTING1_VRF1VSEL_M (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MC13783_REG_REGULATORSETTING1_VRF2VSEL_M (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MC13783_REG_REGULATORSETTING1_VMMC1VSEL_M (7 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MC13783_REG_REGULATORSETTING1_VMMC2VSEL_M (7 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MC13783_REG_REGULATORMODE0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MC13783_REG_REGULATORMODE0_VAUDIOEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MC13783_REG_REGULATORMODE0_VIOHIEN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MC13783_REG_REGULATORMODE0_VIOLOEN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MC13783_REG_REGULATORMODE0_VDIGEN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MC13783_REG_REGULATORMODE0_VGENEN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MC13783_REG_REGULATORMODE0_VRFDIGEN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MC13783_REG_REGULATORMODE0_VRFREFEN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MC13783_REG_REGULATORMODE0_VRFCPEN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MC13783_REG_REGULATORMODE1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MC13783_REG_REGULATORMODE1_VSIMEN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MC13783_REG_REGULATORMODE1_VESIMEN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MC13783_REG_REGULATORMODE1_VCAMEN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MC13783_REG_REGULATORMODE1_VRFBGEN (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MC13783_REG_REGULATORMODE1_VVIBEN (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MC13783_REG_REGULATORMODE1_VRF1EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MC13783_REG_REGULATORMODE1_VRF2EN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MC13783_REG_REGULATORMODE1_VMMC1EN (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MC13783_REG_REGULATORMODE1_VMMC2EN (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MC13783_REG_POWERMISC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MC13783_REG_POWERMISC_GPO1EN (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MC13783_REG_POWERMISC_GPO2EN (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MC13783_REG_POWERMISC_GPO3EN (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MC13783_REG_POWERMISC_GPO4EN (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MC13783_REG_POWERMISC_PWGT1SPIEN (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MC13783_REG_POWERMISC_PWGT2SPIEN (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MC13783_REG_POWERMISC_PWGTSPI_M (3 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Voltage Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const int mc13783_sw1x_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 900000, 925000, 950000, 975000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 1000000, 1025000, 1050000, 1075000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 1100000, 1125000, 1150000, 1175000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 1200000, 1225000, 1250000, 1275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 1300000, 1325000, 1350000, 1375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 1400000, 1425000, 1450000, 1475000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 1500000, 1525000, 1550000, 1575000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 1600000, 1625000, 1650000, 1675000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 1700000, 1700000, 1700000, 1700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 1800000, 1800000, 1800000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 1850000, 1850000, 1850000, 1850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 2000000, 2000000, 2000000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 2100000, 2100000, 2100000, 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 2200000, 2200000, 2200000, 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 2200000, 2200000, 2200000, 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 2200000, 2200000, 2200000, 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const int mc13783_sw2x_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 900000, 925000, 950000, 975000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 1000000, 1025000, 1050000, 1075000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 1100000, 1125000, 1150000, 1175000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 1200000, 1225000, 1250000, 1275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1300000, 1325000, 1350000, 1375000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 1400000, 1425000, 1450000, 1475000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 1500000, 1525000, 1550000, 1575000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 1600000, 1625000, 1650000, 1675000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 1700000, 1700000, 1700000, 1700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 1800000, 1800000, 1800000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 1900000, 1900000, 1900000, 1900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 2000000, 2000000, 2000000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 2100000, 2100000, 2100000, 2100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 2200000, 2200000, 2200000, 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 2200000, 2200000, 2200000, 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 2200000, 2200000, 2200000, 2200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static const unsigned int mc13783_sw3_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 5000000, 5000000, 5000000, 5500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const unsigned int mc13783_vaudio_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const unsigned int mc13783_viohi_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const unsigned int mc13783_violo_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 1200000, 1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const unsigned int mc13783_vdig_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 1200000, 1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static const unsigned int mc13783_vgen_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 1200000, 1300000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 1100000, 2000000, 2775000, 2400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static const unsigned int mc13783_vrfdig_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 1200000, 1500000, 1800000, 1875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const unsigned int mc13783_vrfref_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 2475000, 2600000, 2700000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static const unsigned int mc13783_vrfcp_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 2700000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const unsigned int mc13783_vsim_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 1800000, 2900000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const unsigned int mc13783_vesim_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 1800000, 2900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static const unsigned int mc13783_vcam_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 1500000, 1800000, 2500000, 2550000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 2600000, 2750000, 2800000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const unsigned int mc13783_vrfbg_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static const unsigned int mc13783_vvib_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 1300000, 1800000, 2000000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static const unsigned int mc13783_vmmc_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 1600000, 1800000, 2000000, 2600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 2700000, 2800000, 2900000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static const unsigned int mc13783_vrf_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 1500000, 1875000, 2700000, 2775000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static const unsigned int mc13783_gpo_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 3100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static const unsigned int mc13783_pwgtdrv_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 5500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static const struct regulator_ops mc13783_gpo_regulator_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MC13783_DEFINE(prefix, name, node, reg, vsel_reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MC13xxx_DEFINE(MC13783_REG_, name, node, reg, vsel_reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) mc13xxx_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MC13783_FIXED_DEFINE(prefix, name, node, reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MC13xxx_FIXED_DEFINE(MC13783_REG_, name, node, reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mc13xxx_fixed_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MC13783_GPO_DEFINE(prefix, name, node, reg, voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) MC13xxx_GPO_DEFINE(MC13783_REG_, name, node, reg, voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mc13783_gpo_regulator_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MC13783_DEFINE_SW(_name, _node, _reg, _vsel_reg, _voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MC13783_DEFINE_REGU(_name, _node, _reg, _vsel_reg, _voltages) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MC13783_DEFINE(REG, _name, _node, _reg, _vsel_reg, _voltages)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static struct mc13xxx_regulator mc13783_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) MC13783_DEFINE_SW(SW1A, sw1a, SWITCHERS0, SWITCHERS0, mc13783_sw1x_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) MC13783_DEFINE_SW(SW1B, sw1b, SWITCHERS1, SWITCHERS1, mc13783_sw1x_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MC13783_DEFINE_SW(SW2A, sw2a, SWITCHERS2, SWITCHERS2, mc13783_sw2x_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) MC13783_DEFINE_SW(SW2B, sw2b, SWITCHERS3, SWITCHERS3, mc13783_sw2x_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) MC13783_DEFINE_SW(SW3, sw3, SWITCHERS5, SWITCHERS5, mc13783_sw3_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) MC13783_FIXED_DEFINE(REG, VAUDIO, vaudio, REGULATORMODE0, mc13783_vaudio_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) MC13783_FIXED_DEFINE(REG, VIOHI, viohi, REGULATORMODE0, mc13783_viohi_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MC13783_DEFINE_REGU(VIOLO, violo, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) mc13783_violo_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MC13783_DEFINE_REGU(VDIG, vdig, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) mc13783_vdig_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MC13783_DEFINE_REGU(VGEN, vgen, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mc13783_vgen_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MC13783_DEFINE_REGU(VRFDIG, vrfdig, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) mc13783_vrfdig_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) MC13783_DEFINE_REGU(VRFREF, vrfref, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) mc13783_vrfref_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) MC13783_DEFINE_REGU(VRFCP, vrfcp, REGULATORMODE0, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mc13783_vrfcp_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) MC13783_DEFINE_REGU(VSIM, vsim, REGULATORMODE1, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) mc13783_vsim_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) MC13783_DEFINE_REGU(VESIM, vesim, REGULATORMODE1, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) mc13783_vesim_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) MC13783_DEFINE_REGU(VCAM, vcam, REGULATORMODE1, REGULATORSETTING0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mc13783_vcam_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) MC13783_FIXED_DEFINE(REG, VRFBG, vrfbg, REGULATORMODE1, mc13783_vrfbg_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) MC13783_DEFINE_REGU(VVIB, vvib, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) mc13783_vvib_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MC13783_DEFINE_REGU(VRF1, vrf1, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mc13783_vrf_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) MC13783_DEFINE_REGU(VRF2, vrf2, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mc13783_vrf_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) MC13783_DEFINE_REGU(VMMC1, vmmc1, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mc13783_vmmc_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) MC13783_DEFINE_REGU(VMMC2, vmmc2, REGULATORMODE1, REGULATORSETTING1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mc13783_vmmc_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) MC13783_GPO_DEFINE(REG, GPO1, gpo1, POWERMISC, mc13783_gpo_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) MC13783_GPO_DEFINE(REG, GPO2, gpo1, POWERMISC, mc13783_gpo_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MC13783_GPO_DEFINE(REG, GPO3, gpo1, POWERMISC, mc13783_gpo_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) MC13783_GPO_DEFINE(REG, GPO4, gpo1, POWERMISC, mc13783_gpo_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MC13783_GPO_DEFINE(REG, PWGT1SPI, pwgt1spi, POWERMISC, mc13783_pwgtdrv_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MC13783_GPO_DEFINE(REG, PWGT2SPI, pwgt2spi, POWERMISC, mc13783_pwgtdrv_val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int mc13783_powermisc_rmw(struct mc13xxx_regulator_priv *priv, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct mc13xxx *mc13783 = priv->mc13xxx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 valread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) BUG_ON(val & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ret = mc13xxx_reg_read(mc13783, MC13783_REG_POWERMISC, &valread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Update the stored state for Power Gates. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) priv->powermisc_pwgt_state =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) (priv->powermisc_pwgt_state & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) priv->powermisc_pwgt_state &= MC13783_REG_POWERMISC_PWGTSPI_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Construct the new register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) valread = (valread & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Overwrite the PWGTxEN with the stored version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) valread = (valread & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) priv->powermisc_pwgt_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) ret = mc13xxx_reg_write(mc13783, MC13783_REG_POWERMISC, valread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int mc13783_gpo_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 en_val = mc13xxx_regulators[id].enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Power Gate enable value is 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (id == MC13783_REG_PWGT1SPI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) id == MC13783_REG_PWGT2SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) en_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) en_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int mc13783_gpo_regulator_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u32 dis_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_dbg(rdev_get_dev(rdev), "%s id: %d\n", __func__, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Power Gate disable value is 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (id == MC13783_REG_PWGT1SPI ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) id == MC13783_REG_PWGT2SPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dis_val = mc13xxx_regulators[id].enable_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) dis_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int mc13783_gpo_regulator_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct mc13xxx_regulator_priv *priv = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct mc13xxx_regulator *mc13xxx_regulators = priv->mc13xxx_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int ret, id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) mc13xxx_lock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = mc13xxx_reg_read(priv->mc13xxx, mc13xxx_regulators[id].reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mc13xxx_unlock(priv->mc13xxx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* Power Gates state is stored in powermisc_pwgt_state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * where the meaning of bits is negated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val = (val & ~MC13783_REG_POWERMISC_PWGTSPI_M) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (priv->powermisc_pwgt_state ^ MC13783_REG_POWERMISC_PWGTSPI_M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return (val & mc13xxx_regulators[id].enable_bit) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static const struct regulator_ops mc13783_gpo_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .enable = mc13783_gpo_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .disable = mc13783_gpo_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .is_enabled = mc13783_gpo_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .set_voltage = mc13xxx_fixed_regulator_set_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static int mc13783_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct mc13xxx_regulator_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct mc13xxx *mc13783 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct mc13xxx_regulator_platform_data *pdata =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct mc13xxx_regulator_init_data *mc13xxx_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int i, num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) num_regulators = mc13xxx_get_num_regulators_dt(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (num_regulators <= 0 && pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) num_regulators = pdata->num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (num_regulators <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) priv = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct_size(priv, regulators, num_regulators),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) priv->num_regulators = num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) priv->mc13xxx_regulators = mc13783_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) priv->mc13xxx = mc13783;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) platform_set_drvdata(pdev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mc13xxx_data = mc13xxx_parse_regulators_dt(pdev, mc13783_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ARRAY_SIZE(mc13783_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) for (i = 0; i < priv->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct regulator_init_data *init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct device_node *node = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (mc13xxx_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) id = mc13xxx_data[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) init_data = mc13xxx_data[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) node = mc13xxx_data[i].node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) id = pdata->regulators[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) init_data = pdata->regulators[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) desc = &mc13783_regulators[id].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) config.init_data = init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) config.driver_data = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) config.of_node = node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) priv->regulators[i] = devm_regulator_register(&pdev->dev, desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (IS_ERR(priv->regulators[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_err(&pdev->dev, "failed to register regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) mc13783_regulators[i].desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return PTR_ERR(priv->regulators[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static struct platform_driver mc13783_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .name = "mc13783-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .probe = mc13783_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static int __init mc13783_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return platform_driver_register(&mc13783_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) subsys_initcall(mc13783_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static void __exit mc13783_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) platform_driver_unregister(&mc13783_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) module_exit(mc13783_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) MODULE_DESCRIPTION("Regulator Driver for Freescale MC13783 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) MODULE_ALIAS("platform:mc13783-regulator");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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