^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * max8973-regulator.c -- Maxim max8973
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Regulator driver for MAXIM 8973 DC-DC step-down switching regulator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2012, NVIDIA Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * whether express or implied; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * 02111-1307, USA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/regulator/max8973-regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/thermal.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MAX8973_VOUT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MAX8973_VOUT_DVS 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MAX8973_CONTROL1 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MAX8973_CONTROL2 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MAX8973_CHIPID1 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MAX8973_CHIPID2 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MAX8973_MAX_VOUT_REG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* MAX8973_VOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MAX8973_VOUT_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MAX8973_VOUT_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* MAX8973_VOUT_DVS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAX8973_DVS_VOUT_MASK 0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* MAX8973_CONTROL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MAX8973_SNS_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAX8973_FPWM_EN_M BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAX8973_NFSR_ENABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MAX8973_AD_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MAX8973_BIAS_ENABLE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAX8973_FREQSHIFT_9PER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAX8973_RAMP_12mV_PER_US 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAX8973_RAMP_25mV_PER_US 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAX8973_RAMP_50mV_PER_US 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAX8973_RAMP_200mV_PER_US 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAX8973_RAMP_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* MAX8973_CONTROL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAX8973_WDTMR_ENABLE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX8973_DISCH_ENBABLE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAX8973_FT_ENABLE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAX77621_T_JUNCTION_120 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MAX8973_CKKADV_TRIP_MASK 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAX8973_CKKADV_TRIP_DISABLE 0xC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MAX8973_CKKADV_TRIP_75mV_PER_US 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAX8973_CKKADV_TRIP_150mV_PER_US 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MAX8973_CKKADV_TRIP_75mV_PER_US_HIST_DIS 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MAX8973_CONTROL_CLKADV_TRIP_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX8973_INDUCTOR_MIN_30_PER 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX8973_INDUCTOR_NOMINAL 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MAX8973_INDUCTOR_PLUS_30_PER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MAX8973_INDUCTOR_PLUS_60_PER 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MAX8973_CONTROL_INDUCTOR_VALUE_MASK 0x00300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MAX8973_MIN_VOLATGE 606250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MAX8973_MAX_VOLATGE 1400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MAX8973_VOLATGE_STEP 6250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MAX8973_BUCK_N_VOLTAGE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAX77621_CHIPID_TJINT_S BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAX77621_NORMAL_OPERATING_TEMP 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAX77621_TJINT_WARNING_TEMP_120 120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAX77621_TJINT_WARNING_TEMP_140 140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum device_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MAX8973,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MAX77621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Maxim 8973 chip information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct max8973_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool enable_external_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int dvs_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int lru_index[MAX8973_MAX_VOUT_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int curr_vout_val[MAX8973_MAX_VOUT_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int curr_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int curr_gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct regulator_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) enum device_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) int junction_temp_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct thermal_zone_device *tz_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * find_voltage_set_register: Find new voltage configuration register (VOUT).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * The finding of the new VOUT register will be based on the LRU mechanism.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * Each VOUT register will have different voltage configured . This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Function will look if any of the VOUT register have requested voltage set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * - If it is already there then it will make that register as most
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * recently used and return as found so that caller need not to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * the VOUT register but need to set the proper gpios to select this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * VOUT register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * - If requested voltage is not found then it will use the least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * recently mechanism to get new VOUT register for new configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * and will return not_found so that caller need to set new VOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * register and then gpios (both).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static bool find_voltage_set_register(struct max8973_chip *tps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int req_vsel, int *vout_reg, int *gpio_val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) int new_vout_reg = tps->lru_index[MAX8973_MAX_VOUT_REG - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int found_index = MAX8973_MAX_VOUT_REG - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) for (i = 0; i < MAX8973_MAX_VOUT_REG; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (tps->curr_vout_val[tps->lru_index[i]] == req_vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) new_vout_reg = tps->lru_index[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) found_index = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) found = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) goto update_lru_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) update_lru_index:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (i = found_index; i > 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) tps->lru_index[i] = tps->lru_index[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) tps->lru_index[0] = new_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *gpio_val = new_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *vout_reg = MAX8973_VOUT + new_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int max8973_dcdc_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) ret = regmap_read(max->regmap, max->curr_vout_reg, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_err(max->dev, "register %d read failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) max->curr_vout_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return data & MAX8973_VOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static int max8973_dcdc_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned vsel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bool found = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) int vout_reg = max->curr_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int gpio_val = max->curr_gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * If gpios are available to select the VOUT register then least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * recently used register for new configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) if (gpio_is_valid(max->dvs_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) found = find_voltage_set_register(max, vsel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) &vout_reg, &gpio_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) if (!found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ret = regmap_update_bits(max->regmap, vout_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MAX8973_VOUT_MASK, vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dev_err(max->dev, "register %d update failed, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) vout_reg, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) max->curr_vout_reg = vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) max->curr_vout_val[gpio_val] = vsel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Select proper VOUT register vio gpios */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (gpio_is_valid(max->dvs_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) gpio_set_value_cansleep(max->dvs_gpio, gpio_val & 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) max->curr_gpio_val = gpio_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static int max8973_dcdc_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int pwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Enable force PWM mode in FAST mode only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) pwm = MAX8973_FPWM_EN_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) pwm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = regmap_update_bits(max->regmap, MAX8973_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) MAX8973_FPWM_EN_M, pwm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) dev_err(max->dev, "register %d update failed, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MAX8973_CONTROL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static unsigned int max8973_dcdc_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ret = regmap_read(max->regmap, MAX8973_CONTROL1, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) dev_err(max->dev, "register %d read failed, err %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) MAX8973_CONTROL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return (data & MAX8973_FPWM_EN_M) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int max8973_set_ramp_delay(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* Set ramp delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (ramp_delay <= 12000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) control = MAX8973_RAMP_12mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) else if (ramp_delay <= 25000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) control = MAX8973_RAMP_25mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) else if (ramp_delay <= 50000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) control = MAX8973_RAMP_50mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) else if (ramp_delay <= 200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) control = MAX8973_RAMP_200mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ret = regmap_update_bits(max->regmap, MAX8973_CONTROL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) MAX8973_RAMP_MASK, control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(max->dev, "register %d update failed, %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MAX8973_CONTROL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int max8973_set_current_limit(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int min_ua, int max_ua)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (max_ua <= 9000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) val = MAX8973_CKKADV_TRIP_75mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) else if (max_ua <= 12000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) val = MAX8973_CKKADV_TRIP_150mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) val = MAX8973_CKKADV_TRIP_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) ret = regmap_update_bits(max->regmap, MAX8973_CONTROL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) MAX8973_CKKADV_TRIP_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev_err(max->dev, "register %d update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) MAX8973_CONTROL2, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int max8973_get_current_limit(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct max8973_chip *max = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int control2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) ret = regmap_read(max->regmap, MAX8973_CONTROL2, &control2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dev_err(max->dev, "register %d read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) MAX8973_CONTROL2, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) switch (control2 & MAX8973_CKKADV_TRIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) case MAX8973_CKKADV_TRIP_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 15000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) case MAX8973_CKKADV_TRIP_150mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 12000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) case MAX8973_CKKADV_TRIP_75mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return 9000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 9000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static const struct regulator_ops max8973_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .get_voltage_sel = max8973_dcdc_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .set_voltage_sel = max8973_dcdc_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .set_mode = max8973_dcdc_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .get_mode = max8973_dcdc_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .set_ramp_delay = max8973_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int max8973_init_dcdc(struct max8973_chip *max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct max8973_regulator_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) uint8_t control1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) uint8_t control2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) unsigned int data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = regmap_read(max->regmap, MAX8973_CONTROL1, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) dev_err(max->dev, "register %d read failed, err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) MAX8973_CONTROL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) control1 = data & MAX8973_RAMP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) switch (control1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) case MAX8973_RAMP_12mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) max->desc.ramp_delay = 12000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) case MAX8973_RAMP_25mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) max->desc.ramp_delay = 25000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case MAX8973_RAMP_50mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) max->desc.ramp_delay = 50000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case MAX8973_RAMP_200mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) max->desc.ramp_delay = 200000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (pdata->control_flags & MAX8973_CONTROL_REMOTE_SENSE_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) control1 |= MAX8973_SNS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!(pdata->control_flags & MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) control1 |= MAX8973_NFSR_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (pdata->control_flags & MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) control1 |= MAX8973_AD_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (pdata->control_flags & MAX8973_CONTROL_BIAS_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) control1 |= MAX8973_BIAS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) max->desc.enable_time = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) max->desc.enable_time = 240;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (pdata->control_flags & MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) control1 |= MAX8973_FREQSHIFT_9PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if ((pdata->junction_temp_warning == MAX77621_TJINT_WARNING_TEMP_120) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (max->id == MAX77621))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) control2 |= MAX77621_T_JUNCTION_120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!(pdata->control_flags & MAX8973_CONTROL_PULL_DOWN_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) control2 |= MAX8973_DISCH_ENBABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* Clock advance trip configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) switch (pdata->control_flags & MAX8973_CONTROL_CLKADV_TRIP_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case MAX8973_CONTROL_CLKADV_TRIP_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) control2 |= MAX8973_CKKADV_TRIP_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) case MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) control2 |= MAX8973_CKKADV_TRIP_75mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) case MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) control2 |= MAX8973_CKKADV_TRIP_150mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US_HIST_DIS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) control2 |= MAX8973_CKKADV_TRIP_75mV_PER_US_HIST_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /* Configure inductor value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (pdata->control_flags & MAX8973_CONTROL_INDUCTOR_VALUE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case MAX8973_CONTROL_INDUCTOR_VALUE_NOMINAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) control2 |= MAX8973_INDUCTOR_NOMINAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case MAX8973_CONTROL_INDUCTOR_VALUE_MINUS_30_PER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) control2 |= MAX8973_INDUCTOR_MIN_30_PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case MAX8973_CONTROL_INDUCTOR_VALUE_PLUS_30_PER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) control2 |= MAX8973_INDUCTOR_PLUS_30_PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) case MAX8973_CONTROL_INDUCTOR_VALUE_PLUS_60_PER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) control2 |= MAX8973_INDUCTOR_PLUS_60_PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ret = regmap_write(max->regmap, MAX8973_CONTROL1, control1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dev_err(max->dev, "register %d write failed, err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) MAX8973_CONTROL1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = regmap_write(max->regmap, MAX8973_CONTROL2, control2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev_err(max->dev, "register %d write failed, err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MAX8973_CONTROL2, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* If external control is enabled then disable EN bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (max->enable_external_control && (max->id == MAX8973)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regmap_update_bits(max->regmap, MAX8973_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) MAX8973_VOUT_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dev_err(max->dev, "register %d update failed, err = %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) MAX8973_VOUT, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int max8973_thermal_read_temp(void *data, int *temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct max8973_chip *mchip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = regmap_read(mchip->regmap, MAX8973_CHIPID1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(mchip->dev, "Failed to read register CHIPID1, %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* +1 degC to trigger cool devive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (val & MAX77621_CHIPID_TJINT_S)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *temp = mchip->junction_temp_warning + 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) *temp = MAX77621_NORMAL_OPERATING_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static irqreturn_t max8973_thermal_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct max8973_chip *mchip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) thermal_zone_device_update(mchip->tz_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) THERMAL_EVENT_UNSPECIFIED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct thermal_zone_of_device_ops max77621_tz_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .get_temp = max8973_thermal_read_temp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int max8973_thermal_init(struct max8973_chip *mchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct thermal_zone_device *tzd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct irq_data *irq_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned long irq_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (mchip->id != MAX77621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) tzd = devm_thermal_zone_of_sensor_register(mchip->dev, 0, mchip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) &max77621_tz_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (IS_ERR(tzd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = PTR_ERR(tzd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(mchip->dev, "Failed to register thermal sensor: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (mchip->irq <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) irq_data = irq_get_irq_data(mchip->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (irq_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) irq_flags = irqd_get_trigger_type(irq_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = devm_request_threaded_irq(mchip->dev, mchip->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) max8973_thermal_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) IRQF_ONESHOT | IRQF_SHARED | irq_flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_name(mchip->dev), mchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) dev_err(mchip->dev, "Failed to request irq %d, %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mchip->irq, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) static const struct regmap_config max8973_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .max_register = MAX8973_CHIPID2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static struct max8973_regulator_platform_data *max8973_parse_dt(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct max8973_regulator_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bool etr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) bool etr_sensitivity_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pdata->enable_ext_control = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "maxim,externally-enable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) pdata->dvs_gpio = of_get_named_gpio(np, "maxim,dvs-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ret = of_property_read_u32(np, "maxim,dvs-default-state", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) pdata->dvs_def_state = pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (of_property_read_bool(np, "maxim,enable-remote-sense"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) pdata->control_flags |= MAX8973_CONTROL_REMOTE_SENSE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (of_property_read_bool(np, "maxim,enable-falling-slew-rate"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) pdata->control_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MAX8973_CONTROL_FALLING_SLEW_RATE_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (of_property_read_bool(np, "maxim,enable-active-discharge"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pdata->control_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MAX8973_CONTROL_OUTPUT_ACTIVE_DISCH_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (of_property_read_bool(np, "maxim,enable-frequency-shift"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pdata->control_flags |= MAX8973_CONTROL_FREQ_SHIFT_9PER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (of_property_read_bool(np, "maxim,enable-bias-control"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pdata->control_flags |= MAX8973_CONTROL_BIAS_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) etr_enable = of_property_read_bool(np, "maxim,enable-etr");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) etr_sensitivity_high = of_property_read_bool(np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "maxim,enable-high-etr-sensitivity");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (etr_sensitivity_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) etr_enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (etr_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (etr_sensitivity_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) pdata->control_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) MAX8973_CONTROL_CLKADV_TRIP_75mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) pdata->control_flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MAX8973_CONTROL_CLKADV_TRIP_150mV_PER_US;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pdata->control_flags |= MAX8973_CONTROL_CLKADV_TRIP_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) pdata->junction_temp_warning = MAX77621_TJINT_WARNING_TEMP_140;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = of_property_read_u32(np, "junction-warn-millicelsius", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) if (!ret && (pval <= MAX77621_TJINT_WARNING_TEMP_120))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) pdata->junction_temp_warning = MAX77621_TJINT_WARNING_TEMP_120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static const struct of_device_id of_max8973_match_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { .compatible = "maxim,max8973", .data = (void *)MAX8973, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { .compatible = "maxim,max77621", .data = (void *)MAX77621, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) MODULE_DEVICE_TABLE(of, of_max8973_match_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int max8973_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct max8973_regulator_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct regulator_init_data *ridata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct max8973_chip *max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bool pdata_from_dt = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct gpio_desc *gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) enum gpiod_flags gflags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (!pdata && client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) pdata = max8973_parse_dt(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) pdata_from_dt = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dev_err(&client->dev, "No Platform data");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (pdata->dvs_gpio == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) max = devm_kzalloc(&client->dev, sizeof(*max), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (!max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) max->regmap = devm_regmap_init_i2c(client, &max8973_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (IS_ERR(max->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret = PTR_ERR(max->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) dev_err(&client->dev, "regmap init failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (client->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) const struct of_device_id *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) match = of_match_device(of_match_ptr(of_max8973_match_tbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (!match)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) max->id = (u32)((uintptr_t)match->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) max->id = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = regmap_read(max->regmap, MAX8973_CHIPID1, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dev_err(&client->dev, "register CHIPID1 read failed, %d", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_info(&client->dev, "CHIP-ID OTP: 0x%02x ID_M: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) (chip_id >> 4) & 0xF, (chip_id >> 1) & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) i2c_set_clientdata(client, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) max->ops = max8973_dcdc_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) max->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) max->desc.name = id->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) max->desc.id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) max->desc.ops = &max->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) max->desc.type = REGULATOR_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) max->desc.owner = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) max->desc.min_uV = MAX8973_MIN_VOLATGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) max->desc.uV_step = MAX8973_VOLATGE_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) max->desc.n_voltages = MAX8973_BUCK_N_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) max->dvs_gpio = (pdata->dvs_gpio) ? pdata->dvs_gpio : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) max->enable_external_control = pdata->enable_ext_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) max->curr_gpio_val = pdata->dvs_def_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) max->curr_vout_reg = MAX8973_VOUT + pdata->dvs_def_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) max->junction_temp_warning = pdata->junction_temp_warning;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) max->lru_index[0] = max->curr_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (gpio_is_valid(max->dvs_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) int gpio_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) gpio_flags = (pdata->dvs_def_state) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = devm_gpio_request_one(&client->dev, max->dvs_gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) gpio_flags, "max8973-dvs");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "gpio_request for gpio %d failed, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) max->dvs_gpio, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * Initialize the lru index with vout_reg id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * The index 0 will be most recently used and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * set with the max->curr_vout_reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) for (i = 0; i < MAX8973_MAX_VOUT_REG; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) max->lru_index[i] = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) max->lru_index[0] = max->curr_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) max->lru_index[max->curr_vout_reg] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) * If there is no DVS GPIO, the VOUT register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * address is fixed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) max->ops.set_voltage_sel = regulator_set_voltage_sel_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) max->ops.get_voltage_sel = regulator_get_voltage_sel_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) max->desc.vsel_reg = max->curr_vout_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) max->desc.vsel_mask = MAX8973_VOUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (pdata_from_dt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pdata->reg_init_data = of_get_regulator_init_data(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) client->dev.of_node, &max->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ridata = pdata->reg_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) switch (max->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) case MAX8973:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!pdata->enable_ext_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) max->desc.enable_reg = MAX8973_VOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) max->desc.enable_mask = MAX8973_VOUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) max->ops.enable = regulator_enable_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) max->ops.disable = regulator_disable_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) max->ops.is_enabled = regulator_is_enabled_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ridata && (ridata->constraints.always_on ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ridata->constraints.boot_on))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) gflags = GPIOD_OUT_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) gflags = GPIOD_OUT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) gflags |= GPIOD_FLAGS_BIT_NONEXCLUSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) gpiod = devm_gpiod_get_optional(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "maxim,enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) gflags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (IS_ERR(gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return PTR_ERR(gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (gpiod) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) config.ena_gpiod = gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) max->enable_external_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) case MAX77621:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * We do not let the core switch this regulator on/off,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * we just leave it on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) gpiod = devm_gpiod_get_optional(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "maxim,enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (IS_ERR(gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return PTR_ERR(gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) max->enable_external_control = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) max->desc.enable_reg = MAX8973_VOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) max->desc.enable_mask = MAX8973_VOUT_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) max->ops.enable = regulator_enable_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) max->ops.disable = regulator_disable_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) max->ops.is_enabled = regulator_is_enabled_regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) max->ops.set_current_limit = max8973_set_current_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) max->ops.get_current_limit = max8973_get_current_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = max8973_init_dcdc(max, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dev_err(max->dev, "Max8973 Init failed, err = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) config.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) config.init_data = pdata->reg_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) config.driver_data = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) config.of_node = client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) config.regmap = max->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) * Register the regulators
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Turn the GPIO descriptor over to the regulator core for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * lifecycle management if we pass an ena_gpiod.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (config.ena_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) devm_gpiod_unhinge(&client->dev, config.ena_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) rdev = devm_regulator_register(&client->dev, &max->desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_err(max->dev, "regulator register failed, err %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) max8973_thermal_init(max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct i2c_device_id max8973_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {.name = "max8973", .driver_data = MAX8973},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {.name = "max77621", .driver_data = MAX77621},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_DEVICE_TABLE(i2c, max8973_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static struct i2c_driver max8973_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .name = "max8973",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .of_match_table = of_max8973_match_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) .probe = max8973_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .id_table = max8973_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static int __init max8973_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return i2c_add_driver(&max8973_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) subsys_initcall(max8973_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void __exit max8973_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) i2c_del_driver(&max8973_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) module_exit(max8973_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) MODULE_DESCRIPTION("MAX8973 voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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