Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * max8660.c  --  Voltage regulation for the Maxim 8660/8661
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * based on max1586.c and wm8400-regulator.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 2009 Wolfram Sang, Pengutronix e.K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * Some info:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Datasheet: http://datasheets.maxim-ic.com/en/ds/MAX8660-MAX8661.pdf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * This chip is a bit nasty because it is a write-only device. Thus, the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * uses shadow registers to keep track of its values. The main problem appears
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * to be the initialization: When Linux boots up, we cannot know if the chip is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * in the default state or not, so we would have to pass such information in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  * platform_data. As this adds a bit of complexity to the driver, this is left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  * out for now until it is really needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * [A|S|M]DTV1 registers are currently not used, but [A|S|M]DTV2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * If the driver is feature complete, it might be worth to check if one set of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * functions for V3-V7 is sufficient. For maximum flexibility during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * development, they are separated for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #include <linux/regulator/max8660.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MAX8660_DCDC_MIN_UV	 725000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MAX8660_DCDC_MAX_UV	1800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MAX8660_DCDC_STEP	  25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MAX8660_DCDC_MAX_SEL	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MAX8660_LDO5_MIN_UV	1700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MAX8660_LDO5_MAX_UV	2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define MAX8660_LDO5_STEP	  25000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define MAX8660_LDO5_MAX_SEL	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MAX8660_LDO67_MIN_UV	1800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MAX8660_LDO67_MAX_UV	3300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MAX8660_LDO67_STEP	 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MAX8660_LDO67_MAX_SEL	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	MAX8660_OVER1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	MAX8660_OVER2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	MAX8660_VCC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	MAX8660_ADTV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	MAX8660_ADTV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	MAX8660_SDTV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	MAX8660_SDTV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	MAX8660_MDTV1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	MAX8660_MDTV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	MAX8660_L12VCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	MAX8660_FPWM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	MAX8660_N_REGS,	/* not a real register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct max8660 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 shadow_regs[MAX8660_N_REGS];		/* as chip is write only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int max8660_write(struct max8660 *max8660, u8 reg, u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	static const u8 max8660_addresses[MAX8660_N_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 0x10, 0x12, 0x20, 0x23, 0x24, 0x29, 0x2a, 0x32, 0x33, 0x39, 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u8 reg_val = (max8660->shadow_regs[reg] & mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	dev_vdbg(&max8660->client->dev, "Writing reg %02x with %02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			max8660_addresses[reg], reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	ret = i2c_smbus_write_byte_data(max8660->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			max8660_addresses[reg], reg_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		max8660->shadow_regs[reg] = reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  * DCDC functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static int max8660_dcdc_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u8 val = max8660->shadow_regs[MAX8660_OVER1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u8 mask = (rdev_get_id(rdev) == MAX8660_V3) ? 1 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static int max8660_dcdc_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u8 bit = (rdev_get_id(rdev) == MAX8660_V3) ? 1 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return max8660_write(max8660, MAX8660_OVER1, 0xff, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int max8660_dcdc_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u8 mask = (rdev_get_id(rdev) == MAX8660_V3) ? ~1 : ~4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	return max8660_write(max8660, MAX8660_OVER1, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static int max8660_dcdc_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8 reg = (rdev_get_id(rdev) == MAX8660_V3) ? MAX8660_ADTV2 : MAX8660_SDTV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u8 selector = max8660->shadow_regs[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	return selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static int max8660_dcdc_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 					unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	u8 reg, bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	reg = (rdev_get_id(rdev) == MAX8660_V3) ? MAX8660_ADTV2 : MAX8660_SDTV2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	ret = max8660_write(max8660, reg, 0, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* Select target voltage register and activate regulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	bits = (rdev_get_id(rdev) == MAX8660_V3) ? 0x03 : 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	return max8660_write(max8660, MAX8660_VCC1, 0xff, bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static struct regulator_ops max8660_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.is_enabled = max8660_dcdc_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.set_voltage_sel = max8660_dcdc_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.get_voltage_sel = max8660_dcdc_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)  * LDO5 functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int max8660_ldo5_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u8 selector = max8660->shadow_regs[MAX8660_MDTV2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	return selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static int max8660_ldo5_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 					unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	ret = max8660_write(max8660, MAX8660_MDTV2, 0, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	/* Select target voltage register and activate regulation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return max8660_write(max8660, MAX8660_VCC1, 0xff, 0xc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct regulator_ops max8660_ldo5_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.set_voltage_sel = max8660_ldo5_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.get_voltage_sel = max8660_ldo5_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * LDO67 functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int max8660_ldo67_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	u8 val = max8660->shadow_regs[MAX8660_OVER2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	u8 mask = (rdev_get_id(rdev) == MAX8660_V6) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int max8660_ldo67_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	u8 bit = (rdev_get_id(rdev) == MAX8660_V6) ? 2 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	return max8660_write(max8660, MAX8660_OVER2, 0xff, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static int max8660_ldo67_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	u8 mask = (rdev_get_id(rdev) == MAX8660_V6) ? ~2 : ~4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return max8660_write(max8660, MAX8660_OVER2, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int max8660_ldo67_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	u8 shift = (rdev_get_id(rdev) == MAX8660_V6) ? 0 : 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u8 selector = (max8660->shadow_regs[MAX8660_L12VCR] >> shift) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return selector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int max8660_ldo67_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 					 unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	struct max8660 *max8660 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	if (rdev_get_id(rdev) == MAX8660_V6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return max8660_write(max8660, MAX8660_L12VCR, 0xf0, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		return max8660_write(max8660, MAX8660_L12VCR, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				     selector << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct regulator_ops max8660_ldo67_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	.is_enabled = max8660_ldo67_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	.enable = max8660_ldo67_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	.disable = max8660_ldo67_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	.get_voltage_sel = max8660_ldo67_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	.set_voltage_sel = max8660_ldo67_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct regulator_desc max8660_reg[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.name = "V3(DCDC)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.id = MAX8660_V3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.ops = &max8660_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.n_voltages = MAX8660_DCDC_MAX_SEL + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		.min_uV = MAX8660_DCDC_MIN_UV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		.uV_step = MAX8660_DCDC_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.name = "V4(DCDC)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.id = MAX8660_V4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.ops = &max8660_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.n_voltages = MAX8660_DCDC_MAX_SEL + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		.min_uV = MAX8660_DCDC_MIN_UV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.uV_step = MAX8660_DCDC_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.name = "V5(LDO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.id = MAX8660_V5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.ops = &max8660_ldo5_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		.n_voltages = MAX8660_LDO5_MAX_SEL + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.min_uV = MAX8660_LDO5_MIN_UV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.uV_step = MAX8660_LDO5_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.name = "V6(LDO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.id = MAX8660_V6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.ops = &max8660_ldo67_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		.n_voltages = MAX8660_LDO67_MAX_SEL + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.min_uV = MAX8660_LDO67_MIN_UV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.uV_step = MAX8660_LDO67_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.name = "V7(LDO)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.id = MAX8660_V7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.ops = &max8660_ldo67_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.n_voltages = MAX8660_LDO67_MAX_SEL + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.min_uV = MAX8660_LDO67_MIN_UV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.uV_step = MAX8660_LDO67_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	MAX8660 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	MAX8661 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct of_device_id max8660_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	{ .compatible = "maxim,max8660", .data = (void *) MAX8660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	{ .compatible = "maxim,max8661", .data = (void *) MAX8661 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_DEVICE_TABLE(of, max8660_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int max8660_pdata_from_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				 struct device_node **of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				 struct max8660_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	int matched, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct max8660_subdev_data *sub;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	struct of_regulator_match rmatch[ARRAY_SIZE(max8660_reg)] = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	np = of_get_child_by_name(dev->of_node, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	if (!np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		dev_err(dev, "missing 'regulators' subnode in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	for (i = 0; i < ARRAY_SIZE(rmatch); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		rmatch[i].name = max8660_reg[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	matched = of_regulator_match(dev, np, rmatch, ARRAY_SIZE(rmatch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (matched <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		return matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	pdata->subdevs = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 				      matched,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 				      sizeof(struct max8660_subdev_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 				      GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (!pdata->subdevs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	pdata->num_subdevs = matched;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	sub = pdata->subdevs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	for (i = 0; i < matched; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 		sub->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		sub->name = rmatch[i].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		sub->platform_data = rmatch[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 		of_node[i] = rmatch[i].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		sub++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static inline int max8660_pdata_from_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 					struct device_node **of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 					struct max8660_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int max8660_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 				   const struct i2c_device_id *i2c_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	struct max8660_platform_data pdata_of, *pdata = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	struct max8660 *max8660;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	int boot_on, i, id, ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	struct device_node *of_node[MAX8660_V_END];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	unsigned long type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (dev->of_node && !pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		const struct of_device_id *id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		id = of_match_device(of_match_ptr(max8660_dt_ids), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		if (!id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		ret = max8660_pdata_from_dt(dev, of_node, &pdata_of);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		pdata = &pdata_of;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		type = (unsigned long) id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		type = i2c_id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		memset(of_node, 0, sizeof(of_node));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	if (pdata->num_subdevs > MAX8660_V_END) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		dev_err(dev, "Too many regulators found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	max8660 = devm_kzalloc(dev, sizeof(struct max8660), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (!max8660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	max8660->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (pdata->en34_is_high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		/* Simulate always on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		max8660->shadow_regs[MAX8660_OVER1] = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		/* Otherwise devices can be toggled via software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		max8660_dcdc_ops.enable = max8660_dcdc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		max8660_dcdc_ops.disable = max8660_dcdc_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	 * First, set up shadow registers to prevent glitches. As some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	 * registers are shared between regulators, everything must be properly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	 * set up for all regulators in advance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	max8660->shadow_regs[MAX8660_ADTV1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		max8660->shadow_regs[MAX8660_ADTV2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		max8660->shadow_regs[MAX8660_SDTV1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		max8660->shadow_regs[MAX8660_SDTV2] = 0x1b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	max8660->shadow_regs[MAX8660_MDTV1] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		max8660->shadow_regs[MAX8660_MDTV2] = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	for (i = 0; i < pdata->num_subdevs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		if (!pdata->subdevs[i].platform_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 			boot_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			boot_on = pdata->subdevs[i].platform_data->constraints.boot_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		switch (pdata->subdevs[i].id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		case MAX8660_V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 			if (boot_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 				max8660->shadow_regs[MAX8660_OVER1] |= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		case MAX8660_V4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 			if (boot_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 				max8660->shadow_regs[MAX8660_OVER1] |= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		case MAX8660_V5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		case MAX8660_V6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 			if (boot_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 				max8660->shadow_regs[MAX8660_OVER2] |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		case MAX8660_V7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 			if (type == MAX8661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 				dev_err(dev, "Regulator not on this chip!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 				return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 			if (boot_on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 				max8660->shadow_regs[MAX8660_OVER2] |= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 			dev_err(dev, "invalid regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 				 pdata->subdevs[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 	/* Finally register devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	for (i = 0; i < pdata->num_subdevs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 		struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		id = pdata->subdevs[i].id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 		config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		config.init_data = pdata->subdevs[i].platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		config.of_node = of_node[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		config.driver_data = max8660;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		rdev = devm_regulator_register(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 						  &max8660_reg[id], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 			dev_err(&client->dev, "failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 				max8660_reg[id].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	i2c_set_clientdata(client, max8660);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct i2c_device_id max8660_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	{ .name = "max8660", .driver_data = MAX8660 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	{ .name = "max8661", .driver_data = MAX8661 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MODULE_DEVICE_TABLE(i2c, max8660_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static struct i2c_driver max8660_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	.probe = max8660_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	.driver		= {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		.name	= "max8660",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	.id_table	= max8660_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int __init max8660_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	return i2c_add_driver(&max8660_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) subsys_initcall(max8660_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void __exit max8660_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	i2c_del_driver(&max8660_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) module_exit(max8660_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /* Module information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) MODULE_DESCRIPTION("MAXIM 8660/8661 voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) MODULE_AUTHOR("Wolfram Sang");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) MODULE_LICENSE("GPL v2");