^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Maxim MAX77620 Regulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mallikarjun Kasoju <mkasoju@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Laxman Dewangan <ldewangan@nvidia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mfd/max77620.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define max77620_rails(_name) "max77620-"#_name
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* Power Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX77620_POWER_MODE_NORMAL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MAX77620_POWER_MODE_LPM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MAX77620_POWER_MODE_GLPM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MAX77620_POWER_MODE_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* SD Slew Rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MAX77620_SD_SR_13_75 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MAX77620_SD_SR_27_5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MAX77620_SD_SR_55 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MAX77620_SD_SR_100 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) enum max77620_regulators {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MAX77620_REGULATOR_ID_SD0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MAX77620_REGULATOR_ID_SD1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MAX77620_REGULATOR_ID_SD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MAX77620_REGULATOR_ID_SD3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MAX77620_REGULATOR_ID_SD4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MAX77620_REGULATOR_ID_LDO0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MAX77620_REGULATOR_ID_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MAX77620_REGULATOR_ID_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MAX77620_REGULATOR_ID_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MAX77620_REGULATOR_ID_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MAX77620_REGULATOR_ID_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MAX77620_REGULATOR_ID_LDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MAX77620_REGULATOR_ID_LDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MAX77620_REGULATOR_ID_LDO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MAX77620_NUM_REGS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* Regulator types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) enum max77620_regulator_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MAX77620_REGULATOR_TYPE_SD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MAX77620_REGULATOR_TYPE_LDO_N,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MAX77620_REGULATOR_TYPE_LDO_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct max77620_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u8 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u8 fps_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u8 volt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u8 cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u8 power_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u8 power_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u8 remote_sense_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u8 remote_sense_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct max77620_regulator_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) int active_fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int active_fps_pd_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int active_fps_pu_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int suspend_fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) int suspend_fps_pd_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) int suspend_fps_pu_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int power_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) int ramp_rate_setting;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct max77620_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct regmap *rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct max77620_regulator_info *rinfo[MAX77620_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct max77620_regulator_pdata reg_pdata[MAX77620_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int enable_power_mode[MAX77620_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int current_power_mode[MAX77620_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) int active_fps_src[MAX77620_NUM_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define fps_src_name(fps_src) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) (fps_src == MAX77620_FPS_SRC_0 ? "FPS_SRC_0" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) fps_src == MAX77620_FPS_SRC_1 ? "FPS_SRC_1" : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) fps_src == MAX77620_FPS_SRC_2 ? "FPS_SRC_2" : "FPS_SRC_NONE")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int max77620_regulator_get_fps_src(struct max77620_regulator *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) rinfo->fps_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int max77620_regulator_set_fps_src(struct max77620_regulator *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int fps_src, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!rinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) switch (fps_src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) case MAX77620_FPS_SRC_0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) case MAX77620_FPS_SRC_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) case MAX77620_FPS_SRC_2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case MAX77620_FPS_SRC_NONE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) case MAX77620_FPS_SRC_DEF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) ret = regmap_read(pmic->rmap, rinfo->fps_addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) dev_err(pmic->dev, "Reg 0x%02x read failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) rinfo->fps_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pmic->active_fps_src[id] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dev_err(pmic->dev, "Invalid FPS %d for regulator %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) fps_src, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MAX77620_FPS_SRC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) fps_src << MAX77620_FPS_SRC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) rinfo->fps_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pmic->active_fps_src[id] = fps_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int max77620_regulator_set_fps_slots(struct max77620_regulator *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int id, bool is_suspend)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned int val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) unsigned int mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) int pu = rpdata->active_fps_pu_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int pd = rpdata->active_fps_pd_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!rinfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (is_suspend) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) pu = rpdata->suspend_fps_pu_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pd = rpdata->suspend_fps_pd_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* FPS power up period setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (pu >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) val |= (pu << MAX77620_FPS_PU_PERIOD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) mask |= MAX77620_FPS_PU_PERIOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* FPS power down period setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (pd >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) val |= (pd << MAX77620_FPS_PD_PERIOD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) mask |= MAX77620_FPS_PD_PERIOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ret = regmap_update_bits(pmic->rmap, rinfo->fps_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) rinfo->fps_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static int max77620_regulator_set_power_mode(struct max77620_regulator *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int power_mode, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u8 mask = rinfo->power_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 shift = rinfo->power_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) switch (rinfo->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) case MAX77620_REGULATOR_TYPE_SD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) addr = rinfo->cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) addr = rinfo->volt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ret = regmap_update_bits(pmic->rmap, addr, mask, power_mode << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) dev_err(pmic->dev, "Regulator %d mode set failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pmic->current_power_mode[id] = power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int max77620_regulator_get_power_mode(struct max77620_regulator *pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u8 mask = rinfo->power_mode_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u8 shift = rinfo->power_mode_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) switch (rinfo->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) case MAX77620_REGULATOR_TYPE_SD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) addr = rinfo->cfg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) addr = rinfo->volt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) ret = regmap_read(pmic->rmap, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) dev_err(pmic->dev, "Regulator %d: Reg 0x%02x read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) id, addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return (val & mask) >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int max77620_read_slew_rate(struct max77620_regulator *pmic, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) unsigned int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) int slew_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &rval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(pmic->dev, "Register 0x%02x read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) rinfo->cfg_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (rinfo->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case MAX77620_REGULATOR_TYPE_SD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) slew_rate = (rval >> MAX77620_SD_SR_SHIFT) & 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) switch (slew_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) slew_rate = 13750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) slew_rate = 27500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) slew_rate = 55000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) slew_rate = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) rinfo->desc.ramp_delay = slew_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) slew_rate = rval & 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) switch (slew_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) slew_rate = 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) slew_rate = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) rinfo->desc.ramp_delay = slew_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int max77620_set_slew_rate(struct max77620_regulator *pmic, int id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int slew_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (slew_rate <= 13750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) else if (slew_rate <= 27500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) else if (slew_rate <= 55000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) val = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) val <<= MAX77620_SD_SR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mask = MAX77620_SD_SR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (slew_rate <= 5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) mask = MAX77620_LDO_SLEW_RATE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(pmic->dev, "Regulator %d slew rate set failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int max77620_config_power_ok(struct max77620_regulator *pmic, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct max77620_chip *chip = dev_get_drvdata(pmic->dev->parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) switch (chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) case MAX20024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (rpdata->power_ok >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (rinfo->type == MAX77620_REGULATOR_TYPE_SD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) mask = MAX20024_SD_CFG1_MPOK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) mask = MAX20024_LDO_CFG2_MPOK_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val = rpdata->power_ok ? mask : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(pmic->dev, "Reg 0x%02x update failed %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) rinfo->cfg_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int max77620_init_pmic(struct max77620_regulator *pmic, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) max77620_config_power_ok(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Update power mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = max77620_regulator_get_power_mode(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) pmic->current_power_mode[id] = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (rpdata->active_fps_src == MAX77620_FPS_SRC_DEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ret = max77620_regulator_get_fps_src(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) rpdata->active_fps_src = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* If rails are externally control of FPS then enable it always. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (rpdata->active_fps_src == MAX77620_FPS_SRC_NONE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) ret = max77620_regulator_set_power_mode(pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) pmic->enable_power_mode[id], id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (pmic->current_power_mode[id] !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pmic->enable_power_mode[id]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = max77620_regulator_set_power_mode(pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) pmic->enable_power_mode[id], id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ret = max77620_regulator_set_fps_src(pmic, rpdata->active_fps_src, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = max77620_regulator_set_fps_slots(pmic, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (rpdata->ramp_rate_setting) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = max77620_set_slew_rate(pmic, id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) rpdata->ramp_rate_setting);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int max77620_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return max77620_regulator_set_power_mode(pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) pmic->enable_power_mode[id], id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static int max77620_regulator_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return max77620_regulator_set_power_mode(pmic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) MAX77620_POWER_MODE_DISABLE, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int max77620_regulator_is_enabled(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (pmic->active_fps_src[id] != MAX77620_FPS_SRC_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) ret = max77620_regulator_get_power_mode(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret != MAX77620_POWER_MODE_DISABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int max77620_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) bool fpwm = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) fpwm = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) power_mode = MAX77620_POWER_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) power_mode = MAX77620_POWER_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) power_mode = MAX77620_POWER_MODE_LPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dev_err(pmic->dev, "Regulator %d mode %d is invalid\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) id, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (rinfo->type != MAX77620_REGULATOR_TYPE_SD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) goto skip_fpwm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) val = (fpwm) ? MAX77620_SD_FPWM_MASK : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = regmap_update_bits(pmic->rmap, rinfo->cfg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) MAX77620_SD_FPWM_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev_err(pmic->dev, "Reg 0x%02x update failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) rinfo->cfg_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) rpdata->current_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) skip_fpwm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = max77620_regulator_set_power_mode(pmic, power_mode, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) pmic->enable_power_mode[id] = power_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static unsigned int max77620_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct max77620_regulator_info *rinfo = pmic->rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) int fpwm = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int pm_mode, reg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = max77620_regulator_get_power_mode(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) pm_mode = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (rinfo->type == MAX77620_REGULATOR_TYPE_SD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ret = regmap_read(pmic->rmap, rinfo->cfg_addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(pmic->dev, "Reg 0x%02x read failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) rinfo->cfg_addr, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) fpwm = !!(val & MAX77620_SD_FPWM_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) switch (pm_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) case MAX77620_POWER_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) case MAX77620_POWER_MODE_DISABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (fpwm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) reg_mode = REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) reg_mode = REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) case MAX77620_POWER_MODE_LPM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case MAX77620_POWER_MODE_GLPM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) reg_mode = REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return reg_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int max77620_regulator_set_ramp_delay(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct max77620_regulator *pmic = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* Device specific ramp rate setting tells that platform has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) * different ramp rate from advertised value. In this case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * do not configure anything and just return success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (rpdata->ramp_rate_setting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return max77620_set_slew_rate(pmic, id, ramp_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int max77620_of_parse_cb(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) const struct regulator_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct regulator_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct max77620_regulator *pmic = config->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct max77620_regulator_pdata *rpdata = &pmic->reg_pdata[desc->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u32 pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ret = of_property_read_u32(np, "maxim,active-fps-source", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) rpdata->active_fps_src = (!ret) ? pval : MAX77620_FPS_SRC_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ret = of_property_read_u32(np, "maxim,active-fps-power-up-slot", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) rpdata->active_fps_pu_slot = (!ret) ? pval : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ret = of_property_read_u32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) np, "maxim,active-fps-power-down-slot", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) rpdata->active_fps_pd_slot = (!ret) ? pval : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = of_property_read_u32(np, "maxim,suspend-fps-source", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) rpdata->suspend_fps_src = (!ret) ? pval : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = of_property_read_u32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) np, "maxim,suspend-fps-power-up-slot", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rpdata->suspend_fps_pu_slot = (!ret) ? pval : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) ret = of_property_read_u32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) np, "maxim,suspend-fps-power-down-slot", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) rpdata->suspend_fps_pd_slot = (!ret) ? pval : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret = of_property_read_u32(np, "maxim,power-ok-control", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) rpdata->power_ok = pval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) rpdata->power_ok = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ret = of_property_read_u32(np, "maxim,ramp-rate-setting", &pval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) rpdata->ramp_rate_setting = (!ret) ? pval : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return max77620_init_pmic(pmic, desc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static const struct regulator_ops max77620_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .is_enabled = max77620_regulator_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .enable = max77620_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .disable = max77620_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .set_mode = max77620_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .get_mode = max77620_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .set_ramp_delay = max77620_regulator_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .set_active_discharge = regulator_set_active_discharge_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MAX77620_SD_CNF2_ROVS_EN_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define RAIL_SD(_id, _name, _sname, _volt_mask, _min_uV, _max_uV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) _step_uV, _rs_add, _rs_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) [MAX77620_REGULATOR_ID_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .type = MAX77620_REGULATOR_TYPE_SD, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .volt_addr = MAX77620_REG_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .cfg_addr = MAX77620_REG_##_id##_CFG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .fps_addr = MAX77620_REG_FPS_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .remote_sense_addr = _rs_add, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .remote_sense_mask = MAX77620_SD_CNF2_ROVS_EN_##_rs_mask, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .power_mode_mask = MAX77620_SD_POWER_MODE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .power_mode_shift = MAX77620_SD_POWER_MODE_SHIFT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .name = max77620_rails(_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .of_match = of_match_ptr(#_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .of_parse_cb = max77620_of_parse_cb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .supply_name = _sname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .id = MAX77620_REGULATOR_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .ops = &max77620_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .min_uV = _min_uV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .uV_step = _step_uV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) .enable_time = 500, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .vsel_mask = MAX77620_##_volt_mask##_VOLT_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .vsel_reg = MAX77620_REG_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .active_discharge_off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .active_discharge_on = MAX77620_SD_CFG1_ADE_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .active_discharge_mask = MAX77620_SD_CFG1_ADE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .active_discharge_reg = MAX77620_REG_##_id##_CFG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define RAIL_LDO(_id, _name, _sname, _type, _min_uV, _max_uV, _step_uV) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [MAX77620_REGULATOR_ID_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .type = MAX77620_REGULATOR_TYPE_LDO_##_type, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .volt_addr = MAX77620_REG_##_id##_CFG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .cfg_addr = MAX77620_REG_##_id##_CFG2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .fps_addr = MAX77620_REG_FPS_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .remote_sense_addr = 0xFF, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .power_mode_mask = MAX77620_LDO_POWER_MODE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .power_mode_shift = MAX77620_LDO_POWER_MODE_SHIFT, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .desc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .name = max77620_rails(_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .of_match = of_match_ptr(#_name), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .of_parse_cb = max77620_of_parse_cb, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .supply_name = _sname, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .id = MAX77620_REGULATOR_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) .ops = &max77620_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) .n_voltages = ((_max_uV - _min_uV) / _step_uV) + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) .min_uV = _min_uV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) .uV_step = _step_uV, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) .enable_time = 500, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .vsel_mask = MAX77620_LDO_VOLT_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .vsel_reg = MAX77620_REG_##_id##_CFG, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .active_discharge_off = 0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .active_discharge_on = MAX77620_LDO_CFG2_ADE_ENABLE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) .active_discharge_mask = MAX77620_LDO_CFG2_ADE_MASK, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) .active_discharge_reg = MAX77620_REG_##_id##_CFG2, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static struct max77620_regulator_info max77620_regs_info[MAX77620_NUM_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 1400000, 12500, 0x22, SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 1550000, 12500, 0x22, SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct max77620_regulator_info max20024_regs_info[MAX77620_NUM_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) RAIL_SD(SD0, sd0, "in-sd0", SD0, 800000, 1587500, 12500, 0x22, SD0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) RAIL_SD(SD1, sd1, "in-sd1", SD1, 600000, 3387500, 12500, 0x22, SD1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static struct max77620_regulator_info max77663_regs_info[MAX77620_NUM_REGS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) RAIL_SD(SD0, sd0, "in-sd0", SD0, 600000, 3387500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) RAIL_SD(SD1, sd1, "in-sd1", SD1, 800000, 1587500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) RAIL_SD(SD2, sd2, "in-sd2", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) RAIL_SD(SD3, sd3, "in-sd3", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) RAIL_SD(SD4, sd4, "in-sd4", SDX, 600000, 3787500, 12500, 0xFF, NONE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) RAIL_LDO(LDO0, ldo0, "in-ldo0-1", N, 800000, 2375000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) RAIL_LDO(LDO1, ldo1, "in-ldo0-1", N, 800000, 2375000, 25000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) RAIL_LDO(LDO2, ldo2, "in-ldo2", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) RAIL_LDO(LDO3, ldo3, "in-ldo3-5", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) RAIL_LDO(LDO4, ldo4, "in-ldo4-6", P, 800000, 1587500, 12500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) RAIL_LDO(LDO5, ldo5, "in-ldo3-5", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) RAIL_LDO(LDO6, ldo6, "in-ldo4-6", P, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) RAIL_LDO(LDO7, ldo7, "in-ldo7-8", N, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) RAIL_LDO(LDO8, ldo8, "in-ldo7-8", N, 800000, 3950000, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int max77620_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct max77620_chip *max77620_chip = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct max77620_regulator_info *rinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct max77620_regulator *pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) pmic = devm_kzalloc(dev, sizeof(*pmic), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!pmic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) platform_set_drvdata(pdev, pmic);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) pmic->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pmic->rmap = max77620_chip->rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!dev->of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev->of_node = pdev->dev.parent->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) switch (max77620_chip->chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) case MAX77620:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) rinfo = max77620_regs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) case MAX20024:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) rinfo = max20024_regs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case MAX77663:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) rinfo = max77663_regs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) config.regmap = pmic->rmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) config.driver_data = pmic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * Set of_node_reuse flag to prevent driver core from attempting to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * claim any pinmux resources already claimed by the parent device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * Otherwise PMIC driver will fail to re-probe.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) for (id = 0; id < MAX77620_NUM_REGS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct regulator_desc *rdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if ((max77620_chip->chip_id == MAX77620) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) (id == MAX77620_REGULATOR_ID_SD4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) rdesc = &rinfo[id].desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) pmic->rinfo[id] = &rinfo[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) pmic->enable_power_mode[id] = MAX77620_POWER_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pmic->reg_pdata[id].active_fps_src = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pmic->reg_pdata[id].active_fps_pd_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) pmic->reg_pdata[id].active_fps_pu_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) pmic->reg_pdata[id].suspend_fps_src = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) pmic->reg_pdata[id].suspend_fps_pd_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) pmic->reg_pdata[id].suspend_fps_pu_slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pmic->reg_pdata[id].power_ok = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pmic->reg_pdata[id].ramp_rate_setting = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = max77620_read_slew_rate(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) rdev = devm_regulator_register(dev, rdesc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev_err(dev, "Regulator registration %s failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) rdesc->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int max77620_regulator_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct max77620_regulator *pmic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct max77620_regulator_pdata *reg_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) for (id = 0; id < MAX77620_NUM_REGS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) reg_pdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) max77620_regulator_set_fps_slots(pmic, id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (reg_pdata->suspend_fps_src < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) max77620_regulator_set_fps_src(pmic, reg_pdata->suspend_fps_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int max77620_regulator_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct max77620_regulator *pmic = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct max77620_regulator_pdata *reg_pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) for (id = 0; id < MAX77620_NUM_REGS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) reg_pdata = &pmic->reg_pdata[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) max77620_config_power_ok(pmic, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) max77620_regulator_set_fps_slots(pmic, id, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (reg_pdata->active_fps_src < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) max77620_regulator_set_fps_src(pmic, reg_pdata->active_fps_src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static const struct dev_pm_ops max77620_regulator_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) SET_SYSTEM_SLEEP_PM_OPS(max77620_regulator_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) max77620_regulator_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static const struct platform_device_id max77620_regulator_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) { .name = "max77620-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) { .name = "max20024-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) { .name = "max77663-pmic", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) MODULE_DEVICE_TABLE(platform, max77620_regulator_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static struct platform_driver max77620_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .probe = max77620_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .id_table = max77620_regulator_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .name = "max77620-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .pm = &max77620_regulator_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) module_platform_driver(max77620_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MODULE_DESCRIPTION("MAX77620/MAX20024 regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) MODULE_AUTHOR("Mallikarjun Kasoju <mkasoju@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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