Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2016 Gateworks Corporation, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define DRIVER_NAME		"ltc3676"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* LTC3676 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LTC3676_BUCK1     0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LTC3676_BUCK2     0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LTC3676_BUCK3     0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LTC3676_BUCK4     0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LTC3676_LDOA      0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LTC3676_LDOB      0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LTC3676_SQD1      0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LTC3676_SQD2      0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LTC3676_CNTRL     0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LTC3676_DVB1A     0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LTC3676_DVB1B     0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LTC3676_DVB2A     0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LTC3676_DVB2B     0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LTC3676_DVB3A     0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LTC3676_DVB3B     0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LTC3676_DVB4A     0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LTC3676_DVB4B     0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LTC3676_MSKIRQ    0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LTC3676_MSKPG     0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LTC3676_USER      0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LTC3676_IRQSTAT   0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LTC3676_PGSTATL   0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LTC3676_PGSTATRT  0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define LTC3676_HRST      0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LTC3676_CLIRQ     0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LTC3676_DVBxA_REF_SELECT	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define LTC3676_DVBxB_PGOOD_MASK	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LTC3676_IRQSTAT_PGOOD_TIMEOUT	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LTC3676_IRQSTAT_UNDERVOLT_WARN	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LTC3676_IRQSTAT_UNDERVOLT_FAULT	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LTC3676_IRQSTAT_THERMAL_WARN	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LTC3676_IRQSTAT_THERMAL_FAULT	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) enum ltc3676_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	LTC3676_SW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	LTC3676_SW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	LTC3676_SW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	LTC3676_SW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	LTC3676_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	LTC3676_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	LTC3676_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	LTC3676_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	LTC3676_NUM_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct ltc3676 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct regulator_desc regulator_descs[LTC3676_NUM_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct regulator_dev *regulators[LTC3676_NUM_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) static int ltc3676_set_suspend_voltage(struct regulator_dev *rdev, int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	struct ltc3676 *ltc3676 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct device *dev = ltc3676->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	int dcdc = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	dev_dbg(dev, "%s id=%d uV=%d\n", __func__, dcdc, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	sel = regulator_map_voltage_linear(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	/* DVBB register follows right after the corresponding DVBA register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	return regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				  rdev->desc->vsel_mask, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) static int ltc3676_set_suspend_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				    unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct ltc3676 *ltc3676= rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	struct device *dev = ltc3676->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	int mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	int dcdc = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	dev_dbg(dev, "%s id=%d mode=%d\n", __func__, dcdc, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	mask = LTC3676_DVBxA_REF_SELECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		val = 0; /* select DVBxA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 		val = LTC3676_DVBxA_REF_SELECT; /* select DVBxB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		dev_warn(&rdev->dev, "%s: regulator mode: 0x%x not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			 rdev->desc->name, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 				  mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static int ltc3676_set_voltage_sel(struct regulator_dev *rdev, unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	struct ltc3676 *ltc3676 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	struct device *dev = ltc3676->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	int ret, dcdc = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	dev_dbg(dev, "%s id=%d selector=%d\n", __func__, dcdc, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	ret = regmap_update_bits(ltc3676->regmap, rdev->desc->vsel_reg + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 				 LTC3676_DVBxB_PGOOD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				 LTC3676_DVBxB_PGOOD_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return regulator_set_voltage_sel_regmap(rdev, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline unsigned int ltc3676_scale(unsigned int uV, u32 r1, u32 r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	uint64_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (uV == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	tmp = (uint64_t)uV * r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	do_div(tmp, r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	return uV + (unsigned int)tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int ltc3676_of_parse_cb(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			       const struct regulator_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			       struct regulator_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct ltc3676 *ltc3676 = config->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct regulator_desc *rdesc = &ltc3676->regulator_descs[desc->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	u32 r[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* LDO3 has a fixed output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	if (desc->id == LTC3676_LDO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		dev_err(ltc3676->dev, "Failed to parse voltage divider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	rdesc->min_uV = ltc3676_scale(desc->min_uV, r[0], r[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	rdesc->uV_step = ltc3676_scale(desc->uV_step, r[0], r[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	rdesc->fixed_uV = ltc3676_scale(desc->fixed_uV, r[0], r[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* SW1, SW2, SW3, SW4 linear 0.8V-3.3V with scalar via R1/R2 feeback res */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct regulator_ops ltc3676_linear_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	.set_voltage_sel = ltc3676_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	.set_suspend_voltage = ltc3676_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	.set_suspend_mode = ltc3676_set_suspend_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* LDO1 always on fixed 0.8V-3.3V via scalar via R1/R2 feeback res */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct regulator_ops ltc3676_fixed_standby_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* LDO2, LDO3 fixed (LDO2 has external scalar via R1/R2 feedback res) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct regulator_ops ltc3676_fixed_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LTC3676_REG(_id, _name, _ops, en_reg, en_bit, dvba_reg, dvb_mask)   \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	[LTC3676_ ## _id] = {                                        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		.name = #_name,                                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		.of_match = of_match_ptr(#_name),              \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		.regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		.of_parse_cb = ltc3676_of_parse_cb,            \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		.n_voltages = (dvb_mask) + 1,                  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		.min_uV = (dvba_reg) ? 412500 : 0,             \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		.uV_step = (dvba_reg) ? 12500 : 0,             \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.ramp_delay = (dvba_reg) ? 800 : 0,            \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.fixed_uV = (dvb_mask) ? 0 : 725000,           \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.ops = &ltc3676_ ## _ops ## _regulator_ops,    \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.type = REGULATOR_VOLTAGE,                     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		.id = LTC3676_ ## _id,                         \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		.owner = THIS_MODULE,                          \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		.vsel_reg = (dvba_reg),                        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		.vsel_mask = (dvb_mask),                       \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		.enable_reg = (en_reg),                        \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		.enable_mask = (1 << en_bit),                  \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LTC3676_LINEAR_REG(_id, _name, _en, _dvba)                     \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	LTC3676_REG(_id, _name, linear,                                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		    LTC3676_ ## _en, 7,                                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		    LTC3676_ ## _dvba, 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LTC3676_FIXED_REG(_id, _name, _en_reg, _en_bit)                \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	LTC3676_REG(_id, _name, fixed, LTC3676_ ## _en_reg, _en_bit, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) static const struct regulator_desc ltc3676_regulators[LTC3676_NUM_REGULATORS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	LTC3676_LINEAR_REG(SW1, sw1, BUCK1, DVB1A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	LTC3676_LINEAR_REG(SW2, sw2, BUCK2, DVB2A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	LTC3676_LINEAR_REG(SW3, sw3, BUCK3, DVB3A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	LTC3676_LINEAR_REG(SW4, sw4, BUCK4, DVB4A),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	LTC3676_REG(LDO1, ldo1, fixed_standby, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	LTC3676_FIXED_REG(LDO2, ldo2, LDOA, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	LTC3676_FIXED_REG(LDO3, ldo3, LDOA, 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	LTC3676_FIXED_REG(LDO4, ldo4, LDOB, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static bool ltc3676_readable_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	case LTC3676_BUCK1 ... LTC3676_IRQSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	case LTC3676_HRST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	case LTC3676_CLIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static bool ltc3676_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case LTC3676_IRQSTAT ... LTC3676_PGSTATRT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static const struct regmap_config ltc3676_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	.writeable_reg = ltc3676_readable_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	.readable_reg = ltc3676_readable_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.volatile_reg = ltc3676_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.max_register = LTC3676_CLIRQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static irqreturn_t ltc3676_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct ltc3676 *ltc3676 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct device *dev = ltc3676->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	unsigned int i, irqstat, event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	regmap_read(ltc3676->regmap, LTC3676_IRQSTAT, &irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	dev_dbg(dev, "irq%d irqstat=0x%02x\n", irq, irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (irqstat & LTC3676_IRQSTAT_THERMAL_WARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		dev_warn(dev, "Over-temperature Warning\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		event = REGULATOR_EVENT_OVER_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		for (i = 0; i < LTC3676_NUM_REGULATORS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			regulator_notifier_call_chain(ltc3676->regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 						      event, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	if (irqstat & LTC3676_IRQSTAT_UNDERVOLT_WARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		dev_info(dev, "Undervoltage Warning\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		event = REGULATOR_EVENT_UNDER_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 		for (i = 0; i < LTC3676_NUM_REGULATORS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 			regulator_notifier_call_chain(ltc3676->regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 						      event, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* Clear warning condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	regmap_write(ltc3676->regmap, LTC3676_CLIRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static int ltc3676_regulator_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	struct regulator_init_data *init_data = dev_get_platdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct regulator_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	struct ltc3676 *ltc3676;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	ltc3676 = devm_kzalloc(dev, sizeof(*ltc3676), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (!ltc3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	i2c_set_clientdata(client, ltc3676);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	ltc3676->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	descs = ltc3676->regulator_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	memcpy(descs, ltc3676_regulators, sizeof(ltc3676_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	descs[LTC3676_LDO3].fixed_uV = 1800000; /* LDO3 is fixed 1.8V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	ltc3676->regmap = devm_regmap_init_i2c(client, &ltc3676_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	if (IS_ERR(ltc3676->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		ret = PTR_ERR(ltc3676->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		dev_err(dev, "failed to initialize regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	for (i = 0; i < LTC3676_NUM_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		struct regulator_desc *desc = &ltc3676->regulator_descs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		if (init_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 			config.init_data = &init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		config.driver_data = ltc3676;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		ltc3676->regulators[i] = devm_regulator_register(dev, desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 								 &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		if (IS_ERR(ltc3676->regulators[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 			ret = PTR_ERR(ltc3676->regulators[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			dev_err(dev, "failed to register regulator %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 				desc->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	regmap_write(ltc3676->regmap, LTC3676_CLIRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 		ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 						ltc3676_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 						client->name, ltc3676);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 			dev_err(dev, "Failed to request IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const struct i2c_device_id ltc3676_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	{ "ltc3676" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) MODULE_DEVICE_TABLE(i2c, ltc3676_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static const struct of_device_id __maybe_unused ltc3676_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	{ .compatible = "lltc,ltc3676" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) MODULE_DEVICE_TABLE(of, ltc3676_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static struct i2c_driver ltc3676_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		.of_match_table = of_match_ptr(ltc3676_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	.probe_new = ltc3676_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	.id_table = ltc3676_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) module_i2c_driver(ltc3676_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MODULE_AUTHOR("Tim Harvey <tharvey@gateworks.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3676");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) MODULE_LICENSE("GPL v2");