Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Linear Technology LTC3589,LTC3589-1 regulator support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (c) 2014 Philipp Zabel <p.zabel@pengutronix.de>, Pengutronix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define DRIVER_NAME		"ltc3589"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define LTC3589_IRQSTAT		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define LTC3589_SCR1		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define LTC3589_OVEN		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LTC3589_SCR2		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LTC3589_PGSTAT		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LTC3589_VCCR		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LTC3589_CLIRQ		0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LTC3589_B1DTV1		0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LTC3589_B1DTV2		0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LTC3589_VRRCR		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LTC3589_B2DTV1		0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LTC3589_B2DTV2		0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LTC3589_B3DTV1		0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LTC3589_B3DTV2		0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LTC3589_L2DTV1		0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LTC3589_L2DTV2		0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LTC3589_IRQSTAT_PGOOD_TIMEOUT	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LTC3589_IRQSTAT_UNDERVOLT_WARN	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LTC3589_IRQSTAT_UNDERVOLT_FAULT	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LTC3589_IRQSTAT_THERMAL_WARN	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LTC3589_IRQSTAT_THERMAL_FAULT	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LTC3589_OVEN_SW1		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define LTC3589_OVEN_SW2		BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LTC3589_OVEN_SW3		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define LTC3589_OVEN_BB_OUT		BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define LTC3589_OVEN_LDO2		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LTC3589_OVEN_LDO3		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LTC3589_OVEN_LDO4		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LTC3589_OVEN_SW_CTRL		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LTC3589_VCCR_SW1_GO		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define LTC3589_VCCR_SW2_GO		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LTC3589_VCCR_SW3_GO		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define LTC3589_VCCR_LDO2_GO		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) enum ltc3589_variant {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	LTC3589,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	LTC3589_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	LTC3589_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) enum ltc3589_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	LTC3589_SW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	LTC3589_SW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	LTC3589_SW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	LTC3589_BB_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	LTC3589_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	LTC3589_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	LTC3589_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	LTC3589_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	LTC3589_NUM_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) struct ltc3589 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	enum ltc3589_variant variant;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct regulator_desc regulator_descs[LTC3589_NUM_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct regulator_dev *regulators[LTC3589_NUM_REGULATORS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static const int ltc3589_ldo4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	2800000, 2500000, 1800000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) static const int ltc3589_12_ldo4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	1200000, 1800000, 2500000, 3200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static int ltc3589_set_ramp_delay(struct regulator_dev *rdev, int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	int sel, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (unlikely(ramp_delay <= 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* VRRCR slew rate offsets are the same as VCCR go bit offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	shift = ffs(rdev->desc->apply_bit) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	/* The slew rate can be set to 0.88, 1.75, 3.5, or 7 mV/uS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	for (sel = 0; sel < 4; sel++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if ((880 << sel) >= ramp_delay) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			return regmap_update_bits(ltc3589->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 						  LTC3589_VRRCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 						  0x3 << shift, sel << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static int ltc3589_set_suspend_voltage(struct regulator_dev *rdev, int uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	sel = regulator_map_voltage_linear(rdev, uV, uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (sel < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	/* DTV2 register follows right after the corresponding DTV1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return regmap_update_bits(ltc3589->regmap, rdev->desc->vsel_reg + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				  rdev->desc->vsel_mask, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static int ltc3589_set_suspend_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 				    unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	struct ltc3589 *ltc3589 = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	int mask, bit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	/* VCCR reference selects are right next to the VCCR go bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	mask = rdev->desc->apply_bit << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (mode == REGULATOR_MODE_STANDBY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		bit = mask;	/* Select DTV2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	mask |= rdev->desc->apply_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	bit |= rdev->desc->apply_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	return regmap_update_bits(ltc3589->regmap, LTC3589_VCCR, mask, bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* SW1, SW2, SW3, LDO2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct regulator_ops ltc3589_linear_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	.set_ramp_delay = ltc3589_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	.set_suspend_voltage = ltc3589_set_suspend_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	.set_suspend_mode = ltc3589_set_suspend_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* BB_OUT, LDO3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct regulator_ops ltc3589_fixed_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* LDO1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static const struct regulator_ops ltc3589_fixed_standby_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* LDO4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct regulator_ops ltc3589_table_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static inline unsigned int ltc3589_scale(unsigned int uV, u32 r1, u32 r2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	uint64_t tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (uV == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	tmp = (uint64_t)uV * r1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	do_div(tmp, r2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	return uV + (unsigned int)tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static int ltc3589_of_parse_cb(struct device_node *np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			       const struct regulator_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 			       struct regulator_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	struct ltc3589 *ltc3589 = config->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	struct regulator_desc *rdesc = &ltc3589->regulator_descs[desc->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	u32 r[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	/* Parse feedback voltage dividers. LDO3 and LDO4 don't have them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (desc->id >= LTC3589_LDO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	ret = of_property_read_u32_array(np, "lltc,fb-voltage-divider", r, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dev_err(ltc3589->dev, "Failed to parse voltage divider: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	if (!r[0] || !r[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	rdesc->min_uV = ltc3589_scale(desc->min_uV, r[0], r[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	rdesc->uV_step = ltc3589_scale(desc->uV_step, r[0], r[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	rdesc->fixed_uV = ltc3589_scale(desc->fixed_uV, r[0], r[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define LTC3589_REG(_name, _of_name, _ops, en_bit, dtv1_reg, dtv_mask, go_bit)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	[LTC3589_ ## _name] = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		.name = #_name,						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 		.of_match = of_match_ptr(#_of_name),			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		.regulators_node = of_match_ptr("regulators"),		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		.of_parse_cb = ltc3589_of_parse_cb,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		.n_voltages = (dtv_mask) + 1,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.min_uV = (go_bit) ? 362500 : 0,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		.uV_step = (go_bit) ? 12500 : 0,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 		.ramp_delay = (go_bit) ? 1750 : 0,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 		.fixed_uV = (dtv_mask) ? 0 : 800000,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		.ops = &ltc3589_ ## _ops ## _regulator_ops,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		.type = REGULATOR_VOLTAGE,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		.id = LTC3589_ ## _name,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		.owner = THIS_MODULE,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		.vsel_reg = (dtv1_reg),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 		.vsel_mask = (dtv_mask),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 		.apply_reg = (go_bit) ? LTC3589_VCCR : 0,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		.apply_bit = (go_bit),					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 		.enable_reg = (en_bit) ? LTC3589_OVEN : 0,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 		.enable_mask = (en_bit),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define LTC3589_LINEAR_REG(_name, _of_name, _dtv1)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	LTC3589_REG(_name, _of_name, linear, LTC3589_OVEN_ ## _name,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		    LTC3589_ ## _dtv1, 0x1f,				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		    LTC3589_VCCR_ ## _name ## _GO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define LTC3589_FIXED_REG(_name, _of_name)				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	LTC3589_REG(_name, _of_name, fixed, LTC3589_OVEN_ ## _name, 0, 0, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static const struct regulator_desc ltc3589_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	LTC3589_LINEAR_REG(SW1, sw1, B1DTV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	LTC3589_LINEAR_REG(SW2, sw2, B2DTV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	LTC3589_LINEAR_REG(SW3, sw3, B3DTV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	LTC3589_FIXED_REG(BB_OUT, bb-out),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	LTC3589_REG(LDO1, ldo1, fixed_standby, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	LTC3589_LINEAR_REG(LDO2, ldo2, L2DTV1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	LTC3589_FIXED_REG(LDO3, ldo3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	LTC3589_REG(LDO4, ldo4, table, LTC3589_OVEN_LDO4, LTC3589_L2DTV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		    0x60, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static bool ltc3589_writeable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	case LTC3589_IRQSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	case LTC3589_SCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	case LTC3589_OVEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	case LTC3589_SCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	case LTC3589_VCCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	case LTC3589_CLIRQ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	case LTC3589_B1DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	case LTC3589_B1DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	case LTC3589_VRRCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	case LTC3589_B2DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	case LTC3589_B2DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	case LTC3589_B3DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	case LTC3589_B3DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	case LTC3589_L2DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case LTC3589_L2DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static bool ltc3589_readable_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	case LTC3589_IRQSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	case LTC3589_SCR1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	case LTC3589_OVEN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	case LTC3589_SCR2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	case LTC3589_PGSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	case LTC3589_VCCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	case LTC3589_B1DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	case LTC3589_B1DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	case LTC3589_VRRCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	case LTC3589_B2DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	case LTC3589_B2DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	case LTC3589_B3DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	case LTC3589_B3DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	case LTC3589_L2DTV1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	case LTC3589_L2DTV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static bool ltc3589_volatile_reg(struct device *dev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	switch (reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	case LTC3589_IRQSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	case LTC3589_PGSTAT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	case LTC3589_VCCR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const struct reg_default ltc3589_reg_defaults[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	{ LTC3589_SCR1,   0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	{ LTC3589_OVEN,   0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	{ LTC3589_SCR2,   0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	{ LTC3589_VCCR,   0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	{ LTC3589_B1DTV1, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	{ LTC3589_B1DTV2, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	{ LTC3589_VRRCR,  0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	{ LTC3589_B2DTV1, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	{ LTC3589_B2DTV2, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	{ LTC3589_B3DTV1, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	{ LTC3589_B3DTV2, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	{ LTC3589_L2DTV1, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	{ LTC3589_L2DTV2, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct regmap_config ltc3589_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	.writeable_reg = ltc3589_writeable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	.readable_reg = ltc3589_readable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	.volatile_reg = ltc3589_volatile_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	.max_register = LTC3589_L2DTV2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.reg_defaults = ltc3589_reg_defaults,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	.num_reg_defaults = ARRAY_SIZE(ltc3589_reg_defaults),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.use_single_read = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.use_single_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static irqreturn_t ltc3589_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	struct ltc3589 *ltc3589 = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	unsigned int i, irqstat, event;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	regmap_read(ltc3589->regmap, LTC3589_IRQSTAT, &irqstat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (irqstat & LTC3589_IRQSTAT_THERMAL_WARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		event = REGULATOR_EVENT_OVER_TEMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 		for (i = 0; i < LTC3589_NUM_REGULATORS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 			regulator_notifier_call_chain(ltc3589->regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 						      event, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	if (irqstat & LTC3589_IRQSTAT_UNDERVOLT_WARN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		event = REGULATOR_EVENT_UNDER_VOLTAGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		for (i = 0; i < LTC3589_NUM_REGULATORS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			regulator_notifier_call_chain(ltc3589->regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 						      event, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	/* Clear warning condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	regmap_write(ltc3589->regmap, LTC3589_CLIRQ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static int ltc3589_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	struct regulator_desc *descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	struct ltc3589 *ltc3589;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	ltc3589 = devm_kzalloc(dev, sizeof(*ltc3589), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	if (!ltc3589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	i2c_set_clientdata(client, ltc3589);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	if (client->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		ltc3589->variant = (enum ltc3589_variant)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			of_device_get_match_data(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		ltc3589->variant = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	ltc3589->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	descs = ltc3589->regulator_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	memcpy(descs, ltc3589_regulators, sizeof(ltc3589_regulators));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	if (ltc3589->variant == LTC3589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		descs[LTC3589_LDO3].fixed_uV = 1800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		descs[LTC3589_LDO4].volt_table = ltc3589_ldo4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		descs[LTC3589_LDO3].fixed_uV = 2800000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 		descs[LTC3589_LDO4].volt_table = ltc3589_12_ldo4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	ltc3589->regmap = devm_regmap_init_i2c(client, &ltc3589_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	if (IS_ERR(ltc3589->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		ret = PTR_ERR(ltc3589->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		dev_err(dev, "failed to initialize regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	for (i = 0; i < LTC3589_NUM_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		struct regulator_desc *desc = &ltc3589->regulator_descs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		config.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		config.driver_data = ltc3589;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 		ltc3589->regulators[i] = devm_regulator_register(dev, desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 								 &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		if (IS_ERR(ltc3589->regulators[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 			ret = PTR_ERR(ltc3589->regulators[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 			dev_err(dev, "failed to register regulator %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 				desc->name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	if (client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		ret = devm_request_threaded_irq(dev, client->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 						ltc3589_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 						IRQF_TRIGGER_LOW | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 						client->name, ltc3589);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			dev_err(dev, "Failed to request IRQ: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const struct i2c_device_id ltc3589_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	{ "ltc3589",   LTC3589   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	{ "ltc3589-1", LTC3589_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	{ "ltc3589-2", LTC3589_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) MODULE_DEVICE_TABLE(i2c, ltc3589_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) static const struct of_device_id __maybe_unused ltc3589_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.compatible = "lltc,ltc3589",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		.data = (void *)LTC3589,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		.compatible = "lltc,ltc3589-1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.data = (void *)LTC3589_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		.compatible = "lltc,ltc3589-2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.data = (void *)LTC3589_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_DEVICE_TABLE(of, ltc3589_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct i2c_driver ltc3589_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 		.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 		.of_match_table = of_match_ptr(ltc3589_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	.probe = ltc3589_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	.id_table = ltc3589_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) module_i2c_driver(ltc3589_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MODULE_AUTHOR("Philipp Zabel <p.zabel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_DESCRIPTION("Regulator driver for Linear Technology LTC3589(-1,2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_LICENSE("GPL v2");