^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI LP8788 MFD - ldo regulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/mfd/lp8788.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LP8788_EN_LDO_A 0x0D /* DLDO 1 ~ 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LP8788_EN_LDO_B 0x0E /* DLDO 9 ~ 12, ALDO 1 ~ 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LP8788_EN_LDO_C 0x0F /* ALDO 5 ~ 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LP8788_EN_SEL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP8788_DLDO1_VOUT 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP8788_DLDO2_VOUT 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP8788_DLDO3_VOUT 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP8788_DLDO4_VOUT 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP8788_DLDO5_VOUT 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP8788_DLDO6_VOUT 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP8788_DLDO7_VOUT 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP8788_DLDO8_VOUT 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP8788_DLDO9_VOUT 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP8788_DLDO10_VOUT 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP8788_DLDO11_VOUT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP8788_DLDO12_VOUT 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP8788_ALDO1_VOUT 0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP8788_ALDO2_VOUT 0x3B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP8788_ALDO3_VOUT 0x3C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP8788_ALDO4_VOUT 0x3D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP8788_ALDO5_VOUT 0x3E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP8788_ALDO6_VOUT 0x3F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP8788_ALDO7_VOUT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP8788_ALDO8_VOUT 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP8788_ALDO9_VOUT 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP8788_ALDO10_VOUT 0x43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP8788_DLDO1_TIMESTEP 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* mask/shift bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP8788_EN_DLDO1_M BIT(0) /* Addr 0Dh ~ 0Fh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP8788_EN_DLDO2_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP8788_EN_DLDO3_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LP8788_EN_DLDO4_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP8788_EN_DLDO5_M BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP8788_EN_DLDO6_M BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP8788_EN_DLDO7_M BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP8788_EN_DLDO8_M BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP8788_EN_DLDO9_M BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP8788_EN_DLDO10_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP8788_EN_DLDO11_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP8788_EN_DLDO12_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP8788_EN_ALDO1_M BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP8788_EN_ALDO2_M BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP8788_EN_ALDO3_M BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP8788_EN_ALDO4_M BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LP8788_EN_ALDO5_M BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP8788_EN_ALDO6_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP8788_EN_ALDO7_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP8788_EN_ALDO8_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LP8788_EN_ALDO9_M BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LP8788_EN_ALDO10_M BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LP8788_EN_SEL_DLDO911_M BIT(0) /* Addr 10h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP8788_EN_SEL_DLDO7_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LP8788_EN_SEL_ALDO7_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LP8788_EN_SEL_ALDO5_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LP8788_EN_SEL_ALDO234_M BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LP8788_EN_SEL_ALDO1_M BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LP8788_VOUT_5BIT_M 0x1F /* Addr 2Eh ~ 43h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LP8788_VOUT_4BIT_M 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LP8788_VOUT_3BIT_M 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define LP8788_VOUT_1BIT_M 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LP8788_STARTUP_TIME_M 0xF8 /* Addr 44h ~ 59h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LP8788_STARTUP_TIME_S 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ENABLE_TIME_USEC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) enum lp8788_ldo_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) DLDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) DLDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DLDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) DLDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) DLDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) DLDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) DLDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) DLDO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) DLDO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) DLDO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) DLDO11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) DLDO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) ALDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ALDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ALDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ALDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ALDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ALDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) ALDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ALDO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ALDO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ALDO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct lp8788_ldo {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct lp8788 *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regulator_dev *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gpio_desc *ena_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* DLDO 1, 2, 3, 9 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const int lp8788_dldo1239_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 2600000, 2700000, 2800000, 2900000, 3000000, 2850000, 2850000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* DLDO 4 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static const int lp8788_dldo4_vtbl[] = { 1800000, 3000000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* DLDO 5, 7, 8 and ALDO 6 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const int lp8788_dldo578_aldo6_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 2600000, 2700000, 2800000, 2900000, 3000000, 3000000, 3000000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* DLDO 6 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static const int lp8788_dldo6_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 3000000, 3100000, 3200000, 3300000, 3400000, 3500000, 3600000, 3600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* DLDO 10, 11 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const int lp8788_dldo1011_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 1100000, 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* ALDO 1 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static const int lp8788_aldo1_vtbl[] = { 1800000, 2850000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* ALDO 7 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const int lp8788_aldo7_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 1200000, 1300000, 1400000, 1500000, 1600000, 1700000, 1800000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int lp8788_ldo_enable_time(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct lp8788_ldo *ldo = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) enum lp8788_ldo_id id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 val, addr = LP8788_DLDO1_TIMESTEP + id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (lp8788_read_byte(ldo->lp, addr, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ENABLE_TIME_USEC * val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct regulator_ops lp8788_ldo_voltage_table_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .enable_time = lp8788_ldo_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct regulator_ops lp8788_ldo_voltage_fixed_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .enable_time = lp8788_ldo_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct regulator_desc lp8788_dldo_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .name = "dldo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .id = DLDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .volt_table = lp8788_dldo1239_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .vsel_reg = LP8788_DLDO1_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .vsel_mask = LP8788_VOUT_5BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .enable_mask = LP8788_EN_DLDO1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .name = "dldo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .id = DLDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .volt_table = lp8788_dldo1239_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .vsel_reg = LP8788_DLDO2_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .vsel_mask = LP8788_VOUT_5BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .enable_mask = LP8788_EN_DLDO2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .name = "dldo3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .id = DLDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .volt_table = lp8788_dldo1239_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .vsel_reg = LP8788_DLDO3_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .vsel_mask = LP8788_VOUT_5BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .enable_mask = LP8788_EN_DLDO3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .name = "dldo4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .id = DLDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .n_voltages = ARRAY_SIZE(lp8788_dldo4_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .volt_table = lp8788_dldo4_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) .vsel_reg = LP8788_DLDO4_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) .vsel_mask = LP8788_VOUT_1BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) .enable_mask = LP8788_EN_DLDO4_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .name = "dldo5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .id = DLDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .volt_table = lp8788_dldo578_aldo6_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .vsel_reg = LP8788_DLDO5_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .vsel_mask = LP8788_VOUT_4BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .enable_mask = LP8788_EN_DLDO5_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .name = "dldo6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .id = DLDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .n_voltages = ARRAY_SIZE(lp8788_dldo6_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .volt_table = lp8788_dldo6_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) .vsel_reg = LP8788_DLDO6_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .vsel_mask = LP8788_VOUT_3BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .enable_mask = LP8788_EN_DLDO6_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .name = "dldo7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .id = DLDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .volt_table = lp8788_dldo578_aldo6_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .vsel_reg = LP8788_DLDO7_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .vsel_mask = LP8788_VOUT_4BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .enable_mask = LP8788_EN_DLDO7_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .name = "dldo8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .id = DLDO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .volt_table = lp8788_dldo578_aldo6_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .vsel_reg = LP8788_DLDO8_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .vsel_mask = LP8788_VOUT_4BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .enable_reg = LP8788_EN_LDO_A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .enable_mask = LP8788_EN_DLDO8_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .name = "dldo9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .id = DLDO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .n_voltages = ARRAY_SIZE(lp8788_dldo1239_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .volt_table = lp8788_dldo1239_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .vsel_reg = LP8788_DLDO9_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .vsel_mask = LP8788_VOUT_5BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .enable_mask = LP8788_EN_DLDO9_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .name = "dldo10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .id = DLDO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .volt_table = lp8788_dldo1011_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .vsel_reg = LP8788_DLDO10_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .vsel_mask = LP8788_VOUT_4BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .enable_mask = LP8788_EN_DLDO10_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = "dldo11",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .id = DLDO11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .n_voltages = ARRAY_SIZE(lp8788_dldo1011_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .volt_table = lp8788_dldo1011_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .vsel_reg = LP8788_DLDO11_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .vsel_mask = LP8788_VOUT_4BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .enable_mask = LP8788_EN_DLDO11_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .name = "dldo12",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .id = DLDO12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .enable_mask = LP8788_EN_DLDO12_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .min_uV = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) static const struct regulator_desc lp8788_aldo_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .name = "aldo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .id = ALDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .n_voltages = ARRAY_SIZE(lp8788_aldo1_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .volt_table = lp8788_aldo1_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .vsel_reg = LP8788_ALDO1_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .vsel_mask = LP8788_VOUT_1BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .enable_mask = LP8788_EN_ALDO1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .name = "aldo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .id = ALDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .enable_mask = LP8788_EN_ALDO2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) .min_uV = 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) .name = "aldo3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .id = ALDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .enable_mask = LP8788_EN_ALDO3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .min_uV = 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .name = "aldo4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .id = ALDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .enable_reg = LP8788_EN_LDO_B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .enable_mask = LP8788_EN_ALDO4_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .min_uV = 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .name = "aldo5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .id = ALDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .enable_reg = LP8788_EN_LDO_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .enable_mask = LP8788_EN_ALDO5_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .min_uV = 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .name = "aldo6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .id = ALDO6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .n_voltages = ARRAY_SIZE(lp8788_dldo578_aldo6_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .volt_table = lp8788_dldo578_aldo6_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .vsel_reg = LP8788_ALDO6_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .vsel_mask = LP8788_VOUT_4BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .enable_reg = LP8788_EN_LDO_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .enable_mask = LP8788_EN_ALDO6_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .name = "aldo7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .id = ALDO7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .ops = &lp8788_ldo_voltage_table_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .n_voltages = ARRAY_SIZE(lp8788_aldo7_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .volt_table = lp8788_aldo7_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .vsel_reg = LP8788_ALDO7_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .vsel_mask = LP8788_VOUT_3BIT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .enable_reg = LP8788_EN_LDO_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .enable_mask = LP8788_EN_ALDO7_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .name = "aldo8",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .id = ALDO8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .enable_reg = LP8788_EN_LDO_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .enable_mask = LP8788_EN_ALDO8_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .min_uV = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .name = "aldo9",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .id = ALDO9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .enable_reg = LP8788_EN_LDO_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .enable_mask = LP8788_EN_ALDO9_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .min_uV = 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .name = "aldo10",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .id = ALDO10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .ops = &lp8788_ldo_voltage_fixed_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .n_voltages = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .enable_reg = LP8788_EN_LDO_C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .enable_mask = LP8788_EN_ALDO10_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .min_uV = 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) static int lp8788_config_ldo_enable_mode(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct lp8788_ldo *ldo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) enum lp8788_ldo_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct lp8788 *lp = ldo->lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) enum lp8788_ext_ldo_en_id enable_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static const u8 en_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) [EN_ALDO1] = LP8788_EN_SEL_ALDO1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) [EN_ALDO234] = LP8788_EN_SEL_ALDO234_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) [EN_ALDO5] = LP8788_EN_SEL_ALDO5_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) [EN_ALDO7] = LP8788_EN_SEL_ALDO7_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) [EN_DLDO7] = LP8788_EN_SEL_DLDO7_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) [EN_DLDO911] = LP8788_EN_SEL_DLDO911_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case DLDO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) enable_id = EN_DLDO7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case DLDO9:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case DLDO11:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) enable_id = EN_DLDO911;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) case ALDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enable_id = EN_ALDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) case ALDO2 ... ALDO4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) enable_id = EN_ALDO234;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) case ALDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enable_id = EN_ALDO5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case ALDO7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) enable_id = EN_ALDO7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * Do not use devm* here: the regulator core takes over the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * lifecycle management of the GPIO descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * FIXME: check default mode for GPIO here: high or low?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ldo->ena_gpiod = gpiod_get_index_optional(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) enable_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) GPIOD_OUT_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) GPIOD_FLAGS_BIT_NONEXCLUSIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (IS_ERR(ldo->ena_gpiod))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return PTR_ERR(ldo->ena_gpiod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* if no GPIO for ldo pin, then set default enable mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!ldo->ena_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) goto set_default_ldo_enable_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) set_default_ldo_enable_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return lp8788_update_bits(lp, LP8788_EN_SEL, en_mask[enable_id], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int lp8788_dldo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct lp8788_ldo *ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct regulator_config cfg = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) if (!ldo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ldo->lp = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ret = lp8788_config_ldo_enable_mode(pdev, ldo, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (ldo->ena_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cfg.ena_gpiod = ldo->ena_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cfg.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cfg.init_data = lp->pdata ? lp->pdata->dldo_data[id] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cfg.driver_data = ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) cfg.regmap = lp->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) rdev = devm_regulator_register(&pdev->dev, &lp8788_dldo_desc[id], &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) dev_err(&pdev->dev, "DLDO%d regulator register err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ldo->regulator = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) platform_set_drvdata(pdev, ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static struct platform_driver lp8788_dldo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .probe = lp8788_dldo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .name = LP8788_DEV_DLDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int lp8788_aldo_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) int id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct lp8788_ldo *ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct regulator_config cfg = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ldo = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_ldo), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (!ldo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ldo->lp = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = lp8788_config_ldo_enable_mode(pdev, ldo, id + ALDO1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (ldo->ena_gpiod)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) cfg.ena_gpiod = ldo->ena_gpiod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) cfg.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) cfg.init_data = lp->pdata ? lp->pdata->aldo_data[id] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cfg.driver_data = ldo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) cfg.regmap = lp->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) rdev = devm_regulator_register(&pdev->dev, &lp8788_aldo_desc[id], &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(&pdev->dev, "ALDO%d regulator register err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) ldo->regulator = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) platform_set_drvdata(pdev, ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static struct platform_driver lp8788_aldo_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .probe = lp8788_aldo_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .name = LP8788_DEV_ALDO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static struct platform_driver * const drivers[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &lp8788_dldo_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) &lp8788_aldo_driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int __init lp8788_ldo_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) subsys_initcall(lp8788_ldo_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static void __exit lp8788_ldo_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) module_exit(lp8788_ldo_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) MODULE_DESCRIPTION("TI LP8788 LDO Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) MODULE_AUTHOR("Milo Kim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MODULE_ALIAS("platform:lp8788-dldo");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) MODULE_ALIAS("platform:lp8788-aldo");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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