^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * TI LP8788 MFD - buck regulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mfd/lp8788.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LP8788_EN_BUCK 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define LP8788_BUCK_DVS_SEL 0x1D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LP8788_BUCK1_VOUT0 0x1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LP8788_BUCK1_VOUT1 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP8788_BUCK1_VOUT2 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP8788_BUCK1_VOUT3 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP8788_BUCK2_VOUT0 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP8788_BUCK2_VOUT1 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP8788_BUCK2_VOUT2 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP8788_BUCK2_VOUT3 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define LP8788_BUCK3_VOUT 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP8788_BUCK4_VOUT 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP8788_BUCK1_TIMESTEP 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP8788_BUCK_PWM 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* mask/shift bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP8788_EN_BUCK1_M BIT(0) /* Addr 0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP8788_EN_BUCK2_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP8788_EN_BUCK3_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP8788_EN_BUCK4_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP8788_BUCK1_DVS_SEL_M 0x04 /* Addr 1Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP8788_BUCK1_DVS_M 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP8788_BUCK1_DVS_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP8788_BUCK2_DVS_SEL_M 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP8788_BUCK2_DVS_M 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP8788_BUCK2_DVS_S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP8788_BUCK1_DVS_I2C BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP8788_BUCK2_DVS_I2C BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP8788_BUCK1_DVS_PIN (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP8788_BUCK2_DVS_PIN (0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP8788_VOUT_M 0x1F /* Addr 1Eh ~ 27h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP8788_STARTUP_TIME_M 0xF8 /* Addr 28h ~ 2Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LP8788_STARTUP_TIME_S 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP8788_FPWM_BUCK1_M BIT(0) /* Addr 2Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP8788_FPWM_BUCK1_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LP8788_FPWM_BUCK2_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define LP8788_FPWM_BUCK2_S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP8788_FPWM_BUCK3_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP8788_FPWM_BUCK3_S 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP8788_FPWM_BUCK4_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP8788_FPWM_BUCK4_S 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define INVALID_ADDR 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP8788_FORCE_PWM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LP8788_AUTO_PWM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PIN_LOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PIN_HIGH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ENABLE_TIME_USEC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BUCK_FPWM_MASK(x) (1 << (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BUCK_FPWM_SHIFT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) enum lp8788_dvs_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) DVS_LOW = GPIOF_OUT_INIT_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DVS_HIGH = GPIOF_OUT_INIT_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) enum lp8788_dvs_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) EXTPIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum lp8788_buck_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) BUCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) BUCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) BUCK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct lp8788_buck {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct lp8788 *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct regulator_dev *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) void *dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* BUCK 1 ~ 4 voltage ranges */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static const struct linear_range buck_volt_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) REGULATOR_LINEAR_RANGE(500000, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) REGULATOR_LINEAR_RANGE(800000, 1, 25, 50000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static void lp8788_buck1_set_dvs(struct lp8788_buck *buck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct lp8788_buck1_dvs *dvs = (struct lp8788_buck1_dvs *)buck->dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum lp8788_dvs_state pinstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (!dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) pinstate = dvs->vsel == DVS_SEL_V0 ? DVS_LOW : DVS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (gpio_is_valid(dvs->gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) gpio_set_value(dvs->gpio, pinstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void lp8788_buck2_set_dvs(struct lp8788_buck *buck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct lp8788_buck2_dvs *dvs = (struct lp8788_buck2_dvs *)buck->dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) enum lp8788_dvs_state pin1, pin2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (!dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) switch (dvs->vsel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) case DVS_SEL_V0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pin1 = DVS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) pin2 = DVS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) case DVS_SEL_V1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) pin1 = DVS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) pin2 = DVS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) case DVS_SEL_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pin1 = DVS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) pin2 = DVS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) case DVS_SEL_V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pin1 = DVS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) pin2 = DVS_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (gpio_is_valid(dvs->gpio[0]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) gpio_set_value(dvs->gpio[0], pin1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (gpio_is_valid(dvs->gpio[1]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) gpio_set_value(dvs->gpio[1], pin2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static void lp8788_set_dvs(struct lp8788_buck *buck, enum lp8788_buck_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) case BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) lp8788_buck1_set_dvs(buck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) case BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) lp8788_buck2_set_dvs(buck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static enum lp8788_dvs_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) lp8788_get_buck_dvs_ctrl_mode(struct lp8788_buck *buck, enum lp8788_buck_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) case BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) mask = LP8788_BUCK1_DVS_SEL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) case BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mask = LP8788_BUCK2_DVS_SEL_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return REGISTER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) return val & mask ? REGISTER : EXTPIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static bool lp8788_is_valid_buck_addr(u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) switch (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) case LP8788_BUCK1_VOUT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) case LP8788_BUCK1_VOUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) case LP8788_BUCK1_VOUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) case LP8788_BUCK1_VOUT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case LP8788_BUCK2_VOUT0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) case LP8788_BUCK2_VOUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) case LP8788_BUCK2_VOUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) case LP8788_BUCK2_VOUT3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static u8 lp8788_select_buck_vout_addr(struct lp8788_buck *buck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) enum lp8788_buck_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) enum lp8788_dvs_mode mode = lp8788_get_buck_dvs_ctrl_mode(buck, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct lp8788_buck1_dvs *b1_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct lp8788_buck2_dvs *b2_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u8 val, idx, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) int pin1, pin2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) case BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (mode == EXTPIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) b1_dvs = (struct lp8788_buck1_dvs *)buck->dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (!b1_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) idx = gpio_get_value(b1_dvs->gpio) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) idx = (val & LP8788_BUCK1_DVS_M) >> LP8788_BUCK1_DVS_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) addr = LP8788_BUCK1_VOUT0 + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) case BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (mode == EXTPIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) b2_dvs = (struct lp8788_buck2_dvs *)buck->dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (!b2_dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) pin1 = gpio_get_value(b2_dvs->gpio[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) pin2 = gpio_get_value(b2_dvs->gpio[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (pin1 == PIN_LOW && pin2 == PIN_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) else if (pin1 == PIN_LOW && pin2 == PIN_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) idx = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) else if (pin1 == PIN_HIGH && pin2 == PIN_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) idx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) idx = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) lp8788_read_byte(buck->lp, LP8788_BUCK_DVS_SEL, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) idx = (val & LP8788_BUCK2_DVS_M) >> LP8788_BUCK2_DVS_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) addr = LP8788_BUCK2_VOUT0 + idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return INVALID_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static int lp8788_buck12_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct lp8788_buck *buck = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum lp8788_buck_id id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (buck->dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) lp8788_set_dvs(buck, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) addr = lp8788_select_buck_vout_addr(buck, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (!lp8788_is_valid_buck_addr(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return lp8788_update_bits(buck->lp, addr, LP8788_VOUT_M, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int lp8788_buck12_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct lp8788_buck *buck = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum lp8788_buck_id id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u8 val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) addr = lp8788_select_buck_vout_addr(buck, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!lp8788_is_valid_buck_addr(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) ret = lp8788_read_byte(buck->lp, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return val & LP8788_VOUT_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static int lp8788_buck_enable_time(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct lp8788_buck *buck = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) enum lp8788_buck_id id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u8 val, addr = LP8788_BUCK1_TIMESTEP + id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (lp8788_read_byte(buck->lp, addr, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) val = (val & LP8788_STARTUP_TIME_M) >> LP8788_STARTUP_TIME_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return ENABLE_TIME_USEC * val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int lp8788_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct lp8788_buck *buck = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) enum lp8788_buck_id id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) mask = BUCK_FPWM_MASK(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val = LP8788_FORCE_PWM << BUCK_FPWM_SHIFT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) val = LP8788_AUTO_PWM << BUCK_FPWM_SHIFT(id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return lp8788_update_bits(buck->lp, LP8788_BUCK_PWM, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static unsigned int lp8788_buck_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct lp8788_buck *buck = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) enum lp8788_buck_id id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ret = lp8788_read_byte(buck->lp, LP8788_BUCK_PWM, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return val & BUCK_FPWM_MASK(id) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static const struct regulator_ops lp8788_buck12_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .set_voltage_sel = lp8788_buck12_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .get_voltage_sel = lp8788_buck12_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .enable_time = lp8788_buck_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .set_mode = lp8788_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .get_mode = lp8788_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static const struct regulator_ops lp8788_buck34_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .enable_time = lp8788_buck_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) .set_mode = lp8788_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) .get_mode = lp8788_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static const struct regulator_desc lp8788_buck_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) .name = "buck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) .id = BUCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) .ops = &lp8788_buck12_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) .n_voltages = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) .linear_ranges = buck_volt_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) .enable_reg = LP8788_EN_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) .enable_mask = LP8788_EN_BUCK1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .name = "buck2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .id = BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .ops = &lp8788_buck12_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .n_voltages = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .linear_ranges = buck_volt_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .enable_reg = LP8788_EN_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .enable_mask = LP8788_EN_BUCK2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .name = "buck3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .id = BUCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .ops = &lp8788_buck34_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .n_voltages = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) .linear_ranges = buck_volt_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .vsel_reg = LP8788_BUCK3_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .vsel_mask = LP8788_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .enable_reg = LP8788_EN_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .enable_mask = LP8788_EN_BUCK3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .name = "buck4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .id = BUCK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .ops = &lp8788_buck34_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .n_voltages = 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .linear_ranges = buck_volt_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .n_linear_ranges = ARRAY_SIZE(buck_volt_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .vsel_reg = LP8788_BUCK4_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .vsel_mask = LP8788_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .enable_reg = LP8788_EN_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .enable_mask = LP8788_EN_BUCK4_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int lp8788_dvs_gpio_request(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct lp8788_buck *buck,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) enum lp8788_buck_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct lp8788_platform_data *pdata = buck->lp->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) char *b1_name = "LP8788_B1_DVS";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) char *b2_name[] = { "LP8788_B2_DVS1", "LP8788_B2_DVS2" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int i, gpio, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) gpio = pdata->buck1_dvs->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = devm_gpio_request_one(&pdev->dev, gpio, DVS_LOW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) b1_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) buck->dvs = pdata->buck1_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) for (i = 0; i < LP8788_NUM_BUCK2_DVS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) gpio = pdata->buck2_dvs->gpio[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = devm_gpio_request_one(&pdev->dev, gpio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) DVS_LOW, b2_name[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) buck->dvs = pdata->buck2_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int lp8788_init_dvs(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct lp8788_buck *buck, enum lp8788_buck_id id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct lp8788_platform_data *pdata = buck->lp->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 mask[] = { LP8788_BUCK1_DVS_SEL_M, LP8788_BUCK2_DVS_SEL_M };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u8 val[] = { LP8788_BUCK1_DVS_PIN, LP8788_BUCK2_DVS_PIN };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u8 default_dvs_mode[] = { LP8788_BUCK1_DVS_I2C, LP8788_BUCK2_DVS_I2C };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* no dvs for buck3, 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (id > BUCK2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* no dvs platform data, then dvs will be selected by I2C registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto set_default_dvs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if ((id == BUCK1 && !pdata->buck1_dvs) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) (id == BUCK2 && !pdata->buck2_dvs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) goto set_default_dvs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (lp8788_dvs_gpio_request(pdev, buck, id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) goto set_default_dvs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return lp8788_update_bits(buck->lp, LP8788_BUCK_DVS_SEL, mask[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) set_default_dvs_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return lp8788_update_bits(buck->lp, LP8788_BUCK_DVS_SEL, mask[id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) default_dvs_mode[id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int lp8788_buck_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct lp8788 *lp = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int id = pdev->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct lp8788_buck *buck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct regulator_config cfg = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (id >= LP8788_NUM_BUCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) buck = devm_kzalloc(&pdev->dev, sizeof(struct lp8788_buck), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (!buck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) buck->lp = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = lp8788_init_dvs(pdev, buck, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cfg.dev = pdev->dev.parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cfg.init_data = lp->pdata ? lp->pdata->buck_data[id] : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) cfg.driver_data = buck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cfg.regmap = lp->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) rdev = devm_regulator_register(&pdev->dev, &lp8788_buck_desc[id], &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(&pdev->dev, "BUCK%d regulator register err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) id + 1, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) buck->regulator = rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) platform_set_drvdata(pdev, buck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) static struct platform_driver lp8788_buck_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .probe = lp8788_buck_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .name = LP8788_DEV_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int __init lp8788_buck_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return platform_driver_register(&lp8788_buck_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) subsys_initcall(lp8788_buck_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static void __exit lp8788_buck_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) platform_driver_unregister(&lp8788_buck_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) module_exit(lp8788_buck_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_DESCRIPTION("TI LP8788 BUCK Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) MODULE_AUTHOR("Milo Kim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) MODULE_ALIAS("platform:lp8788-buck");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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