Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Regulator driver for LP87565 PMIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2017 Texas Instruments Incorporated - https://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/mfd/lp87565.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define LP87565_REGULATOR(_name, _id, _of, _ops, _n, _vr, _vm,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 			  _er, _em, _ev, _delay, _lr, _cr)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 	[_id] = {							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 		.desc = {						\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 			.name			= _name,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 			.supply_name		= _of "-in",		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 			.id			= _id,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 			.of_match		= of_match_ptr(_of),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 			.regulators_node	= of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 			.ops			= &_ops,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 			.n_voltages		= _n,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 			.type			= REGULATOR_VOLTAGE,	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 			.owner			= THIS_MODULE,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 			.vsel_reg		= _vr,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 			.vsel_mask		= _vm,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 			.enable_reg		= _er,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 			.enable_mask		= _em,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			.enable_val		= _ev,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 			.ramp_delay		= _delay,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 			.linear_ranges		= _lr,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 			.n_linear_ranges	= ARRAY_SIZE(_lr),	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 			.curr_table = lp87565_buck_uA,			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 			.n_current_limits = ARRAY_SIZE(lp87565_buck_uA),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 			.csel_reg = (_cr),				\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			.csel_mask = LP87565_BUCK_CTRL_2_ILIM,		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 		},							\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 		.ctrl2_reg = _cr,					\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct lp87565_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	unsigned int ctrl2_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) static const struct lp87565_regulator regulators[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) static const struct linear_range buck0_1_2_3_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	REGULATOR_LINEAR_RANGE(600000, 0xA, 0x17, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	REGULATOR_LINEAR_RANGE(735000, 0x18, 0x9d, 5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	REGULATOR_LINEAR_RANGE(1420000, 0x9e, 0xff, 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) static const unsigned int lp87565_buck_ramp_delay[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	30000, 15000, 10000, 7500, 3800, 1900, 940, 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* LP87565 BUCK current limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) static const unsigned int lp87565_buck_uA[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	1500000, 2000000, 2500000, 3000000, 3500000, 4000000, 4500000, 5000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) static int lp87565_buck_set_ramp_delay(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 				       int ramp_delay)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	if (ramp_delay <= 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 		reg = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	else if (ramp_delay <= 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		reg = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	else if (ramp_delay <= 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		reg = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	else if (ramp_delay <= 3800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		reg = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	else if (ramp_delay <= 7500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		reg = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	else if (ramp_delay <= 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		reg = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	else if (ramp_delay <= 15000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		reg = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ret = regmap_update_bits(rdev->regmap, regulators[id].ctrl2_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 				 LP87565_BUCK_CTRL_2_SLEW_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				 reg << __ffs(LP87565_BUCK_CTRL_2_SLEW_RATE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		dev_err(&rdev->dev, "SLEW RATE write failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	rdev->constraints->ramp_delay = lp87565_buck_ramp_delay[reg];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Conservatively give a 15% margin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	rdev->constraints->ramp_delay =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 				rdev->constraints->ramp_delay * 85 / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Operations permitted on BUCKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const struct regulator_ops lp87565_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	.is_enabled		= regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	.enable			= regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	.disable		= regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	.set_voltage_sel	= regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	.list_voltage		= regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	.map_voltage		= regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.set_ramp_delay		= lp87565_buck_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.set_current_limit	= regulator_set_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.get_current_limit	= regulator_get_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static const struct lp87565_regulator regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	LP87565_REGULATOR("BUCK0", LP87565_BUCK_0, "buck0", lp87565_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			  256, LP87565_REG_BUCK0_VOUT, LP87565_BUCK_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 			  LP87565_REG_BUCK0_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			  LP87565_BUCK_CTRL_1_EN, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	LP87565_REGULATOR("BUCK1", LP87565_BUCK_1, "buck1", lp87565_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			  256, LP87565_REG_BUCK1_VOUT, LP87565_BUCK_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			  LP87565_REG_BUCK1_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			  LP87565_BUCK_CTRL_1_EN, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK1_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	LP87565_REGULATOR("BUCK2", LP87565_BUCK_2, "buck2", lp87565_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			  256, LP87565_REG_BUCK2_VOUT, LP87565_BUCK_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 			  LP87565_REG_BUCK2_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 			  LP87565_BUCK_CTRL_1_EN, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK2_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	LP87565_REGULATOR("BUCK3", LP87565_BUCK_3, "buck3", lp87565_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 			  256, LP87565_REG_BUCK3_VOUT, LP87565_BUCK_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			  LP87565_REG_BUCK3_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			  LP87565_BUCK_CTRL_1_EN, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK3_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	LP87565_REGULATOR("BUCK10", LP87565_BUCK_10, "buck10", lp87565_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			  256, LP87565_REG_BUCK0_VOUT, LP87565_BUCK_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 			  LP87565_REG_BUCK0_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	LP87565_REGULATOR("BUCK23", LP87565_BUCK_23, "buck23", lp87565_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			  256, LP87565_REG_BUCK2_VOUT, LP87565_BUCK_VSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			  LP87565_REG_BUCK2_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			  LP87565_BUCK_CTRL_1_EN, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK2_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	LP87565_REGULATOR("BUCK3210", LP87565_BUCK_3210, "buck3210",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			  lp87565_buck_ops, 256, LP87565_REG_BUCK0_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			  LP87565_BUCK_VSET, LP87565_REG_BUCK0_CTRL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			  LP87565_BUCK_CTRL_1_EN_PIN_CTRL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			  LP87565_BUCK_CTRL_1_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			  LP87565_BUCK_CTRL_1_FPWM_MP_0_2, 3230,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			  buck0_1_2_3_ranges, LP87565_REG_BUCK0_CTRL_2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static int lp87565_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	struct lp87565 *lp87565 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int i, min_idx, max_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	platform_set_drvdata(pdev, lp87565);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	config.dev->of_node = lp87565->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	config.driver_data = lp87565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	config.regmap = lp87565->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	switch (lp87565->dev_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	case LP87565_DEVICE_TYPE_LP87565_Q1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		min_idx = LP87565_BUCK_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		max_idx = LP87565_BUCK_23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	case LP87565_DEVICE_TYPE_LP87561_Q1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		min_idx = LP87565_BUCK_3210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 		max_idx = LP87565_BUCK_3210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		min_idx = LP87565_BUCK_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		max_idx = LP87565_BUCK_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	for (i = min_idx; i <= max_idx; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		rdev = devm_regulator_register(&pdev->dev, &regulators[i].desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 					       &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			dev_err(lp87565->dev, "failed to register %s regulator\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 				pdev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static const struct platform_device_id lp87565_regulator_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	{ "lp87565-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ "lp87565-q1-regulator", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_DEVICE_TABLE(platform, lp87565_regulator_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static struct platform_driver lp87565_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		.name = "lp87565-pmic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	.probe = lp87565_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	.id_table = lp87565_regulator_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) module_platform_driver(lp87565_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) MODULE_AUTHOR("J Keerthy <j-keerthy@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MODULE_DESCRIPTION("LP87565 voltage regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_LICENSE("GPL v2");