Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * LP8755 High Performance Power Management Unit : System Interface Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * (based on rev. 0.26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Daniel(Geon Si) Jeong <daniel.jeong@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/platform_data/lp8755.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define LP8755_REG_BUCK0	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LP8755_REG_BUCK1	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LP8755_REG_BUCK2	0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LP8755_REG_BUCK3	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LP8755_REG_BUCK4	0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LP8755_REG_BUCK5	0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LP8755_REG_MAX		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LP8755_BUCK_EN_M	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LP8755_BUCK_LINEAR_OUT_MAX	0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LP8755_BUCK_VOUT_M	0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) struct lp8755_mphase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	int nreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	int buck_num[LP8755_BUCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) struct lp8755_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct lp8755_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	unsigned int irqmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int mphase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct regulator_dev *rdev[LP8755_BUCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static int lp8755_buck_enable_time(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	enum lp8755_bucks id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	ret = regmap_read(rdev->regmap, 0x12 + id, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 		dev_err(&rdev->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	return (regval & 0xff) * 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) static int lp8755_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	unsigned int regbval = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	enum lp8755_bucks id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct lp8755_chip *pchip = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		/* forced pwm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 		regbval = (0x01 << id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 		/* enable automatic pwm/pfm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		ret = regmap_update_bits(rdev->regmap, 0x08 + id, 0x20, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	case REGULATOR_MODE_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		/* enable automatic pwm/pfm/lppfm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		ret = regmap_update_bits(rdev->regmap, 0x08 + id, 0x20, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		ret = regmap_update_bits(rdev->regmap, 0x10, 0x01, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 			goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		dev_err(pchip->dev, "Not supported buck mode %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		/* forced pwm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		regbval = (0x01 << id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	ret = regmap_update_bits(rdev->regmap, 0x06, 0x01 << id, regbval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	dev_err(&rdev->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) static unsigned int lp8755_buck_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	enum lp8755_bucks id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	ret = regmap_read(rdev->regmap, 0x06, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* mode fast means forced pwm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (regval & (0x01 << id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return REGULATOR_MODE_FAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	ret = regmap_read(rdev->regmap, 0x08 + id, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	/* mode idle means automatic pwm/pfm/lppfm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	if (regval & 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		return REGULATOR_MODE_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	/* mode normal means automatic pwm/pfm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	dev_err(&rdev->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int lp8755_buck_set_ramp(struct regulator_dev *rdev, int ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	unsigned int regval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	enum lp8755_bucks id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	/* uV/us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	switch (ramp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	case 0 ... 230:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		regval = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	case 231 ... 470:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		regval = 0x06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	case 471 ... 940:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		regval = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	case 941 ... 1900:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		regval = 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	case 1901 ... 3800:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		regval = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	case 3801 ... 7500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 		regval = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	case 7501 ... 15000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		regval = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	case 15001 ... 30000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		regval = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		dev_err(&rdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			"Not supported ramp value %d %s\n", ramp, __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	ret = regmap_update_bits(rdev->regmap, 0x07 + id, 0x07, regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	dev_err(&rdev->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static const struct regulator_ops lp8755_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.map_voltage = regulator_map_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.enable_time = lp8755_buck_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.set_mode = lp8755_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	.get_mode = lp8755_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	.set_ramp_delay = lp8755_buck_set_ramp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define lp8755_rail(_id) "lp8755_buck"#_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define lp8755_buck_init(_id)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	.constraints = {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		.name = lp8755_rail(_id),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		.min_uV = 500000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		.max_uV = 1675000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct regulator_init_data lp8755_reg_default[LP8755_BUCK_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	[LP8755_BUCK0] = lp8755_buck_init(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	[LP8755_BUCK1] = lp8755_buck_init(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	[LP8755_BUCK2] = lp8755_buck_init(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	[LP8755_BUCK3] = lp8755_buck_init(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	[LP8755_BUCK4] = lp8755_buck_init(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	[LP8755_BUCK5] = lp8755_buck_init(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) static const struct lp8755_mphase mphase_buck[MPHASE_CONF_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	{ 3, { LP8755_BUCK0, LP8755_BUCK3, LP8755_BUCK5 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	{ 6, { LP8755_BUCK0, LP8755_BUCK1, LP8755_BUCK2, LP8755_BUCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	       LP8755_BUCK4, LP8755_BUCK5 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	{ 5, { LP8755_BUCK0, LP8755_BUCK2, LP8755_BUCK3, LP8755_BUCK4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	       LP8755_BUCK5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	{ 4, { LP8755_BUCK0, LP8755_BUCK3, LP8755_BUCK4, LP8755_BUCK5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	{ 3, { LP8755_BUCK0, LP8755_BUCK4, LP8755_BUCK5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	{ 2, { LP8755_BUCK0, LP8755_BUCK5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	{ 1, { LP8755_BUCK0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	{ 2, { LP8755_BUCK0, LP8755_BUCK3} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	{ 4, { LP8755_BUCK0, LP8755_BUCK2, LP8755_BUCK3, LP8755_BUCK5} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int lp8755_init_data(struct lp8755_chip *pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	int ret, icnt, buck_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	struct lp8755_platform_data *pdata = pchip->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	/* read back  muti-phase configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	ret = regmap_read(pchip->regmap, 0x3D, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 		goto out_i2c_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	pchip->mphase = regval & 0x0F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	/* set default data based on multi-phase config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		buck_num = mphase_buck[pchip->mphase].buck_num[icnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		pdata->buck_data[buck_num] = &lp8755_reg_default[buck_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) out_i2c_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	dev_err(pchip->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define lp8755_buck_desc(_id)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	.name = lp8755_rail(_id),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	.id   = LP8755_BUCK##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.ops  = &lp8755_buck_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.n_voltages = LP8755_BUCK_LINEAR_OUT_MAX+1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	.uV_step = 10000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.min_uV = 500000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.enable_reg = LP8755_REG_BUCK##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.enable_mask = LP8755_BUCK_EN_M,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.vsel_reg = LP8755_REG_BUCK##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.vsel_mask = LP8755_BUCK_VOUT_M,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static const struct regulator_desc lp8755_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	lp8755_buck_desc(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	lp8755_buck_desc(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	lp8755_buck_desc(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	lp8755_buck_desc(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	lp8755_buck_desc(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	lp8755_buck_desc(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static int lp8755_regulator_init(struct lp8755_chip *pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	int ret, icnt, buck_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	struct lp8755_platform_data *pdata = pchip->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	struct regulator_config rconfig = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	rconfig.regmap = pchip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	rconfig.dev = pchip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 	rconfig.driver_data = pchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	for (icnt = 0; icnt < mphase_buck[pchip->mphase].nreg; icnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		buck_num = mphase_buck[pchip->mphase].buck_num[icnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		rconfig.init_data = pdata->buck_data[buck_num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		rconfig.of_node = pchip->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		pchip->rdev[buck_num] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		    devm_regulator_register(pchip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				    &lp8755_regulators[buck_num], &rconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		if (IS_ERR(pchip->rdev[buck_num])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 			ret = PTR_ERR(pchip->rdev[buck_num]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 			pchip->rdev[buck_num] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 			dev_err(pchip->dev, "regulator init failed: buck %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 				buck_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static irqreturn_t lp8755_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	int ret, icnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	unsigned int flag0, flag1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct lp8755_chip *pchip = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	/* read flag0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	ret = regmap_read(pchip->regmap, 0x0D, &flag0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	/* clear flag register to pull up int. pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	ret = regmap_write(pchip->regmap, 0x0D, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	/* sent power fault detection event to specific regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 		if ((flag0 & (0x4 << icnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		    && (pchip->irqmask & (0x04 << icnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		    && (pchip->rdev[icnt] != NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 			regulator_notifier_call_chain(pchip->rdev[icnt],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 						      LP8755_EVENT_PWR_FAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 						      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	/* read flag1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	ret = regmap_read(pchip->regmap, 0x0E, &flag1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	/* clear flag register to pull up int. pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	ret = regmap_write(pchip->regmap, 0x0E, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		goto err_i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	/* send OCP event to all regulator devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	if ((flag1 & 0x01) && (pchip->irqmask & 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 		for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 			if (pchip->rdev[icnt] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				regulator_notifier_call_chain(pchip->rdev[icnt],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 							      LP8755_EVENT_OCP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 							      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	/* send OVP event to all regulator devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	if ((flag1 & 0x02) && (pchip->irqmask & 0x02))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 		for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 			if (pchip->rdev[icnt] != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 				regulator_notifier_call_chain(pchip->rdev[icnt],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 							      LP8755_EVENT_OVP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 							      NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) err_i2c:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	dev_err(pchip->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int lp8755_int_config(struct lp8755_chip *pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	unsigned int regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	if (pchip->irq == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		dev_warn(pchip->dev, "not use interrupt : %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	ret = regmap_read(pchip->regmap, 0x0F, &regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		dev_err(pchip->dev, "i2c access error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	pchip->irqmask = regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	return devm_request_threaded_irq(pchip->dev, pchip->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 					 lp8755_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 					 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 					 "lp8755-irq", pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static const struct regmap_config lp8755_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	.max_register = LP8755_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static int lp8755_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	int ret, icnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	struct lp8755_chip *pchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	struct lp8755_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		dev_err(&client->dev, "i2c functionality check fail.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	pchip = devm_kzalloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			     sizeof(struct lp8755_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	if (!pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	pchip->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	pchip->regmap = devm_regmap_init_i2c(client, &lp8755_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	if (IS_ERR(pchip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		ret = PTR_ERR(pchip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		dev_err(&client->dev, "fail to allocate regmap %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	i2c_set_clientdata(client, pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	if (pdata != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		pchip->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		pchip->mphase = pdata->mphase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		pchip->pdata = devm_kzalloc(pchip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 					    sizeof(struct lp8755_platform_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 					    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 		if (!pchip->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		ret = lp8755_init_data(pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 			dev_err(&client->dev, "fail to initialize chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	ret = lp8755_regulator_init(pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		dev_err(&client->dev, "fail to initialize regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	pchip->irq = client->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	ret = lp8755_int_config(pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		dev_err(&client->dev, "fail to irq config\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	/* output disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 		regmap_write(pchip->regmap, icnt, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) static int lp8755_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	int icnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	struct lp8755_chip *pchip = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	for (icnt = 0; icnt < LP8755_BUCK_MAX; icnt++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		regmap_write(pchip->regmap, icnt, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const struct i2c_device_id lp8755_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	{LP8755_NAME, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_DEVICE_TABLE(i2c, lp8755_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static struct i2c_driver lp8755_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		   .name = LP8755_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		   },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	.probe = lp8755_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	.remove = lp8755_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	.id_table = lp8755_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int __init lp8755_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	return i2c_add_driver(&lp8755_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) subsys_initcall(lp8755_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void __exit lp8755_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	i2c_del_driver(&lp8755_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) module_exit(lp8755_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) MODULE_DESCRIPTION("Texas Instruments lp8755 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) MODULE_AUTHOR("Daniel Jeong <daniel.jeong@ti.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) MODULE_LICENSE("GPL v2");