Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * LP8752 High Performance Power Management Unit : System Interface Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: zhangqing <zhangqing@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LP8752_CTRL_BUCK0		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LP8752_CTRL_BUCK1		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LP8752_CTRL_BUCK2		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LP8752_CTRL_BUCK3		0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LP8752_VOUT_BUCK0		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LP8752_VOUT_BUCK1		0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LP8752_VOUT_BUCK2		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LP8752_VOUT_BUCK3		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LP8752_BUCK_VSEL_MASK		0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LP8752_REG_MAX			0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) enum lp8752_bucks {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	LP8752_BUCK0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	LP8752_BUCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	LP8752_BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	LP8752_BUCK3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	LP8752_BUCK_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static const struct linear_range lp8752_buck_voltage_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	REGULATOR_LINEAR_RANGE(500000, 0, 23, 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	REGULATOR_LINEAR_RANGE(735000, 24, 157, 5000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	REGULATOR_LINEAR_RANGE(1420000, 158, 255, 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) struct lp8752_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	int nphase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct device_node *of_node[LP8752_BUCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	struct regulator_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct regulator_init_data *buck_data[LP8752_BUCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) struct lp8752_mphase {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	int nreg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	int buck_id[LP8752_BUCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) struct lp8752_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	int nphase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct lp8752_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct regulator_dev *rdev[LP8752_BUCK_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) static int lp8752_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct lp8752_chip *pchip = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	u8 msk = BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	case REGULATOR_MODE_FAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 		/* forced pwm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 		ret = regmap_update_bits(pchip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 					 rdev->desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 					 msk, 0x1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 		/* automatic pwm/pfm mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 		ret = regmap_update_bits(pchip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 					 rdev->desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 					 msk, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		dev_err(pchip->dev, "error:lp8752 only support auto and pwm mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static unsigned int lp8752_buck_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	struct lp8752_chip *pchip = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	unsigned int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	ret = regmap_read(pchip->regmap, rdev->desc->enable_reg, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		dev_err(pchip->dev, "i2c acceess error %s\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	return (reg & BIT(1)) ?  REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static struct regulator_ops lp8752_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	.map_voltage = regulator_map_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	.list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	.set_voltage_time_sel = regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	.set_mode = lp8752_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	.get_mode = lp8752_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define lp8752_rail(_id) "lp8752_buck"#_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define vin(_id) "vin"#_id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct lp8752_mphase mphase_buck[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{ 1, { LP8752_BUCK0} },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{ 2, { LP8752_BUCK0, LP8752_BUCK3 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{ 3, { LP8752_BUCK0, LP8752_BUCK2, LP8752_BUCK3 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{ 4, { LP8752_BUCK0, LP8752_BUCK1, LP8752_BUCK2, LP8752_BUCK3 } },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static struct of_regulator_match lp8752_reg_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{ .name = "lp8752_buck0", .driver_data = (void *)0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{ .name = "lp8752_buck1", .driver_data = (void *)1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{ .name = "lp8752_buck2", .driver_data = (void *)2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	{ .name = "lp8752_buck3", .driver_data = (void *)3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static int lp8752_init_data(struct lp8752_chip *pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	int icnt, buck_id, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct lp8752_platform_data *pdata = pchip->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	struct device_node *regs, *lp8752_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	lp8752_np = of_node_get(pchip->dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!lp8752_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		dev_err(pchip->dev, "Failed to find device node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	regs = of_find_node_by_name(lp8752_np, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	count = of_regulator_match(pchip->dev, regs, lp8752_reg_matches,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 				   LP8752_BUCK_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	of_node_put(regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	if ((count <= 0) || (count > LP8752_BUCK_MAX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	pchip->nphase = (count - 1) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* set default data based on multi-phase config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	for (icnt = 0; icnt < mphase_buck[pchip->nphase].nreg; icnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 		buck_id = mphase_buck[pchip->nphase].buck_id[icnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		pdata->buck_data[buck_id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		lp8752_reg_matches[buck_id].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 		pdata->of_node[buck_id] = lp8752_reg_matches[buck_id].of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define lp8752_buck_desc(_id)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	.name = lp8752_rail(_id),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	.id   = LP8752_BUCK##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	.supply_name = vin(_id),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	.ops  = &lp8752_buck_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	.n_voltages = LP8752_BUCK_VSEL_MASK + 1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	.linear_ranges = lp8752_buck_voltage_ranges,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	.n_linear_ranges = ARRAY_SIZE(lp8752_buck_voltage_ranges),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	.enable_reg = LP8752_CTRL_BUCK##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	.enable_mask = BIT(7),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	.vsel_reg = LP8752_VOUT_BUCK##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	.vsel_mask = LP8752_BUCK_VSEL_MASK,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	.enable_time = 400,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static struct regulator_desc lp8752_reg_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	lp8752_buck_desc(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	lp8752_buck_desc(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	lp8752_buck_desc(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	lp8752_buck_desc(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int lp8752_regulator_init(struct lp8752_chip *pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	int ret, icnt, buck_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct lp8752_platform_data *pdata = pchip->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct regulator_config rconfig = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	rconfig.regmap = pchip->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	rconfig.dev = pchip->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	rconfig.driver_data = pchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	for (icnt = 0; icnt < mphase_buck[pchip->nphase].nreg; icnt++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		buck_id = mphase_buck[pchip->nphase].buck_id[icnt];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		rconfig.init_data = pdata->buck_data[buck_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 		rconfig.of_node = pdata->of_node[buck_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		pchip->rdev[buck_id] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 		devm_regulator_register(pchip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 					&lp8752_reg_desc[buck_id],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 					&rconfig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 		if (IS_ERR(pchip->rdev[buck_id])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 			ret = PTR_ERR(pchip->rdev[buck_id]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 			pchip->rdev[buck_id] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 			dev_err(pchip->dev, "regulator init failed: buck %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 				buck_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct regmap_config lp8752_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.max_register = LP8752_REG_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static int lp8752_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct lp8752_chip *pchip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct lp8752_platform_data *pdata = dev_get_platdata(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	pchip = devm_kzalloc(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			     sizeof(struct lp8752_chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	if (!pchip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	pchip->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	pchip->regmap = devm_regmap_init_i2c(client, &lp8752_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (IS_ERR(pchip->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		ret = PTR_ERR(pchip->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		dev_err(&client->dev, "fail to allocate regmap %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	i2c_set_clientdata(client, pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	ret = regmap_update_bits(pchip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 				 LP8752_CTRL_BUCK0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 				 (1 << 0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	ret = regmap_update_bits(pchip->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				 LP8752_CTRL_BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 				 (1 << 0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		pchip->pdata = devm_kzalloc(pchip->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 					    sizeof(struct lp8752_platform_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 					    GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		if (!pchip->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		ret = lp8752_init_data(pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			dev_err(&client->dev, "fail to initialize chip\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		pchip->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		pchip->nphase = pdata->nphase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	lp8752_regulator_init(pchip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static const struct of_device_id lp8752_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	{ .compatible = "ti,lp8752", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) MODULE_DEVICE_TABLE(of, lp8752_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static const struct i2c_device_id lp8752_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	{"lp8752", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	{}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) MODULE_DEVICE_TABLE(i2c, lp8752_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct i2c_driver lp8752_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.probe = lp8752_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.id_table = lp8752_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.name = "lp8752",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.of_match_table = of_match_ptr(lp8752_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) module_i2c_driver(lp8752_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_DESCRIPTION("Texas Instruments lp8752 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_LICENSE("GPL v2");