^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2012 Texas Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Milo(Woogyom) Kim <milo.kim@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regulator/lp872x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Registers : LP8720/8725 shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP872X_GENERAL_CFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP872X_LDO1_VOUT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP872X_LDO2_VOUT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP872X_LDO3_VOUT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP872X_LDO4_VOUT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP872X_LDO5_VOUT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Registers : LP8720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP8720_BUCK_VOUT1 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP8720_BUCK_VOUT2 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP8720_ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Registers : LP8725 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP8725_LILO1_VOUT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP8725_LILO2_VOUT 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP8725_BUCK1_VOUT1 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define LP8725_BUCK1_VOUT2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LP8725_BUCK2_VOUT1 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LP8725_BUCK2_VOUT2 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LP8725_BUCK_CTRL 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LP8725_LDO_CTRL 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Mask/shift : LP8720/LP8725 shared */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP872X_VOUT_M 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP872X_START_DELAY_M 0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define LP872X_START_DELAY_S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define LP872X_EN_LDO1_M BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LP872X_EN_LDO2_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LP872X_EN_LDO3_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LP872X_EN_LDO4_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LP872X_EN_LDO5_M BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Mask/shift : LP8720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define LP8720_TIMESTEP_S 0 /* Addr 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LP8720_TIMESTEP_M BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LP8720_EXT_DVS_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LP8720_BUCK_FPWM_S 5 /* Addr 07h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LP8720_BUCK_FPWM_M BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LP8720_EN_BUCK_M BIT(5) /* Addr 08h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LP8720_DVS_SEL_M BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Mask/shift : LP8725 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LP8725_TIMESTEP_M 0xC0 /* Addr 00h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LP8725_TIMESTEP_S 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LP8725_BUCK1_EN_M BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LP8725_DVS1_M BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LP8725_DVS2_M BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LP8725_BUCK2_EN_M BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LP8725_BUCK_CL_M 0xC0 /* Addr 09h, 0Bh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LP8725_BUCK_CL_S 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LP8725_BUCK1_FPWM_S 1 /* Addr 0Ch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LP8725_BUCK1_FPWM_M BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LP8725_BUCK2_FPWM_S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LP8725_BUCK2_FPWM_M BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LP8725_EN_LILO1_M BIT(5) /* Addr 0Dh */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define LP8725_EN_LILO2_M BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* PWM mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LP872X_FORCE_PWM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LP872X_AUTO_PWM 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LP8720_NUM_REGULATORS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LP8725_NUM_REGULATORS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define EXTERN_DVS_USED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MAX_DELAY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Default DVS Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LP8720_DEFAULT_DVS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LP8725_DEFAULT_DVS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* dump registers in regmap-debugfs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MAX_REGISTERS 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum lp872x_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) LP8720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) LP8725,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct lp872x {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum lp872x_id chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct lp872x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int num_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum lp872x_dvs_state dvs_pin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* LP8720/LP8725 shared voltage table for LDOs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const unsigned int lp872x_ldo_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000, 1550000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 1900000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 2100000, 2200000, 2300000, 2400000, 2500000, 2600000, 2650000, 2700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 2750000, 2800000, 2850000, 2900000, 2950000, 3000000, 3100000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* LP8720 LDO4 voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) static const unsigned int lp8720_ldo4_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 800000, 850000, 900000, 1000000, 1100000, 1200000, 1250000, 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 1350000, 1400000, 1450000, 1500000, 1550000, 1600000, 1650000, 1700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 1750000, 1800000, 1850000, 1900000, 2000000, 2100000, 2200000, 2300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 2400000, 2500000, 2600000, 2650000, 2700000, 2750000, 2800000, 2850000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* LP8725 LILO(Low Input Low Output) voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static const unsigned int lp8725_lilo_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, 1150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 1200000, 1250000, 1300000, 1350000, 1400000, 1500000, 1600000, 1700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 2600000, 2700000, 2800000, 2850000, 2900000, 3000000, 3100000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* LP8720 BUCK voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EXT_R 0 /* external resistor divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static const unsigned int lp8720_buck_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) EXT_R, 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 1550000, 1600000, 1650000, 1700000, 1750000, 1800000, 1850000, 1900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 1950000, 2000000, 2050000, 2100000, 2150000, 2200000, 2250000, 2300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* LP8725 BUCK voltage table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const unsigned int lp8725_buck_vtbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 800000, 850000, 900000, 950000, 1000000, 1050000, 1100000, 1150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 1200000, 1250000, 1300000, 1350000, 1400000, 1500000, 1600000, 1700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 1750000, 1800000, 1850000, 1900000, 2000000, 2100000, 2200000, 2300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 2400000, 2500000, 2600000, 2700000, 2800000, 2850000, 2900000, 3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* LP8725 BUCK current limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const unsigned int lp8725_buck_uA[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 460000, 780000, 1050000, 1370000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int lp872x_read_byte(struct lp872x *lp, u8 addr, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ret = regmap_read(lp->regmap, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(lp->dev, "failed to read 0x%.2x\n", addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) *data = (u8)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline int lp872x_write_byte(struct lp872x *lp, u8 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return regmap_write(lp->regmap, addr, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static inline int lp872x_update_bits(struct lp872x *lp, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned int mask, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return regmap_update_bits(lp->regmap, addr, mask, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int lp872x_get_timestep_usec(struct lp872x *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) enum lp872x_id chip = lp->chipid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 val, mask, shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int *time_usec, size, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int lp8720_time_usec[] = { 25, 50 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int lp8725_time_usec[] = { 32, 64, 128, 256 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) switch (chip) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) case LP8720:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) mask = LP8720_TIMESTEP_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) shift = LP8720_TIMESTEP_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) time_usec = &lp8720_time_usec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) size = ARRAY_SIZE(lp8720_time_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) case LP8725:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mask = LP8725_TIMESTEP_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) shift = LP8725_TIMESTEP_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) time_usec = &lp8725_time_usec[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) size = ARRAY_SIZE(lp8725_time_usec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = lp872x_read_byte(lp, LP872X_GENERAL_CFG, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val = (val & mask) >> shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (val >= size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return *(time_usec + val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int lp872x_regulator_enable_time(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct lp872x *lp = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) enum lp872x_regulator_id rid = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int time_step_us = lp872x_get_timestep_usec(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u8 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (time_step_us < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return time_step_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) switch (rid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case LP8720_ID_LDO1 ... LP8720_ID_BUCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) addr = LP872X_LDO1_VOUT + rid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) case LP8725_ID_LDO1 ... LP8725_ID_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) addr = LP872X_LDO1_VOUT + rid - LP8725_ID_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) case LP8725_ID_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) addr = LP8725_BUCK2_VOUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = lp872x_read_byte(lp, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) val = (val & LP872X_START_DELAY_M) >> LP872X_START_DELAY_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return val > MAX_DELAY ? 0 : val * time_step_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void lp872x_set_dvs(struct lp872x *lp, enum lp872x_dvs_sel dvs_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum lp872x_dvs_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) state = dvs_sel == SEL_V1 ? DVS_HIGH : DVS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) gpio_set_value(gpio, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) lp->dvs_pin = state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static u8 lp872x_select_buck_vout_addr(struct lp872x *lp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) enum lp872x_regulator_id buck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u8 val, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (lp872x_read_byte(lp, LP872X_GENERAL_CFG, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) switch (buck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) case LP8720_ID_BUCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (val & LP8720_EXT_DVS_M) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) addr = (lp->dvs_pin == DVS_HIGH) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) LP8720_BUCK_VOUT1 : LP8720_BUCK_VOUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (lp872x_read_byte(lp, LP8720_ENABLE, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) addr = val & LP8720_DVS_SEL_M ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) LP8720_BUCK_VOUT1 : LP8720_BUCK_VOUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) case LP8725_ID_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) if (val & LP8725_DVS1_M)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) addr = LP8725_BUCK1_VOUT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) addr = (lp->dvs_pin == DVS_HIGH) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) LP8725_BUCK1_VOUT1 : LP8725_BUCK1_VOUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) case LP8725_ID_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) addr = val & LP8725_DVS2_M ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) LP8725_BUCK2_VOUT1 : LP8725_BUCK2_VOUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static bool lp872x_is_valid_buck_addr(u8 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) switch (addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) case LP8720_BUCK_VOUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case LP8720_BUCK_VOUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) case LP8725_BUCK1_VOUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) case LP8725_BUCK1_VOUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) case LP8725_BUCK2_VOUT1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case LP8725_BUCK2_VOUT2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int lp872x_buck_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct lp872x *lp = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) enum lp872x_regulator_id buck = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u8 addr, mask = LP872X_VOUT_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct lp872x_dvs *dvs = lp->pdata ? lp->pdata->dvs : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (dvs && gpio_is_valid(dvs->gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) lp872x_set_dvs(lp, dvs->vsel, dvs->gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) addr = lp872x_select_buck_vout_addr(lp, buck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (!lp872x_is_valid_buck_addr(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return lp872x_update_bits(lp, addr, mask, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) static int lp872x_buck_get_voltage_sel(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct lp872x *lp = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) enum lp872x_regulator_id buck = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 addr, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) addr = lp872x_select_buck_vout_addr(lp, buck);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (!lp872x_is_valid_buck_addr(addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = lp872x_read_byte(lp, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return val & LP872X_VOUT_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int lp872x_buck_set_mode(struct regulator_dev *rdev, unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct lp872x *lp = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) enum lp872x_regulator_id buck = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 addr, mask, shift, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) switch (buck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) case LP8720_ID_BUCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) addr = LP8720_BUCK_VOUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) mask = LP8720_BUCK_FPWM_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) shift = LP8720_BUCK_FPWM_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) case LP8725_ID_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) addr = LP8725_BUCK_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mask = LP8725_BUCK1_FPWM_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) shift = LP8725_BUCK1_FPWM_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) case LP8725_ID_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) addr = LP8725_BUCK_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) mask = LP8725_BUCK2_FPWM_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) shift = LP8725_BUCK2_FPWM_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (mode == REGULATOR_MODE_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val = LP872X_FORCE_PWM << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else if (mode == REGULATOR_MODE_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val = LP872X_AUTO_PWM << shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return lp872x_update_bits(lp, addr, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static unsigned int lp872x_buck_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct lp872x *lp = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) enum lp872x_regulator_id buck = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u8 addr, mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (buck) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case LP8720_ID_BUCK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) addr = LP8720_BUCK_VOUT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) mask = LP8720_BUCK_FPWM_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case LP8725_ID_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) addr = LP8725_BUCK_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) mask = LP8725_BUCK1_FPWM_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case LP8725_ID_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) addr = LP8725_BUCK_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) mask = LP8725_BUCK2_FPWM_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = lp872x_read_byte(lp, addr, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return val & mask ? REGULATOR_MODE_FAST : REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct regulator_ops lp872x_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .enable_time = lp872x_regulator_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) static const struct regulator_ops lp8720_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .set_voltage_sel = lp872x_buck_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .get_voltage_sel = lp872x_buck_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .enable_time = lp872x_regulator_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .set_mode = lp872x_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .get_mode = lp872x_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct regulator_ops lp8725_buck_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .set_voltage_sel = lp872x_buck_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .get_voltage_sel = lp872x_buck_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .enable_time = lp872x_regulator_enable_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .set_mode = lp872x_buck_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .get_mode = lp872x_buck_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .set_current_limit = regulator_set_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .get_current_limit = regulator_get_current_limit_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct regulator_desc lp8720_regulator_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .name = "ldo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .of_match = of_match_ptr("ldo1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .id = LP8720_ID_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .vsel_reg = LP872X_LDO1_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .enable_reg = LP8720_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .enable_mask = LP872X_EN_LDO1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .name = "ldo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .of_match = of_match_ptr("ldo2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .id = LP8720_ID_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .vsel_reg = LP872X_LDO2_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .enable_reg = LP8720_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .enable_mask = LP872X_EN_LDO2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .name = "ldo3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .of_match = of_match_ptr("ldo3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .id = LP8720_ID_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .vsel_reg = LP872X_LDO3_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .enable_reg = LP8720_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .enable_mask = LP872X_EN_LDO3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .name = "ldo4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .of_match = of_match_ptr("ldo4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .id = LP8720_ID_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .n_voltages = ARRAY_SIZE(lp8720_ldo4_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .volt_table = lp8720_ldo4_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .vsel_reg = LP872X_LDO4_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .enable_reg = LP8720_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .enable_mask = LP872X_EN_LDO4_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .name = "ldo5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .of_match = of_match_ptr("ldo5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .id = LP8720_ID_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .vsel_reg = LP872X_LDO5_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .enable_reg = LP8720_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .enable_mask = LP872X_EN_LDO5_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .name = "buck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .of_match = of_match_ptr("buck"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .id = LP8720_ID_BUCK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .ops = &lp8720_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .n_voltages = ARRAY_SIZE(lp8720_buck_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .volt_table = lp8720_buck_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .enable_reg = LP8720_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .enable_mask = LP8720_EN_BUCK_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static const struct regulator_desc lp8725_regulator_desc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .name = "ldo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .of_match = of_match_ptr("ldo1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .id = LP8725_ID_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .vsel_reg = LP872X_LDO1_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .enable_mask = LP872X_EN_LDO1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .name = "ldo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .of_match = of_match_ptr("ldo2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .id = LP8725_ID_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .vsel_reg = LP872X_LDO2_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .enable_mask = LP872X_EN_LDO2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .name = "ldo3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .of_match = of_match_ptr("ldo3"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .id = LP8725_ID_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .vsel_reg = LP872X_LDO3_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .enable_mask = LP872X_EN_LDO3_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .name = "ldo4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .of_match = of_match_ptr("ldo4"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .id = LP8725_ID_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .vsel_reg = LP872X_LDO4_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .enable_mask = LP872X_EN_LDO4_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .name = "ldo5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .of_match = of_match_ptr("ldo5"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .id = LP8725_ID_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .n_voltages = ARRAY_SIZE(lp872x_ldo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .volt_table = lp872x_ldo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) .vsel_reg = LP872X_LDO5_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .enable_mask = LP872X_EN_LDO5_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .name = "lilo1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .of_match = of_match_ptr("lilo1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .id = LP8725_ID_LILO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .n_voltages = ARRAY_SIZE(lp8725_lilo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .volt_table = lp8725_lilo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) .vsel_reg = LP8725_LILO1_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .enable_mask = LP8725_EN_LILO1_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .name = "lilo2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .of_match = of_match_ptr("lilo2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .id = LP8725_ID_LILO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .ops = &lp872x_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .n_voltages = ARRAY_SIZE(lp8725_lilo_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .volt_table = lp8725_lilo_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .vsel_reg = LP8725_LILO2_VOUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .vsel_mask = LP872X_VOUT_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .enable_reg = LP8725_LDO_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .enable_mask = LP8725_EN_LILO2_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .name = "buck1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .of_match = of_match_ptr("buck1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .id = LP8725_ID_BUCK1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .ops = &lp8725_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .n_voltages = ARRAY_SIZE(lp8725_buck_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .volt_table = lp8725_buck_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .enable_reg = LP872X_GENERAL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .enable_mask = LP8725_BUCK1_EN_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .curr_table = lp8725_buck_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) .n_current_limits = ARRAY_SIZE(lp8725_buck_uA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) .csel_reg = LP8725_BUCK1_VOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) .csel_mask = LP8725_BUCK_CL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .name = "buck2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .of_match = of_match_ptr("buck2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .id = LP8725_ID_BUCK2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .ops = &lp8725_buck_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .n_voltages = ARRAY_SIZE(lp8725_buck_vtbl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .volt_table = lp8725_buck_vtbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) .enable_reg = LP872X_GENERAL_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .enable_mask = LP8725_BUCK2_EN_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .curr_table = lp8725_buck_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .n_current_limits = ARRAY_SIZE(lp8725_buck_uA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .csel_reg = LP8725_BUCK2_VOUT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .csel_mask = LP8725_BUCK_CL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static int lp872x_init_dvs(struct lp872x *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int ret, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct lp872x_dvs *dvs = lp->pdata ? lp->pdata->dvs : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) enum lp872x_dvs_state pinstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u8 mask[] = { LP8720_EXT_DVS_M, LP8725_DVS1_M | LP8725_DVS2_M };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 default_dvs_mode[] = { LP8720_DEFAULT_DVS, LP8725_DEFAULT_DVS };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto set_default_dvs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) gpio = dvs->gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!gpio_is_valid(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) goto set_default_dvs_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) pinstate = dvs->init_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = devm_gpio_request_one(lp->dev, gpio, pinstate, "LP872X DVS");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev_err(lp->dev, "gpio request err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) lp->dvs_pin = pinstate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) set_default_dvs_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return lp872x_update_bits(lp, LP872X_GENERAL_CFG, mask[lp->chipid],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) default_dvs_mode[lp->chipid]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int lp872x_hw_enable(struct lp872x *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int ret, gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (!lp->pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) gpio = lp->pdata->enable_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!gpio_is_valid(gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Always set enable GPIO high. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) ret = devm_gpio_request_one(lp->dev, gpio, GPIOF_OUT_INIT_HIGH, "LP872X EN");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dev_err(lp->dev, "gpio request err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Each chip has a different enable delay. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (lp->chipid == LP8720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) usleep_range(LP8720_ENABLE_DELAY, 1.5 * LP8720_ENABLE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) usleep_range(LP8725_ENABLE_DELAY, 1.5 * LP8725_ENABLE_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int lp872x_config(struct lp872x *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct lp872x_platform_data *pdata = lp->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (!pdata || !pdata->update_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) goto init_dvs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = lp872x_write_byte(lp, LP872X_GENERAL_CFG, pdata->general_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) init_dvs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return lp872x_init_dvs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static struct regulator_init_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) *lp872x_find_regulator_init_data(int id, struct lp872x *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct lp872x_platform_data *pdata = lp->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0; i < lp->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (pdata->regulator_data[i].id == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return pdata->regulator_data[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int lp872x_regulator_register(struct lp872x *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) const struct regulator_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct regulator_config cfg = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) for (i = 0; i < lp->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) desc = (lp->chipid == LP8720) ? &lp8720_regulator_desc[i] :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) &lp8725_regulator_desc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) cfg.dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) cfg.init_data = lp872x_find_regulator_init_data(desc->id, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) cfg.driver_data = lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) cfg.regmap = lp->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) rdev = devm_regulator_register(lp->dev, desc, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev_err(lp->dev, "regulator register err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static const struct regmap_config lp872x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .max_register = MAX_REGISTERS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define LP872X_VALID_OPMODE (REGULATOR_MODE_FAST | REGULATOR_MODE_NORMAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static struct of_regulator_match lp8720_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { .name = "ldo1", .driver_data = (void *)LP8720_ID_LDO1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { .name = "ldo2", .driver_data = (void *)LP8720_ID_LDO2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { .name = "ldo3", .driver_data = (void *)LP8720_ID_LDO3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) { .name = "ldo4", .driver_data = (void *)LP8720_ID_LDO4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) { .name = "ldo5", .driver_data = (void *)LP8720_ID_LDO5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) { .name = "buck", .driver_data = (void *)LP8720_ID_BUCK, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) static struct of_regulator_match lp8725_matches[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) { .name = "ldo1", .driver_data = (void *)LP8725_ID_LDO1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) { .name = "ldo2", .driver_data = (void *)LP8725_ID_LDO2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) { .name = "ldo3", .driver_data = (void *)LP8725_ID_LDO3, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) { .name = "ldo4", .driver_data = (void *)LP8725_ID_LDO4, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { .name = "ldo5", .driver_data = (void *)LP8725_ID_LDO5, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { .name = "lilo1", .driver_data = (void *)LP8725_ID_LILO1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { .name = "lilo2", .driver_data = (void *)LP8725_ID_LILO2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { .name = "buck1", .driver_data = (void *)LP8725_ID_BUCK1, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { .name = "buck2", .driver_data = (void *)LP8725_ID_BUCK2, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static struct lp872x_platform_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) *lp872x_populate_pdata_from_dt(struct device *dev, enum lp872x_id which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct lp872x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct of_regulator_match *match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int num_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) u8 dvs_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (!pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) of_property_read_u8(np, "ti,general-config", &pdata->general_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (of_find_property(np, "ti,update-config", NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) pdata->update_config = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pdata->dvs = devm_kzalloc(dev, sizeof(struct lp872x_dvs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!pdata->dvs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) pdata->dvs->gpio = of_get_named_gpio(np, "ti,dvs-gpio", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) of_property_read_u8(np, "ti,dvs-vsel", (u8 *)&pdata->dvs->vsel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) of_property_read_u8(np, "ti,dvs-state", &dvs_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) pdata->dvs->init_state = dvs_state ? DVS_HIGH : DVS_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) pdata->enable_gpio = of_get_named_gpio(np, "enable-gpios", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (of_get_child_count(np) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) case LP8720:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) match = lp8720_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) num_matches = ARRAY_SIZE(lp8720_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case LP8725:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) match = lp8725_matches;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) num_matches = ARRAY_SIZE(lp8725_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) count = of_regulator_match(dev, np, match, num_matches);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) for (i = 0; i < num_matches; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) pdata->regulator_data[i].id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) (enum lp872x_regulator_id)match[i].driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pdata->regulator_data[i].init_data = match[i].init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static struct lp872x_platform_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) *lp872x_populate_pdata_from_dt(struct device *dev, enum lp872x_id which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int lp872x_probe(struct i2c_client *cl, const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct lp872x *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct lp872x_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) const int lp872x_num_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) [LP8720] = LP8720_NUM_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) [LP8725] = LP8725_NUM_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (cl->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) pdata = lp872x_populate_pdata_from_dt(&cl->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) (enum lp872x_id)id->driver_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (IS_ERR(pdata))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return PTR_ERR(pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) pdata = dev_get_platdata(&cl->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) lp = devm_kzalloc(&cl->dev, sizeof(struct lp872x), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) lp->num_regulators = lp872x_num_regulators[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) lp->regmap = devm_regmap_init_i2c(cl, &lp872x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (IS_ERR(lp->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ret = PTR_ERR(lp->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dev_err(&cl->dev, "regmap init i2c err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) lp->dev = &cl->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) lp->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) lp->chipid = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) i2c_set_clientdata(cl, lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = lp872x_hw_enable(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret = lp872x_config(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return lp872x_regulator_register(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) static const struct of_device_id lp872x_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) { .compatible = "ti,lp8720", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) { .compatible = "ti,lp8725", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) MODULE_DEVICE_TABLE(of, lp872x_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static const struct i2c_device_id lp872x_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {"lp8720", LP8720},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {"lp8725", LP8725},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) MODULE_DEVICE_TABLE(i2c, lp872x_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static struct i2c_driver lp872x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .name = "lp872x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .of_match_table = of_match_ptr(lp872x_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .probe = lp872x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .id_table = lp872x_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) module_i2c_driver(lp872x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) MODULE_DESCRIPTION("TI/National Semiconductor LP872x PMU Regulator Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) MODULE_AUTHOR("Milo Kim");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags