Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Regulator driver for National Semiconductors LP3972 PMIC chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Based on lp3971.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/lp3972.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) struct lp3972 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 	struct mutex io_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* LP3972 Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define LP3972_SCR_REG		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define LP3972_OVER1_REG	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define LP3972_OVSR1_REG	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define LP3972_OVER2_REG	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LP3972_OVSR2_REG	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LP3972_VCC1_REG		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define LP3972_ADTV1_REG	0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define LP3972_ADTV2_REG	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define LP3972_AVRC_REG		0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define LP3972_CDTC1_REG	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define LP3972_CDTC2_REG	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LP3972_SDTV1_REG	0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LP3972_SDTV2_REG	0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LP3972_MDTV1_REG	0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define LP3972_MDTV2_REG	0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define LP3972_L2VCR_REG	0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define LP3972_L34VCR_REG	0x3A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define LP3972_SCR1_REG		0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define LP3972_SCR2_REG		0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define LP3972_OEN3_REG		0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define LP3972_OSR3_REG		0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define LP3972_LOER4_REG	0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define LP3972_B2TV_REG		0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define LP3972_B3TV_REG		0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define LP3972_B32RC_REG	0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LP3972_ISRA_REG		0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LP3972_BCCR_REG		0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LP3972_II1RR_REG	0x8E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define LP3972_II2RR_REG	0x8F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define LP3972_SYS_CONTROL1_REG		LP3972_SCR1_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) /* System control register 1 initial value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * bits 5, 6 and 7 are EPROM programmable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SYS_CONTROL1_INIT_VAL		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SYS_CONTROL1_INIT_MASK		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define LP3972_VOL_CHANGE_REG		LP3972_VCC1_REG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LP3972_VOL_CHANGE_FLAG_GO	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define LP3972_VOL_CHANGE_FLAG_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* LDO output enable mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define LP3972_OEN3_L1EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define LP3972_OVER2_LDO2_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define LP3972_OVER2_LDO3_EN	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define LP3972_OVER2_LDO4_EN	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define LP3972_OVER1_S_EN	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) static const unsigned int ldo1_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	1700000, 1725000, 1750000, 1775000, 1800000, 1825000, 1850000, 1875000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	1900000, 1925000, 1950000, 1975000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static const unsigned int ldo23_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) static const unsigned int ldo4_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	1400000, 1500000, 1800000, 1900000, 2500000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) static const unsigned int ldo5_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	      0,       0,       0,       0,       0,  850000,  875000,  900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 925000,  950000,  975000, 1000000, 1025000, 1050000, 1075000, 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static const unsigned int buck1_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 725000,  750000,  775000,  800000,  825000,  850000,  875000,  900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 925000,  950000,  975000, 1000000, 1025000, 1050000, 1075000, 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	1125000, 1150000, 1175000, 1200000, 1225000, 1250000, 1275000, 1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	1325000, 1350000, 1375000, 1400000, 1425000, 1450000, 1475000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const unsigned int buck23_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	      0,  800000,  850000,  900000,  950000, 1000000, 1050000, 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	1550000, 1600000, 1650000, 1700000, 1800000, 1900000, 2500000, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static const int ldo_output_enable_mask[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	LP3972_OEN3_L1EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	LP3972_OVER2_LDO2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	LP3972_OVER2_LDO3_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	LP3972_OVER2_LDO4_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	LP3972_OVER1_S_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static const int ldo_output_enable_addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	LP3972_OEN3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	LP3972_OVER2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	LP3972_OVER2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	LP3972_OVER2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	LP3972_OVER1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) static const int ldo_vol_ctl_addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	LP3972_MDTV1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	LP3972_L2VCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	LP3972_L34VCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	LP3972_L34VCR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	LP3972_SDTV1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const int buck_vol_enable_addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	LP3972_OVER1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	LP3972_OEN3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	LP3972_OEN3_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static const int buck_base_addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	LP3972_ADTV1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	LP3972_B2TV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	LP3972_B3TV_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LP3972_LDO_OUTPUT_ENABLE_MASK(x) (ldo_output_enable_mask[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LP3972_LDO_OUTPUT_ENABLE_REG(x) (ldo_output_enable_addr[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*	LDO voltage control registers shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	LP3972_LDO1 -> 0, LP3972_LDO2 -> 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	LP3972_LDO3 -> 0, LP3972_LDO4 -> 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	LP3972_LDO5 -> 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LP3972_LDO_VOL_CONTR_SHIFT(x) (((x) & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LP3972_LDO_VOL_CONTR_REG(x) (ldo_vol_ctl_addr[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LP3972_LDO_VOL_CHANGE_SHIFT(x) ((x) ? 4 : 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LP3972_LDO_VOL_MASK(x) (((x) % 4) ? 0x0f : 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LP3972_LDO_VOL_MIN_IDX(x) (((x) == 4) ? 0x05 : 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LP3972_LDO_VOL_MAX_IDX(x) ((x) ? (((x) == 4) ? 0x1f : 0x0f) : 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LP3972_BUCK_VOL_ENABLE_REG(x) (buck_vol_enable_addr[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LP3972_BUCK_VOL1_REG(x) (buck_base_addr[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LP3972_BUCK_VOL_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static int lp3972_i2c_read(struct i2c_client *i2c, char reg, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u16 *dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	ret = i2c_smbus_read_byte_data(i2c, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	*dest = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int lp3972_i2c_write(struct i2c_client *i2c, char reg, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	const u16 *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	return i2c_smbus_write_byte_data(i2c, reg, *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static u8 lp3972_reg_read(struct lp3972 *lp3972, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	mutex_lock(&lp3972->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	lp3972_i2c_read(lp3972->i2c, reg, 1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	dev_dbg(lp3972->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		(unsigned)val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	mutex_unlock(&lp3972->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	return val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static int lp3972_set_bits(struct lp3972 *lp3972, u8 reg, u16 mask, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	mutex_lock(&lp3972->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	ret = lp3972_i2c_read(lp3972->i2c, reg, 1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		tmp = (tmp & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		ret = lp3972_i2c_write(lp3972->i2c, reg, 1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		dev_dbg(lp3972->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			(unsigned)val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	mutex_unlock(&lp3972->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int lp3972_ldo_is_enabled(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int ldo = rdev_get_id(dev) - LP3972_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	val = lp3972_reg_read(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static int lp3972_ldo_enable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	int ldo = rdev_get_id(dev) - LP3972_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return lp3972_set_bits(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 				mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int lp3972_ldo_disable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	int ldo = rdev_get_id(dev) - LP3972_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	u16 mask = LP3972_LDO_OUTPUT_ENABLE_MASK(ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return lp3972_set_bits(lp3972, LP3972_LDO_OUTPUT_ENABLE_REG(ldo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 				mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int lp3972_ldo_get_voltage_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	int ldo = rdev_get_id(dev) - LP3972_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	u16 mask = LP3972_LDO_VOL_MASK(ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u16 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	reg = lp3972_reg_read(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	val = (reg >> LP3972_LDO_VOL_CONTR_SHIFT(ldo)) & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int lp3972_ldo_set_voltage_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 				      unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	int ldo = rdev_get_id(dev) - LP3972_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	int shift, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	shift = LP3972_LDO_VOL_CONTR_SHIFT(ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	ret = lp3972_set_bits(lp3972, LP3972_LDO_VOL_CONTR_REG(ldo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		LP3972_LDO_VOL_MASK(ldo) << shift, selector << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	/*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	 * LDO1 and LDO5 support voltage control by either target voltage1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	 * or target voltage2 register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	 * We use target voltage1 register for LDO1 and LDO5 in this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	 * We need to update voltage change control register(0x20) to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	 * LDO1 and LDO5 to change to their programmed target values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	switch (ldo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	case LP3972_LDO1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	case LP3972_LDO5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		shift = LP3972_LDO_VOL_CHANGE_SHIFT(ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			LP3972_VOL_CHANGE_FLAG_MASK << shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 			LP3972_VOL_CHANGE_FLAG_GO << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			LP3972_VOL_CHANGE_FLAG_MASK << shift, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const struct regulator_ops lp3972_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	.map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	.is_enabled = lp3972_ldo_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	.enable = lp3972_ldo_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	.disable = lp3972_ldo_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.get_voltage_sel = lp3972_ldo_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	.set_voltage_sel = lp3972_ldo_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static int lp3972_dcdc_is_enabled(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	int buck = rdev_get_id(dev) - LP3972_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u16 mask = 1 << (buck * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	val = lp3972_reg_read(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	return !!(val & mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int lp3972_dcdc_enable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	int buck = rdev_get_id(dev) - LP3972_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	u16 mask = 1 << (buck * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 				mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static int lp3972_dcdc_disable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	int buck = rdev_get_id(dev) - LP3972_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	u16 mask = 1 << (buck * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	val = lp3972_set_bits(lp3972, LP3972_BUCK_VOL_ENABLE_REG(buck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 				mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int lp3972_dcdc_get_voltage_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	int buck = rdev_get_id(dev) - LP3972_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	reg = lp3972_reg_read(lp3972, LP3972_BUCK_VOL1_REG(buck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	reg &= LP3972_BUCK_VOL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int lp3972_dcdc_set_voltage_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 				       unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct lp3972 *lp3972 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	int buck = rdev_get_id(dev) - LP3972_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	ret = lp3972_set_bits(lp3972, LP3972_BUCK_VOL1_REG(buck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 				LP3972_BUCK_VOL_MASK, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (buck != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	ret = lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		LP3972_VOL_CHANGE_FLAG_MASK, LP3972_VOL_CHANGE_FLAG_GO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	return lp3972_set_bits(lp3972, LP3972_VOL_CHANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 				LP3972_VOL_CHANGE_FLAG_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static const struct regulator_ops lp3972_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	.map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	.is_enabled = lp3972_dcdc_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	.enable = lp3972_dcdc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	.disable = lp3972_dcdc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	.get_voltage_sel = lp3972_dcdc_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 	.set_voltage_sel = lp3972_dcdc_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const struct regulator_desc regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		.name = "LDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		.id = LP3972_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		.ops = &lp3972_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		.n_voltages = ARRAY_SIZE(ldo1_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 		.volt_table = ldo1_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		.name = "LDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 		.id = LP3972_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		.ops = &lp3972_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		.n_voltages = ARRAY_SIZE(ldo23_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		.volt_table = ldo23_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		.name = "LDO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		.id = LP3972_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		.ops = &lp3972_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		.n_voltages = ARRAY_SIZE(ldo23_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		.volt_table = ldo23_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		.name = "LDO4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 		.id = LP3972_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 		.ops = &lp3972_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		.n_voltages = ARRAY_SIZE(ldo4_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 		.volt_table = ldo4_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 		.name = "LDO5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 		.id = LP3972_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		.ops = &lp3972_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		.n_voltages = ARRAY_SIZE(ldo5_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 		.volt_table = ldo5_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		.name = "DCDC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 		.id = LP3972_DCDC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 		.ops = &lp3972_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		.n_voltages = ARRAY_SIZE(buck1_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 		.volt_table = buck1_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		.name = "DCDC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		.id = LP3972_DCDC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 		.ops = &lp3972_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 		.n_voltages = ARRAY_SIZE(buck23_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		.volt_table = buck23_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		.name = "DCDC3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 		.id = LP3972_DCDC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 		.ops = &lp3972_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		.n_voltages = ARRAY_SIZE(buck23_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 		.volt_table = buck23_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int setup_regulators(struct lp3972 *lp3972,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	struct lp3972_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	/* Instantiate the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 	for (i = 0; i < pdata->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 		struct lp3972_regulator_subdev *reg = &pdata->regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 		struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 		struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		config.dev = lp3972->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 		config.init_data = reg->initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		config.driver_data = lp3972;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 		rdev = devm_regulator_register(lp3972->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 					       &regulators[reg->id], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 			err = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 			dev_err(lp3972->dev, "regulator init failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 				err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int lp3972_i2c_probe(struct i2c_client *i2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 			    const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 	struct lp3972 *lp3972;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	struct lp3972_platform_data *pdata = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 		dev_dbg(&i2c->dev, "No platform init data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	lp3972 = devm_kzalloc(&i2c->dev, sizeof(struct lp3972), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	if (!lp3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	lp3972->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	lp3972->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	mutex_init(&lp3972->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	/* Detect LP3972 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	ret = lp3972_i2c_read(i2c, LP3972_SYS_CONTROL1_REG, 1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	if (ret == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 		(val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		dev_err(&i2c->dev, "chip reported: val = 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 		dev_err(&i2c->dev, "failed to detect device. ret = %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	ret = setup_regulators(lp3972, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	i2c_set_clientdata(i2c, lp3972);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static const struct i2c_device_id lp3972_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	{ "lp3972", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) MODULE_DEVICE_TABLE(i2c, lp3972_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static struct i2c_driver lp3972_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		.name = "lp3972",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	.probe    = lp3972_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	.id_table = lp3972_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int __init lp3972_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	return i2c_add_driver(&lp3972_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) subsys_initcall(lp3972_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void __exit lp3972_module_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	i2c_del_driver(&lp3972_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) module_exit(lp3972_module_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) MODULE_AUTHOR("Axel Lin <axel.lin@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) MODULE_DESCRIPTION("LP3972 PMIC driver");