Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Regulator driver for National Semiconductors LP3971 PMIC chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *  Copyright (C) 2009 Samsung Electronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *  Author: Marek Szyprowski <m.szyprowski@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Based on wm8350.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bug.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/lp3971.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) struct lp3971 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 	struct mutex io_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) 	struct i2c_client *i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define LP3971_SYS_CONTROL1_REG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* System control register 1 initial value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)    bits 4 and 5 are EPROM programmable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SYS_CONTROL1_INIT_VAL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SYS_CONTROL1_INIT_MASK 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LP3971_BUCK_VOL_ENABLE_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define LP3971_BUCK_VOL_CHANGE_REG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /*	Voltage control registers shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	LP3971_BUCK1 -> 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	LP3971_BUCK2 -> 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	LP3971_BUCK3 -> 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define BUCK_VOL_CHANGE_SHIFT(x) (((!!x) << 2) | (x & ~0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define BUCK_VOL_CHANGE_FLAG_GO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define BUCK_VOL_CHANGE_FLAG_TARGET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define BUCK_VOL_CHANGE_FLAG_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define LP3971_BUCK1_BASE 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define LP3971_BUCK2_BASE 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define LP3971_BUCK3_BASE 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static const int buck_base_addr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	LP3971_BUCK1_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	LP3971_BUCK2_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	LP3971_BUCK3_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define LP3971_BUCK_TARGET_VOL1_REG(x) (buck_base_addr[x])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define LP3971_BUCK_TARGET_VOL2_REG(x) (buck_base_addr[x]+1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) static const unsigned int buck_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	      0,  800000,  850000,  900000,  950000, 1000000, 1050000, 1100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	1150000, 1200000, 1250000, 1300000, 1350000, 1400000, 1450000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	1550000, 1600000, 1650000, 1700000, 1800000, 1900000, 2500000, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define BUCK_TARGET_VOL_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define LP3971_BUCK_RAMP_REG(x)	(buck_base_addr[x]+2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define LP3971_LDO_ENABLE_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define LP3971_LDO_VOL_CONTR_BASE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) /*	Voltage control registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	LP3971_LDO1 -> LP3971_LDO_VOL_CONTR_BASE + 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	LP3971_LDO2 -> LP3971_LDO_VOL_CONTR_BASE + 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	LP3971_LDO3 -> LP3971_LDO_VOL_CONTR_BASE + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	LP3971_LDO4 -> LP3971_LDO_VOL_CONTR_BASE + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	LP3971_LDO5 -> LP3971_LDO_VOL_CONTR_BASE + 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define LP3971_LDO_VOL_CONTR_REG(x)	(LP3971_LDO_VOL_CONTR_BASE + (x >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /*	Voltage control registers shift:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	LP3971_LDO1 -> 0, LP3971_LDO2 -> 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	LP3971_LDO3 -> 0, LP3971_LDO4 -> 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	LP3971_LDO5 -> 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define LDO_VOL_CONTR_SHIFT(x) ((x & 1) << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define LDO_VOL_CONTR_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) static const unsigned int ldo45_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	1000000, 1050000, 1100000, 1150000, 1200000, 1250000, 1300000, 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	1400000, 1500000, 1800000, 1900000, 2500000, 2800000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) static const unsigned int ldo123_voltage_map[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	1800000, 1900000, 2000000, 2100000, 2200000, 2300000, 2400000, 2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	2600000, 2700000, 2800000, 2900000, 3000000, 3100000, 3200000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LDO_VOL_MIN_IDX 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LDO_VOL_MAX_IDX 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static int lp3971_ldo_is_enabled(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u16 mask = 1 << (1 + ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	val = lp3971_reg_read(lp3971, LP3971_LDO_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	return (val & mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static int lp3971_ldo_enable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	u16 mask = 1 << (1 + ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static int lp3971_ldo_disable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u16 mask = 1 << (1 + ldo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	return lp3971_set_bits(lp3971, LP3971_LDO_ENABLE_REG, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static int lp3971_ldo_get_voltage_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	u16 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	reg = lp3971_reg_read(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	val = (reg >> LDO_VOL_CONTR_SHIFT(ldo)) & LDO_VOL_CONTR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int lp3971_ldo_set_voltage_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 				      unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	int ldo = rdev_get_id(dev) - LP3971_LDO1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return lp3971_set_bits(lp3971, LP3971_LDO_VOL_CONTR_REG(ldo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			LDO_VOL_CONTR_MASK << LDO_VOL_CONTR_SHIFT(ldo),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 			selector << LDO_VOL_CONTR_SHIFT(ldo));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static const struct regulator_ops lp3971_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	.map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	.is_enabled = lp3971_ldo_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	.enable = lp3971_ldo_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	.disable = lp3971_ldo_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	.get_voltage_sel = lp3971_ldo_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	.set_voltage_sel = lp3971_ldo_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int lp3971_dcdc_is_enabled(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	u16 mask = 1 << (buck * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	val = lp3971_reg_read(lp3971, LP3971_BUCK_VOL_ENABLE_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	return (val & mask) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static int lp3971_dcdc_enable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	u16 mask = 1 << (buck * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static int lp3971_dcdc_disable(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	u16 mask = 1 << (buck * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_ENABLE_REG, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static int lp3971_dcdc_get_voltage_sel(struct regulator_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	reg = lp3971_reg_read(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	reg &= BUCK_TARGET_VOL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int lp3971_dcdc_set_voltage_sel(struct regulator_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				       unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct lp3971 *lp3971 = rdev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	int buck = rdev_get_id(dev) - LP3971_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	ret = lp3971_set_bits(lp3971, LP3971_BUCK_TARGET_VOL1_REG(buck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	       BUCK_TARGET_VOL_MASK, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	ret = lp3971_set_bits(lp3971, LP3971_BUCK_VOL_CHANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	       BUCK_VOL_CHANGE_FLAG_MASK << BUCK_VOL_CHANGE_SHIFT(buck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	       BUCK_VOL_CHANGE_FLAG_GO << BUCK_VOL_CHANGE_SHIFT(buck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return lp3971_set_bits(lp3971, LP3971_BUCK_VOL_CHANGE_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	       BUCK_VOL_CHANGE_FLAG_MASK << BUCK_VOL_CHANGE_SHIFT(buck),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	       0 << BUCK_VOL_CHANGE_SHIFT(buck));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static const struct regulator_ops lp3971_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	.list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	.map_voltage = regulator_map_voltage_ascend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	.is_enabled = lp3971_dcdc_is_enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	.enable = lp3971_dcdc_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	.disable = lp3971_dcdc_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	.get_voltage_sel = lp3971_dcdc_get_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	.set_voltage_sel = lp3971_dcdc_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct regulator_desc regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		.name = "LDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 		.id = LP3971_LDO1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		.ops = &lp3971_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 		.n_voltages = ARRAY_SIZE(ldo123_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 		.volt_table = ldo123_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		.name = "LDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 		.id = LP3971_LDO2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		.ops = &lp3971_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 		.n_voltages = ARRAY_SIZE(ldo123_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		.volt_table = ldo123_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		.name = "LDO3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		.id = LP3971_LDO3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		.ops = &lp3971_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		.n_voltages = ARRAY_SIZE(ldo123_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		.volt_table = ldo123_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		.name = "LDO4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		.id = LP3971_LDO4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 		.ops = &lp3971_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		.n_voltages = ARRAY_SIZE(ldo45_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		.volt_table = ldo45_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 		.name = "LDO5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 		.id = LP3971_LDO5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		.ops = &lp3971_ldo_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		.n_voltages = ARRAY_SIZE(ldo45_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 		.volt_table = ldo45_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.name = "DCDC1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.id = LP3971_DCDC1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.ops = &lp3971_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.n_voltages = ARRAY_SIZE(buck_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.volt_table = buck_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.name = "DCDC2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.id = LP3971_DCDC2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.ops = &lp3971_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		.n_voltages = ARRAY_SIZE(buck_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 		.volt_table = buck_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 		.name = "DCDC3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		.id = LP3971_DCDC3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		.ops = &lp3971_dcdc_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		.n_voltages = ARRAY_SIZE(buck_voltage_map),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.volt_table = buck_voltage_map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static int lp3971_i2c_read(struct i2c_client *i2c, char reg, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	u16 *dest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	ret = i2c_smbus_read_byte_data(i2c, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	*dest = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int lp3971_i2c_write(struct i2c_client *i2c, char reg, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	const u16 *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	if (count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return i2c_smbus_write_byte_data(i2c, reg, *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static u8 lp3971_reg_read(struct lp3971 *lp3971, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	u16 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	mutex_lock(&lp3971->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	lp3971_i2c_read(lp3971->i2c, reg, 1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	dev_dbg(lp3971->dev, "reg read 0x%02x -> 0x%02x\n", (int)reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 		(unsigned)val&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	mutex_unlock(&lp3971->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	return val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int lp3971_set_bits(struct lp3971 *lp3971, u8 reg, u16 mask, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	mutex_lock(&lp3971->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	ret = lp3971_i2c_read(lp3971->i2c, reg, 1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 		tmp = (tmp & ~mask) | val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		ret = lp3971_i2c_write(lp3971->i2c, reg, 1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		dev_dbg(lp3971->dev, "reg write 0x%02x -> 0x%02x\n", (int)reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 			(unsigned)val&0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	mutex_unlock(&lp3971->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int setup_regulators(struct lp3971 *lp3971,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 				      struct lp3971_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	/* Instantiate the regulators */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	for (i = 0; i < pdata->num_regulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		struct lp3971_regulator_subdev *reg = &pdata->regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 		struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		config.dev = lp3971->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		config.init_data = reg->initdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		config.driver_data = lp3971;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		rdev = devm_regulator_register(lp3971->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 					       &regulators[reg->id], &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 			err = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 			dev_err(lp3971->dev, "regulator init failed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 				err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 			return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static int lp3971_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	struct lp3971 *lp3971;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	struct lp3971_platform_data *pdata = dev_get_platdata(&i2c->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		dev_dbg(&i2c->dev, "No platform init data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	lp3971 = devm_kzalloc(&i2c->dev, sizeof(struct lp3971), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	if (lp3971 == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	lp3971->i2c = i2c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	lp3971->dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	mutex_init(&lp3971->io_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	/* Detect LP3971 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	ret = lp3971_i2c_read(i2c, LP3971_SYS_CONTROL1_REG, 1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (ret == 0 && (val & SYS_CONTROL1_INIT_MASK) != SYS_CONTROL1_INIT_VAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		dev_err(&i2c->dev, "failed to detect device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	ret = setup_regulators(lp3971, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	i2c_set_clientdata(i2c, lp3971);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) static const struct i2c_device_id lp3971_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	{ "lp3971", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) MODULE_DEVICE_TABLE(i2c, lp3971_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct i2c_driver lp3971_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 		.name = "LP3971",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 	.probe_new = lp3971_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.id_table = lp3971_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) module_i2c_driver(lp3971_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_AUTHOR("Marek Szyprowski <m.szyprowski@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_DESCRIPTION("LP3971 PMIC driver");