^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * isl9305 - Intersil ISL9305 DCDC regulator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2014 Linaro Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Mark Brown <broonie@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_data/isl9305.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ISL9305_DCD1OUT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ISL9305_DCD2OUT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ISL9305_LDO1OUT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ISL9305_LDO2OUT 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ISL9305_DCD_PARAMETER 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ISL9305_SYSTEM_PARAMETER 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ISL9305_DCD_SRCTL 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ISL9305_MAX_REG ISL9305_DCD_SRCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DCD_PARAMETER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ISL9305_DCD_PHASE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ISL9305_DCD2_ULTRA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ISL9305_DCD1_ULTRA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ISL9305_DCD2_BLD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ISL9305_DCD1_BLD 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ISL9305_DCD2_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ISL9305_DCD1_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * SYSTEM_PARAMETER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ISL9305_I2C_EN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ISL9305_DCDPOR_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ISL9305_LDO2_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ISL9305_LDO1_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ISL9305_DCD2_EN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ISL9305_DCD1_EN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * DCD_SRCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ISL9305_DCD2SR_MASK 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISL9305_DCD1SR_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static const struct regulator_ops isl9305_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static const struct regulator_desc isl9305_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) [ISL9305_DCD1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) .name = "DCD1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) .of_match = of_match_ptr("dcd1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) .regulators_node = of_match_ptr("regulators"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) .n_voltages = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) .min_uV = 825000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) .uV_step = 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .vsel_reg = ISL9305_DCD1OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .vsel_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) .enable_reg = ISL9305_SYSTEM_PARAMETER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) .enable_mask = ISL9305_DCD1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) .supply_name = "VINDCD1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .ops = &isl9305_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) [ISL9305_DCD2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .name = "DCD2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .of_match = of_match_ptr("dcd2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .regulators_node = of_match_ptr("regulators"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .n_voltages = 0x70,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .min_uV = 825000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .uV_step = 25000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) .vsel_reg = ISL9305_DCD2OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .vsel_mask = 0x7f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .enable_reg = ISL9305_SYSTEM_PARAMETER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) .enable_mask = ISL9305_DCD2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .supply_name = "VINDCD2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) .ops = &isl9305_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) [ISL9305_LDO1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) .name = "LDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) .of_match = of_match_ptr("ldo1"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) .regulators_node = of_match_ptr("regulators"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) .n_voltages = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) .min_uV = 900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) .uV_step = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .vsel_reg = ISL9305_LDO1OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .vsel_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .enable_reg = ISL9305_SYSTEM_PARAMETER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .enable_mask = ISL9305_LDO1_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .supply_name = "VINLDO1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .ops = &isl9305_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) [ISL9305_LDO2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .name = "LDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .of_match = of_match_ptr("ldo2"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .regulators_node = of_match_ptr("regulators"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .n_voltages = 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .min_uV = 900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .uV_step = 50000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .vsel_reg = ISL9305_LDO2OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .vsel_mask = 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .enable_reg = ISL9305_SYSTEM_PARAMETER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .enable_mask = ISL9305_LDO2_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .supply_name = "VINLDO2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .ops = &isl9305_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static const struct regmap_config isl9305_regmap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .max_register = ISL9305_MAX_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .cache_type = REGCACHE_RBTREE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static int isl9305_i2c_probe(struct i2c_client *i2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct isl9305_pdata *pdata = i2c->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) regmap = devm_regmap_init_i2c(i2c, &isl9305_regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (IS_ERR(regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = PTR_ERR(regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dev_err(&i2c->dev, "Failed to create regmap: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) config.dev = &i2c->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) for (i = 0; i < ARRAY_SIZE(isl9305_regulators); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) config.init_data = pdata->init_data[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) config.init_data = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rdev = devm_regulator_register(&i2c->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) &isl9305_regulators[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) dev_err(&i2c->dev, "Failed to register %s: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) isl9305_regulators[i].name, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static const struct of_device_id isl9305_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { .compatible = "isl,isl9305" }, /* for backward compat., don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { .compatible = "isil,isl9305" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { .compatible = "isl,isl9305h" }, /* for backward compat., don't use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { .compatible = "isil,isl9305h" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) MODULE_DEVICE_TABLE(of, isl9305_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct i2c_device_id isl9305_i2c_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { "isl9305", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { "isl9305h", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MODULE_DEVICE_TABLE(i2c, isl9305_i2c_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static struct i2c_driver isl9305_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .name = "isl9305",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .of_match_table = of_match_ptr(isl9305_dt_ids),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .probe_new = isl9305_i2c_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .id_table = isl9305_i2c_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) module_i2c_driver(isl9305_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MODULE_AUTHOR("Mark Brown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MODULE_DESCRIPTION("Intersil ISL9305 DCDC regulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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