Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * da9211-regulator.h - Regulator definitions for DA9211/DA9212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * /DA9213/DA9223/DA9214/DA9224/DA9215/DA9225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015  Dialog Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __DA9211_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __DA9211_REGISTERS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* Page selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define	DA9211_REG_PAGE_CON			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) /* System Control and Event Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	DA9211_REG_STATUS_A			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	DA9211_REG_STATUS_B			0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define	DA9211_REG_EVENT_A			0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define	DA9211_REG_EVENT_B			0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define	DA9211_REG_MASK_A			0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define	DA9211_REG_MASK_B			0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define	DA9211_REG_CONTROL_A		0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* GPIO Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	DA9211_REG_GPIO_0_1			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	DA9211_REG_GPIO_2_3			0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	DA9211_REG_GPIO_4			0x5A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* Regulator Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	DA9211_REG_BUCKA_CONT			0x5D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	DA9211_REG_BUCKB_CONT			0x5E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	DA9211_REG_BUCK_ILIM			0xD0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define	DA9211_REG_BUCKA_CONF			0xD1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define	DA9211_REG_BUCKB_CONF			0xD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	DA9211_REG_BUCK_CONF			0xD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	DA9211_REG_VBACKA_MAX			0xD5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define	DA9211_REG_VBACKB_MAX			0xD6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	DA9211_REG_VBUCKA_A				0xD7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	DA9211_REG_VBUCKA_B				0xD8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	DA9211_REG_VBUCKB_A				0xD9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	DA9211_REG_VBUCKB_B				0xDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* I2C Interface Settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DA9211_REG_INTERFACE			0x105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* BUCK Phase Selection*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DA9211_REG_CONFIG_E			0x147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	DA9211_REG_DEVICE_ID			0x201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * Registers bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* DA9211_REG_PAGE_CON (addr=0x00) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	DA9211_REG_PAGE_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	DA9211_REG_PAGE_MASK			0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* On I2C registers 0x00 - 0xFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	DA9211_REG_PAGE0			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* On I2C registers 0x100 - 0x1FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	DA9211_REG_PAGE2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	DA9211_PAGE_WRITE_MODE			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	DA9211_REPEAT_WRITE_MODE		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	DA9211_PAGE_REVERT			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* DA9211_REG_STATUS_A (addr=0x50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	DA9211_GPI0				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	DA9211_GPI1				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	DA9211_GPI2				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	DA9211_GPI3				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define	DA9211_GPI4				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* DA9211_REG_EVENT_A (addr=0x52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define	DA9211_E_GPI0				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define	DA9211_E_GPI1				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define	DA9211_E_GPI2				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define	DA9211_E_GPI3				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define	DA9211_E_GPI4				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define	DA9211_E_UVLO_IO			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* DA9211_REG_EVENT_B (addr=0x53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define	DA9211_E_PWRGOOD_A			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define	DA9211_E_PWRGOOD_B			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define	DA9211_E_TEMP_WARN			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define	DA9211_E_TEMP_CRIT			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define	DA9211_E_OV_CURR_A			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	DA9211_E_OV_CURR_B			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* DA9211_REG_MASK_A (addr=0x54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define	DA9211_M_GPI0				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define	DA9211_M_GPI1				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	DA9211_M_GPI2				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	DA9211_M_GPI3				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	DA9211_M_GPI4				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	DA9211_M_UVLO_IO			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* DA9211_REG_MASK_B (addr=0x55) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	DA9211_M_PWRGOOD_A			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	DA9211_M_PWRGOOD_B			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	DA9211_M_TEMP_WARN			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	DA9211_M_TEMP_CRIT			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define	DA9211_M_OV_CURR_A			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define	DA9211_M_OV_CURR_B			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* DA9211_REG_CONTROL_A (addr=0x56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define	DA9211_DEBOUNCING_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define	DA9211_DEBOUNCING_MASK		0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define	DA9211_SLEW_RATE_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	DA9211_SLEW_RATE_A_MASK		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define	DA9211_SLEW_RATE_B_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define	DA9211_SLEW_RATE_B_MASK		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define	DA9211_V_LOCK				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* DA9211_REG_GPIO_0_1 (addr=0x58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define	DA9211_GPIO0_PIN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define	DA9211_GPIO0_PIN_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define	DA9211_GPIO0_PIN_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define	DA9211_GPIO0_PIN_GPO_OD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	DA9211_GPIO0_PIN_GPO		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define	DA9211_GPIO0_TYPE			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define	DA9211_GPIO0_TYPE_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define	DA9211_GPIO0_TYPE_GPO		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	DA9211_GPIO0_MODE			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define	DA9211_GPIO1_PIN_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define	DA9211_GPIO1_PIN_MASK		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define	DA9211_GPIO1_PIN_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define	DA9211_GPIO1_PIN_VERROR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define	DA9211_GPIO1_PIN_GPO_OD		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define	DA9211_GPIO1_PIN_GPO		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	DA9211_GPIO1_TYPE_SHIFT		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	DA9211_GPIO1_TYPE_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	DA9211_GPIO1_TYPE_GPO		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	DA9211_GPIO1_MODE			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* DA9211_REG_GPIO_2_3 (addr=0x59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	DA9211_GPIO2_PIN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define	DA9211_GPIO2_PIN_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	DA9211_GPIO2_PIN_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define	DA9211_GPIO5_PIN_BUCK_CLK	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define	DA9211_GPIO2_PIN_GPO_OD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define	DA9211_GPIO2_PIN_GPO		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define	DA9211_GPIO2_TYPE			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	DA9211_GPIO2_TYPE_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define	DA9211_GPIO2_TYPE_GPO		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define	DA9211_GPIO2_MODE			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define	DA9211_GPIO3_PIN_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define	DA9211_GPIO3_PIN_MASK		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define	DA9211_GPIO3_PIN_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define	DA9211_GPIO3_PIN_IERROR		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define	DA9211_GPIO3_PIN_GPO_OD		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define	DA9211_GPIO3_PIN_GPO		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define	DA9211_GPIO3_TYPE_SHIFT		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define	DA9211_GPIO3_TYPE_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define	DA9211_GPIO3_TYPE_GPO		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define	DA9211_GPIO3_MODE			0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* DA9211_REG_GPIO_4 (addr=0x5A) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define	DA9211_GPIO4_PIN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define	DA9211_GPIO4_PIN_MASK		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define	DA9211_GPIO4_PIN_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define	DA9211_GPIO4_PIN_GPO_OD		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define	DA9211_GPIO4_PIN_GPO		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define	DA9211_GPIO4_TYPE			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define	DA9211_GPIO4_TYPE_GPI		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define	DA9211_GPIO4_TYPE_GPO		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define	DA9211_GPIO4_MODE			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* DA9211_REG_BUCKA_CONT (addr=0x5D) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define	DA9211_BUCKA_EN				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define	DA9211_BUCKA_GPI_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DA9211_BUCKA_GPI_MASK		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define	DA9211_BUCKA_GPI_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define	DA9211_BUCKA_GPI_GPIO0		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define	DA9211_BUCKA_GPI_GPIO1		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define	DA9211_BUCKA_GPI_GPIO3		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define	DA9211_BUCKA_PD_DIS			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define	DA9211_VBUCKA_SEL			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define	DA9211_VBUCKA_SEL_A			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define	DA9211_VBUCKA_SEL_B			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define	DA9211_VBUCKA_GPI_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define	DA9211_VBUCKA_GPI_MASK		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define	DA9211_VBUCKA_GPI_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define	DA9211_VBUCKA_GPI_GPIO1		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define	DA9211_VBUCKA_GPI_GPIO2		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define	DA9211_VBUCKA_GPI_GPIO4		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* DA9211_REG_BUCKB_CONT (addr=0x5E) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define	DA9211_BUCKB_EN				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define	DA9211_BUCKB_GPI_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define DA9211_BUCKB_GPI_MASK		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define	DA9211_BUCKB_GPI_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define	DA9211_BUCKB_GPI_GPIO0		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define	DA9211_BUCKB_GPI_GPIO1		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define	DA9211_BUCKB_GPI_GPIO3		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define	DA9211_BUCKB_PD_DIS			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define	DA9211_VBUCKB_SEL			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define	DA9211_VBUCKB_SEL_A			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define	DA9211_VBUCKB_SEL_B			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define	DA9211_VBUCKB_GPI_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define	DA9211_VBUCKB_GPI_MASK		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define	DA9211_VBUCKB_GPI_OFF		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define	DA9211_VBUCKB_GPI_GPIO1		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define	DA9211_VBUCKB_GPI_GPIO2		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define	DA9211_VBUCKB_GPI_GPIO4		0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* DA9211_REG_BUCK_ILIM (addr=0xD0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define DA9211_BUCKA_ILIM_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define DA9211_BUCKA_ILIM_MASK			0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define DA9211_BUCKB_ILIM_SHIFT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DA9211_BUCKB_ILIM_MASK			0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* DA9211_REG_BUCKA_CONF (addr=0xD1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define DA9211_BUCKA_MODE_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DA9211_BUCKA_MODE_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define	DA9211_BUCKA_MODE_MANUAL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define	DA9211_BUCKA_MODE_SLEEP			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define	DA9211_BUCKA_MODE_SYNC			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define	DA9211_BUCKA_MODE_AUTO			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DA9211_BUCKA_UP_CTRL_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DA9211_BUCKA_UP_CTRL_MASK		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DA9211_BUCKA_DOWN_CTRL_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DA9211_BUCKA_DOWN_CTRL_MASK		0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* DA9211_REG_BUCKB_CONF (addr=0xD2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DA9211_BUCKB_MODE_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define DA9211_BUCKB_MODE_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define	DA9211_BUCKB_MODE_MANUAL		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define	DA9211_BUCKB_MODE_SLEEP			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define	DA9211_BUCKB_MODE_SYNC			0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define	DA9211_BUCKB_MODE_AUTO			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DA9211_BUCKB_UP_CTRL_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define DA9211_BUCKB_UP_CTRL_MASK		0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DA9211_BUCKB_DOWN_CTRL_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DA9211_BUCKB_DOWN_CTRL_MASK		0xE0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* DA9211_REG_BUCK_CONF (addr=0xD3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DA9211_PHASE_SEL_A_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DA9211_PHASE_SEL_A_MASK			0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DA9211_PHASE_SEL_B_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DA9211_PHASE_SEL_B_MASK			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DA9211_PH_SH_EN_A_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DA9211_PH_SH_EN_A_MASK			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DA9211_PH_SH_EN_B_SHIFT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DA9211_PH_SH_EN_B_MASK			0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* DA9211_REG_VBUCKA_MAX (addr=0xD5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DA9211_VBUCKA_BASE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DA9211_VBUCKA_BASE_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* DA9211_REG_VBUCKB_MAX (addr=0xD6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DA9211_VBUCKB_BASE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DA9211_VBUCKB_BASE_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* DA9211_REG_VBUCKA/B_A/B (addr=0xD7/0xD8/0xD9/0xDA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DA9211_VBUCK_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DA9211_VBUCK_MASK			0x7F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DA9211_VBUCK_BIAS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DA9211_BUCK_SL				0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* DA9211_REG_INTERFACE (addr=0x105) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define DA9211_IF_BASE_ADDR_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define DA9211_IF_BASE_ADDR_MASK		0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* DA9211_REG_CONFIG_E (addr=0x147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define DA9211_SLAVE_SEL			0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #endif	/* __DA9211_REGISTERS_H__ */