Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // da9052-regulator.c: Regulator driver for DA9052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright(c) 2011 Dialog Semiconductor Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) // Author: David Dajun Chen <dchen@diasemi.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/mfd/da9052/da9052.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/mfd/da9052/reg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/mfd/da9052/pdata.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* Buck step size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define DA9052_BUCK_PERI_3uV_STEP		100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define DA9052_BUCK_PERI_REG_MAP_UPTO_3uV	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define DA9052_CONST_3uV			3000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define DA9052_MIN_UA		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define DA9052_MAX_UA		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define DA9052_CURRENT_RANGE	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) /* Bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DA9052_BUCK_ILIM_MASK_EVEN	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define DA9052_BUCK_ILIM_MASK_ODD	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* DA9052 REGULATOR IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define DA9052_ID_BUCK1		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define DA9052_ID_BUCK2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define DA9052_ID_BUCK3		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define DA9052_ID_BUCK4		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define DA9052_ID_LDO1		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define DA9052_ID_LDO2		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DA9052_ID_LDO3		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define DA9052_ID_LDO4		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define DA9052_ID_LDO5		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define DA9052_ID_LDO6		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define DA9052_ID_LDO7		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define DA9052_ID_LDO8		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define DA9052_ID_LDO9		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define DA9052_ID_LDO10		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) static const u32 da9052_current_limits[3][4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	{700000, 800000, 1000000, 1200000},	/* DA9052-BC BUCKs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	{1600000, 2000000, 2400000, 3000000},	/* DA9053-AA/Bx BUCK-CORE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	{800000, 1000000, 1200000, 1500000},	/* DA9053-AA/Bx BUCK-PRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 						 * BUCK-MEM and BUCK-PERI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 						*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) struct da9052_regulator_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct regulator_desc reg_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int step_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	int min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	int max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	unsigned char activate_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) struct da9052_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct da9052 *da9052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct da9052_regulator_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) static int verify_range(struct da9052_regulator_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 			 int min_uV, int max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	if (min_uV > info->max_uV || max_uV < info->min_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) static int da9052_dcdc_get_current_limit(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int offset = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int ret, row = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	ret = da9052_reg_read(regulator->da9052, DA9052_BUCKA_REG + offset/2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	/* Determine the even or odd position of the buck current limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * register field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	if (offset % 2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		ret = (ret & DA9052_BUCK_ILIM_MASK_EVEN) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		ret = (ret & DA9052_BUCK_ILIM_MASK_ODD) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	/* Select the appropriate current limit range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	if (regulator->da9052->chip_id == DA9052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		row = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	else if (offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 		row = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	return da9052_current_limits[row][ret];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static int da9052_dcdc_set_current_limit(struct regulator_dev *rdev, int min_uA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 					  int max_uA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int offset = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	int reg_val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int i, row = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	/* Select the appropriate current limit range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	if (regulator->da9052->chip_id == DA9052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		row = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	else if (offset == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 		row = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	for (i = DA9052_CURRENT_RANGE - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		if ((min_uA <= da9052_current_limits[row][i]) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		    (da9052_current_limits[row][i] <= max_uA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			reg_val = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	/* Determine the even or odd position of the buck current limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	 * register field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	if (offset % 2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		return da9052_reg_update(regulator->da9052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 					 DA9052_BUCKA_REG + offset/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 					 DA9052_BUCK_ILIM_MASK_EVEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 					 reg_val << 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		return da9052_reg_update(regulator->da9052,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 					 DA9052_BUCKA_REG + offset/2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 					 DA9052_BUCK_ILIM_MASK_ODD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 					 reg_val << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int da9052_list_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct da9052_regulator_info *info = regulator->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	int volt_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if ((id == DA9052_ID_BUCK4) && (regulator->da9052->chip_id == DA9052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		&& (selector >= DA9052_BUCK_PERI_REG_MAP_UPTO_3uV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		volt_uV = ((DA9052_BUCK_PERI_REG_MAP_UPTO_3uV * info->step_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			  + info->min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		volt_uV += (selector - DA9052_BUCK_PERI_REG_MAP_UPTO_3uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 				    * (DA9052_BUCK_PERI_3uV_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 		volt_uV = (selector * info->step_uV) + info->min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	if (volt_uV > info->max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	return volt_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static int da9052_map_voltage(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			      int min_uV, int max_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	struct da9052_regulator_info *info = regulator->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	int ret, sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	ret = verify_range(info, min_uV, max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	if (min_uV < info->min_uV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 		min_uV = info->min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	if ((id == DA9052_ID_BUCK4) && (regulator->da9052->chip_id == DA9052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 		&& (min_uV >= DA9052_CONST_3uV)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 			sel = DA9052_BUCK_PERI_REG_MAP_UPTO_3uV +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 			      DIV_ROUND_UP(min_uV - DA9052_CONST_3uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 					   DA9052_BUCK_PERI_3uV_STEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		sel = DIV_ROUND_UP(min_uV - info->min_uV, info->step_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = da9052_list_voltage(rdev, sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	return sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static int da9052_regulator_set_voltage_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 					    unsigned int selector)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct da9052_regulator_info *info = regulator->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	ret = da9052_reg_update(regulator->da9052, rdev->desc->vsel_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 				rdev->desc->vsel_mask, selector);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	/* Some LDOs and DCDCs are DVC controlled which requires enabling of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	 * the activate bit to implment the changes on the output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	case DA9052_ID_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	case DA9052_ID_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	case DA9052_ID_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	case DA9052_ID_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	case DA9052_ID_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		ret = da9052_reg_update(regulator->da9052, DA9052_SUPPLY_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 					info->activate_bit, info->activate_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int da9052_regulator_set_voltage_time_sel(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 						 unsigned int old_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 						 unsigned int new_sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	struct da9052_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	struct da9052_regulator_info *info = regulator->info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	/* The DVC controlled LDOs and DCDCs ramp with 6.25mV/µs after enabling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	 * the activate bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	case DA9052_ID_BUCK1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	case DA9052_ID_BUCK2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	case DA9052_ID_BUCK3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	case DA9052_ID_LDO2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	case DA9052_ID_LDO3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 		ret = DIV_ROUND_UP(abs(new_sel - old_sel) * info->step_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 				   6250);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static const struct regulator_ops da9052_dcdc_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	.get_current_limit = da9052_dcdc_get_current_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	.set_current_limit = da9052_dcdc_set_current_limit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	.list_voltage = da9052_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	.map_voltage = da9052_map_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	.set_voltage_sel = da9052_regulator_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	.set_voltage_time_sel = da9052_regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static const struct regulator_ops da9052_ldo_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	.list_voltage = da9052_list_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	.map_voltage = da9052_map_voltage,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	.set_voltage_sel = da9052_regulator_set_voltage_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	.set_voltage_time_sel = da9052_regulator_set_voltage_time_sel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	.is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	.enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	.disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define DA9052_LDO(_id, _name, step, min, max, sbits, ebits, abits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	.reg_desc = {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		.name = #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		.of_match = of_match_ptr(#_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 		.regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 		.ops = &da9052_ldo_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		.id = DA9052_ID_##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		.n_voltages = (max - min) / step + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		.vsel_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		.vsel_mask = (1 << (sbits)) - 1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 		.enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		.enable_mask = 1 << (ebits),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	.min_uV = (min) * 1000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	.max_uV = (max) * 1000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	.step_uV = (step) * 1000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	.activate_bit = (abits),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DA9052_DCDC(_id, _name, step, min, max, sbits, ebits, abits) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	.reg_desc = {\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		.name = #_name,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		.of_match = of_match_ptr(#_name),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		.regulators_node = of_match_ptr("regulators"),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 		.ops = &da9052_dcdc_ops,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		.type = REGULATOR_VOLTAGE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		.id = DA9052_ID_##_id,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 		.n_voltages = (max - min) / step + 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 		.owner = THIS_MODULE,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 		.vsel_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		.vsel_mask = (1 << (sbits)) - 1,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		.enable_reg = DA9052_BUCKCORE_REG + DA9052_ID_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 		.enable_mask = 1 << (ebits),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	},\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	.min_uV = (min) * 1000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	.max_uV = (max) * 1000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	.step_uV = (step) * 1000,\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	.activate_bit = (abits),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) static struct da9052_regulator_info da9052_regulator_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	DA9052_DCDC(BUCK1, buck1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	DA9052_DCDC(BUCK2, buck2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	DA9052_DCDC(BUCK3, buck3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	DA9052_DCDC(BUCK4, buck4, 50, 1800, 3600, 5, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	DA9052_LDO(LDO1, ldo1, 50, 600, 1800, 5, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 	DA9052_LDO(LDO2, ldo2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	DA9052_LDO(LDO3, ldo3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	DA9052_LDO(LDO4, ldo4, 25, 1725, 3300, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	DA9052_LDO(LDO5, ldo5, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	DA9052_LDO(LDO6, ldo6, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	DA9052_LDO(LDO7, ldo7, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 	DA9052_LDO(LDO8, ldo8, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	DA9052_LDO(LDO9, ldo9, 50, 1250, 3650, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	DA9052_LDO(LDO10, ldo10, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static struct da9052_regulator_info da9053_regulator_info[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	DA9052_DCDC(BUCK1, buck1, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBCOREGO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	DA9052_DCDC(BUCK2, buck2, 25, 500, 2075, 6, 6, DA9052_SUPPLY_VBPROGO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	DA9052_DCDC(BUCK3, buck3, 25, 950, 2525, 6, 6, DA9052_SUPPLY_VBMEMGO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	DA9052_DCDC(BUCK4, buck4, 25, 950, 2525, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	DA9052_LDO(LDO1, ldo1, 50, 600, 1800, 5, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	DA9052_LDO(LDO2, ldo2, 25, 600, 1800, 6, 6, DA9052_SUPPLY_VLDO2GO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	DA9052_LDO(LDO3, ldo3, 25, 1725, 3300, 6, 6, DA9052_SUPPLY_VLDO3GO),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	DA9052_LDO(LDO4, ldo4, 25, 1725, 3300, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	DA9052_LDO(LDO5, ldo5, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	DA9052_LDO(LDO6, ldo6, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	DA9052_LDO(LDO7, ldo7, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	DA9052_LDO(LDO8, ldo8, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	DA9052_LDO(LDO9, ldo9, 50, 1250, 3650, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	DA9052_LDO(LDO10, ldo10, 50, 1200, 3600, 6, 6, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static inline struct da9052_regulator_info *find_regulator_info(u8 chip_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 								 int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	struct da9052_regulator_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	switch (chip_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	case DA9052:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 		for (i = 0; i < ARRAY_SIZE(da9052_regulator_info); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 			info = &da9052_regulator_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			if (info->reg_desc.id == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 				return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	case DA9053_AA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	case DA9053_BA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	case DA9053_BB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	case DA9053_BC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		for (i = 0; i < ARRAY_SIZE(da9053_regulator_info); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			info = &da9053_regulator_info[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 			if (info->reg_desc.id == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 				return info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int da9052_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	const struct mfd_cell *cell = mfd_get_cell(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	struct regulator_config config = { };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	struct da9052_regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	struct da9052 *da9052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	struct da9052_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	regulator = devm_kzalloc(&pdev->dev, sizeof(struct da9052_regulator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 				 GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (!regulator)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	da9052 = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	pdata = dev_get_platdata(da9052->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 	regulator->da9052 = da9052;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 	regulator->info = find_regulator_info(regulator->da9052->chip_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 					      cell->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	if (regulator->info == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		dev_err(&pdev->dev, "invalid regulator ID specified\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 	config.dev = da9052->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	config.driver_data = regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 	config.regmap = da9052->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	if (pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		config.init_data = pdata->regulators[cell->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	regulator->rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 						  &regulator->info->reg_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 						  &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	if (IS_ERR(regulator->rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 		dev_err(&pdev->dev, "failed to register regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			regulator->info->reg_desc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 		return PTR_ERR(regulator->rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	platform_set_drvdata(pdev, regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) static struct platform_driver da9052_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	.probe = da9052_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		.name = "da9052-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int __init da9052_regulator_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	return platform_driver_register(&da9052_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) subsys_initcall(da9052_regulator_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void __exit da9052_regulator_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	platform_driver_unregister(&da9052_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) module_exit(da9052_regulator_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) MODULE_AUTHOR("David Dajun Chen <dchen@diasemi.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) MODULE_DESCRIPTION("Power Regulator driver for Dialog DA9052 PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) MODULE_ALIAS("platform:da9052-regulator");