^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Motorola CPCAP PMIC regulator driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Based on cpcap-regulator.c from Motorola Linux kernel tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009-2011 Motorola, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Rewritten for mainline kernel to use device tree and regmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2017 Tony Lindgren <tony@atomide.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mfd/motorola-cpcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Resource assignment register bits. These seem to control the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * idle modes adn are used at least for omap4.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* CPCAP_REG_ASSIGN2 bits - Resource Assignment 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CPCAP_BIT_VSDIO_SEL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CPCAP_BIT_VDIG_SEL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPCAP_BIT_VCAM_SEL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPCAP_BIT_SW6_SEL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPCAP_BIT_SW5_SEL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CPCAP_BIT_SW4_SEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CPCAP_BIT_SW3_SEL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CPCAP_BIT_SW2_SEL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CPCAP_BIT_SW1_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* CPCAP_REG_ASSIGN3 bits - Resource Assignment 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CPCAP_BIT_VUSBINT2_SEL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CPCAP_BIT_VUSBINT1_SEL BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CPCAP_BIT_VVIB_SEL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CPCAP_BIT_VWLAN1_SEL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CPCAP_BIT_VRF1_SEL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CPCAP_BIT_VHVIO_SEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CPCAP_BIT_VDAC_SEL BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CPCAP_BIT_VUSB_SEL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CPCAP_BIT_VSIM_SEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CPCAP_BIT_VRFREF_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CPCAP_BIT_VPLL_SEL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CPCAP_BIT_VFUSE_SEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CPCAP_BIT_VCSI_SEL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CPCAP_BIT_SPARE_14_2 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CPCAP_BIT_VWLAN2_SEL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CPCAP_BIT_VRF2_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* CPCAP_REG_ASSIGN4 bits - Resource Assignment 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CPCAP_BIT_VAUDIO_SEL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * Enable register bits. At least CPCAP_BIT_AUDIO_LOW_PWR is generic,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * and not limited to audio regulator. Let's use the Motorola kernel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * naming for now until we have a better understanding of the other
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * enable register bits. No idea why BIT(3) is not defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CPCAP_BIT_AUDIO_LOW_PWR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CPCAP_BIT_AUD_LOWPWR_SPEED BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CPCAP_BIT_VAUDIOPRISTBY BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CPCAP_BIT_VAUDIO_MODE1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CPCAP_BIT_VAUDIO_MODE0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CPCAP_BIT_V_AUDIO_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CPCAP_BIT_AUDIO_NORMAL_MODE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * Off mode configuration bit. Used currently only by SW5 on omap4. There's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * the following comment in Motorola Linux kernel tree for it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * When set in the regulator mode, the regulator assignment will be changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * to secondary when the regulator is disabled. The mode will be set back to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * primary when the regulator is turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CPCAP_REG_OFF_MODE_SEC BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * SoC specific configuration for CPCAP regulator. There are at least three
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * different SoCs each with their own parameters: omap3, omap4 and tegra2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * The assign_reg and assign_mask seem to allow toggling between primary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * and secondary mode that at least omap4 uses for off mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct cpcap_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct regulator_desc rdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const u16 assign_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const u16 assign_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CPCAP_REG(_ID, reg, assignment_reg, assignment_mask, val_tbl, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) mode_mask, volt_mask, mode_val, off_val, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) volt_trans_time) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .rdesc = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) .name = #_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) .of_match = of_match_ptr(#_ID), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) .ops = &cpcap_regulator_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) .id = CPCAP_##_ID, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .n_voltages = ARRAY_SIZE(val_tbl), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .volt_table = (val_tbl), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .vsel_reg = (reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .vsel_mask = (volt_mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .enable_reg = (reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .enable_mask = (mode_mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .enable_val = (mode_val), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .disable_val = (off_val), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .ramp_delay = (volt_trans_time), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .of_map_mode = cpcap_map_mode, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .assign_reg = (assignment_reg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .assign_mask = (assignment_mask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct cpcap_ddata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct regmap *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const struct cpcap_regulator *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) enum cpcap_regulator_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) CPCAP_SW1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) CPCAP_SW2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) CPCAP_SW3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) CPCAP_SW4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) CPCAP_SW5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) CPCAP_SW6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) CPCAP_VCAM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) CPCAP_VCSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) CPCAP_VDAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) CPCAP_VDIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CPCAP_VFUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CPCAP_VHVIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) CPCAP_VSDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) CPCAP_VPLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) CPCAP_VRF1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) CPCAP_VRF2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) CPCAP_VRFREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) CPCAP_VWLAN1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) CPCAP_VWLAN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) CPCAP_VSIM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) CPCAP_VSIMCARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) CPCAP_VVIB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) CPCAP_VUSB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) CPCAP_VAUDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) CPCAP_NR_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * We need to also configure regulator idle mode for SoC off mode if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * CPCAP_REG_OFF_MODE_SEC is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static int cpcap_regulator_enable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) error = regulator_enable_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) regulator->assign_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) regulator->assign_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) regulator_disable_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * We need to also configure regulator idle mode for SoC off mode if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * CPCAP_REG_OFF_MODE_SEC is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static int cpcap_regulator_disable(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct cpcap_regulator *regulator = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) if (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) error = regmap_update_bits(rdev->regmap, regulator->assign_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) regulator->assign_mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) error = regulator_disable_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) if (error && (rdev->desc->enable_val & CPCAP_REG_OFF_MODE_SEC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) regmap_update_bits(rdev->regmap, regulator->assign_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) regulator->assign_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) regulator->assign_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static unsigned int cpcap_map_mode(unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) case CPCAP_BIT_AUDIO_NORMAL_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case CPCAP_BIT_AUDIO_LOW_PWR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return REGULATOR_MODE_INVALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static unsigned int cpcap_regulator_get_mode(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) regmap_read(rdev->regmap, rdev->desc->enable_reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (value & CPCAP_BIT_AUDIO_LOW_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return REGULATOR_MODE_STANDBY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return REGULATOR_MODE_NORMAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static int cpcap_regulator_set_mode(struct regulator_dev *rdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) case REGULATOR_MODE_NORMAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) value = CPCAP_BIT_AUDIO_NORMAL_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) case REGULATOR_MODE_STANDBY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) value = CPCAP_BIT_AUDIO_LOW_PWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CPCAP_BIT_AUDIO_LOW_PWR, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static const struct regulator_ops cpcap_regulator_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) .enable = cpcap_regulator_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) .disable = cpcap_regulator_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) .list_voltage = regulator_list_voltage_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) .map_voltage = regulator_map_voltage_iterate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) .get_mode = cpcap_regulator_get_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) .set_mode = cpcap_regulator_set_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const unsigned int unknown_val_tbl[] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static const unsigned int sw2_sw4_val_tbl[] = { 612500, 625000, 637500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 650000, 662500, 675000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 687500, 700000, 712500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 725000, 737500, 750000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 762500, 775000, 787500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 800000, 812500, 825000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 837500, 850000, 862500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 875000, 887500, 900000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 912500, 925000, 937500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 950000, 962500, 975000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 987500, 1000000, 1012500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 1025000, 1037500, 1050000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 1062500, 1075000, 1087500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 1100000, 1112500, 1125000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 1137500, 1150000, 1162500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 1175000, 1187500, 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 1212500, 1225000, 1237500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 1250000, 1262500, 1275000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 1287500, 1300000, 1312500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 1325000, 1337500, 1350000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 1362500, 1375000, 1387500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 1400000, 1412500, 1425000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 1437500, 1450000, 1462500, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static const unsigned int sw5_val_tbl[] = { 0, 5050000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const unsigned int vcam_val_tbl[] = { 2600000, 2700000, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 2900000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const unsigned int vcsi_val_tbl[] = { 1200000, 1800000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static const unsigned int vdac_val_tbl[] = { 1200000, 1500000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 2500000,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const unsigned int vdig_val_tbl[] = { 1200000, 1350000, 1500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 1875000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static const unsigned int vfuse_val_tbl[] = { 1500000, 1600000, 1700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 1800000, 1900000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 2100000, 2200000, 2300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 2400000, 2500000, 2600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 2700000, 3150000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static const unsigned int vhvio_val_tbl[] = { 2775000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) static const unsigned int vsdio_val_tbl[] = { 1500000, 1600000, 1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 2600000, 2700000, 2800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 2900000, 3000000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const unsigned int vpll_val_tbl[] = { 1200000, 1300000, 1400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 1800000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Quirk: 2775000 is before 2500000 for vrf1 regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const unsigned int vrf1_val_tbl[] = { 2775000, 2500000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static const unsigned int vrf2_val_tbl[] = { 0, 2775000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static const unsigned int vrfref_val_tbl[] = { 2500000, 2775000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static const unsigned int vwlan1_val_tbl[] = { 1800000, 1900000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const unsigned int vwlan2_val_tbl[] = { 2775000, 3000000, 3300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 3300000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static const unsigned int vsim_val_tbl[] = { 1800000, 2900000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static const unsigned int vsimcard_val_tbl[] = { 1800000, 2900000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const unsigned int vvib_val_tbl[] = { 1300000, 1800000, 2000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 3000000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static const unsigned int vusb_val_tbl[] = { 0, 3300000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static const unsigned int vaudio_val_tbl[] = { 0, 2775000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * SoC specific configuration for omap4. The data below is comes from Motorola
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Linux kernel tree. It's basically the values of cpcap_regltr_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * cpcap_regulator_mode_values and cpcap_regulator_off_mode_values, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * CPCAP_REG macro above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * SW1 to SW4 and SW6 seems to be unused for mapphone. Note that VSIM and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * VSIMCARD have a shared resource assignment bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct cpcap_regulator omap4_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) CPCAP_BIT_SW1_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) CPCAP_BIT_SW2_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) CPCAP_BIT_SW3_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) CPCAP_BIT_SW4_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) CPCAP_BIT_SW5_SEL, sw5_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x28, 0, 0x20 | CPCAP_REG_OFF_MODE_SEC, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) CPCAP_BIT_SW6_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x87, 0x30, 0x3, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x47, 0x10, 0x43, 0x41, 350),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x87, 0x30, 0x3, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x87, 0x30, 0x82, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x80, 0xf, 0x80, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x17, 0, 0, 0x12, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x87, 0x38, 0x82, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x43, 0x18, 0x2, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0xac, 0x2, 0x4, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x23, 0x8, 0, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x23, 0x8, 0, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x47, 0x10, 0, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x20c, 0xc0, 0x20c, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0xffff, vsim_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x23, 0x8, 0x3, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0xffff, vsimcard_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x1e80, 0x8, 0x1e00, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x1, 0xc, 0x1, 0, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x11c, 0x40, 0xc, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x16, 0x1, 0x4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static const struct cpcap_regulator xoom_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) CPCAP_REG(SW1, CPCAP_REG_S1C1, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) CPCAP_BIT_SW1_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) CPCAP_REG(SW2, CPCAP_REG_S2C1, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) CPCAP_BIT_SW2_SEL, sw2_sw4_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0xf00, 0x7f, 0x800, 0, 120),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) CPCAP_REG(SW3, CPCAP_REG_S3C, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) CPCAP_BIT_SW3_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) CPCAP_REG(SW4, CPCAP_REG_S4C1, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) CPCAP_BIT_SW4_SEL, sw2_sw4_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0xf00, 0x7f, 0x900, 0, 100),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) CPCAP_REG(SW5, CPCAP_REG_S5C, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) CPCAP_BIT_SW5_SEL, sw5_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x2a, 0, 0x22, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) CPCAP_REG(SW6, CPCAP_REG_S6C, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) CPCAP_BIT_SW6_SEL, unknown_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0, 0, 0, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) CPCAP_REG(VCAM, CPCAP_REG_VCAMC, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) CPCAP_BIT_VCAM_SEL, vcam_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0x87, 0x30, 0x7, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CPCAP_REG(VCSI, CPCAP_REG_VCSIC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) CPCAP_BIT_VCSI_SEL, vcsi_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x47, 0x10, 0x7, 0, 350),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) CPCAP_REG(VDAC, CPCAP_REG_VDACC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) CPCAP_BIT_VDAC_SEL, vdac_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 0x87, 0x30, 0x3, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) CPCAP_REG(VDIG, CPCAP_REG_VDIGC, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) CPCAP_BIT_VDIG_SEL, vdig_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x87, 0x30, 0x5, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) CPCAP_REG(VFUSE, CPCAP_REG_VFUSEC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) CPCAP_BIT_VFUSE_SEL, vfuse_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0x80, 0xf, 0x80, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) CPCAP_REG(VHVIO, CPCAP_REG_VHVIOC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) CPCAP_BIT_VHVIO_SEL, vhvio_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x17, 0, 0x2, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) CPCAP_REG(VSDIO, CPCAP_REG_VSDIOC, CPCAP_REG_ASSIGN2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) CPCAP_BIT_VSDIO_SEL, vsdio_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0x87, 0x38, 0x2, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) CPCAP_BIT_VPLL_SEL, vpll_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x43, 0x18, 0x1, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) CPCAP_REG(VRF1, CPCAP_REG_VRF1C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) CPCAP_BIT_VRF1_SEL, vrf1_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0xac, 0x2, 0xc, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) CPCAP_REG(VRF2, CPCAP_REG_VRF2C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) CPCAP_BIT_VRF2_SEL, vrf2_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x23, 0x8, 0x3, 0, 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) CPCAP_REG(VRFREF, CPCAP_REG_VRFREFC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) CPCAP_BIT_VRFREF_SEL, vrfref_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x23, 0x8, 0x3, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) CPCAP_REG(VWLAN1, CPCAP_REG_VWLAN1C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) CPCAP_BIT_VWLAN1_SEL, vwlan1_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x47, 0x10, 0x5, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) CPCAP_REG(VWLAN2, CPCAP_REG_VWLAN2C, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) CPCAP_BIT_VWLAN2_SEL, vwlan2_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0x20c, 0xc0, 0x8, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) CPCAP_REG(VSIM, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0xffff, vsim_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0x23, 0x8, 0x3, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) CPCAP_REG(VSIMCARD, CPCAP_REG_VSIMC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0xffff, vsimcard_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0x1e80, 0x8, 0x1e00, 0, 420),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) CPCAP_REG(VVIB, CPCAP_REG_VVIBC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) CPCAP_BIT_VVIB_SEL, vvib_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x1, 0xc, 0, 0x1, 500),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) CPCAP_REG(VUSB, CPCAP_REG_VUSBC, CPCAP_REG_ASSIGN3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) CPCAP_BIT_VUSB_SEL, vusb_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0x11c, 0x40, 0xc, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) CPCAP_REG(VAUDIO, CPCAP_REG_VAUDIOC, CPCAP_REG_ASSIGN4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) CPCAP_BIT_VAUDIO_SEL, vaudio_val_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0x16, 0x1, 0x4, 0, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct of_device_id cpcap_regulator_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .compatible = "motorola,cpcap-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .compatible = "motorola,mapphone-cpcap-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .data = omap4_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .compatible = "motorola,xoom-cpcap-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .data = xoom_regulators,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) MODULE_DEVICE_TABLE(of, cpcap_regulator_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int cpcap_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct cpcap_ddata *ddata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) const struct cpcap_regulator *match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct regulator_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) match_data = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!match_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(&pdev->dev, "no configuration data found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (!ddata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ddata->reg = dev_get_regmap(pdev->dev.parent, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) if (!ddata->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ddata->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ddata->soc = match_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) platform_set_drvdata(pdev, ddata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) memset(&config, 0, sizeof(config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) config.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) config.regmap = ddata->reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) for (i = 0; i < CPCAP_NR_REGULATORS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) const struct cpcap_regulator *regulator = &ddata->soc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (!regulator->rdesc.name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (regulator->rdesc.volt_table == unknown_val_tbl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) config.driver_data = (void *)regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ®ulator->rdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(&pdev->dev, "failed to register regulator %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regulator->rdesc.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static struct platform_driver cpcap_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .probe = cpcap_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .name = "cpcap-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .of_match_table = of_match_ptr(cpcap_regulator_id_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) module_platform_driver(cpcap_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) MODULE_ALIAS("platform:cpcap-regulator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_DESCRIPTION("CPCAP regulator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags