^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * AXP20x regulators driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2013 Carlo Caione <carlo@caione.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This file is subject to the terms and conditions of the GNU General
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Public License. See the file "COPYING" in the main directory of this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * archive for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/mfd/axp20x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/regulator/driver.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/regulator/machine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/regulator/of_regulator.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AXP20X_GPIO0_FUNC_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AXP20X_GPIO1_FUNC_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define AXP20X_IO_ENABLED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AXP20X_IO_DISABLED 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define AXP20X_WORKMODE_DCDC2_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AXP20X_WORKMODE_DCDC3_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AXP20X_FREQ_DCDC_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AXP20X_VBUS_IPSOUT_MGMT_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AXP20X_DCDC2_V_OUT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AXP20X_DCDC3_V_OUT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AXP20X_LDO2_V_OUT_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AXP20X_LDO3_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AXP20X_LDO4_V_OUT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AXP20X_LDO5_V_OUT_MASK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AXP20X_PWR_OUT_EXTEN_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define AXP20X_PWR_OUT_DCDC3_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AXP20X_PWR_OUT_LDO2_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AXP20X_PWR_OUT_LDO4_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define AXP20X_PWR_OUT_DCDC2_MASK BIT_MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AXP20X_PWR_OUT_LDO3_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) ((x) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AXP20X_LDO4_V_OUT_1250mV_START 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define AXP20X_LDO4_V_OUT_1250mV_STEPS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define AXP20X_LDO4_V_OUT_1250mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) (AXP20X_LDO4_V_OUT_1250mV_START + AXP20X_LDO4_V_OUT_1250mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define AXP20X_LDO4_V_OUT_1300mV_START 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define AXP20X_LDO4_V_OUT_1300mV_STEPS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AXP20X_LDO4_V_OUT_1300mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) (AXP20X_LDO4_V_OUT_1300mV_START + AXP20X_LDO4_V_OUT_1300mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define AXP20X_LDO4_V_OUT_2500mV_START 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define AXP20X_LDO4_V_OUT_2500mV_STEPS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define AXP20X_LDO4_V_OUT_2500mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) (AXP20X_LDO4_V_OUT_2500mV_START + AXP20X_LDO4_V_OUT_2500mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define AXP20X_LDO4_V_OUT_2700mV_START 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define AXP20X_LDO4_V_OUT_2700mV_STEPS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AXP20X_LDO4_V_OUT_2700mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (AXP20X_LDO4_V_OUT_2700mV_START + AXP20X_LDO4_V_OUT_2700mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define AXP20X_LDO4_V_OUT_3000mV_START 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define AXP20X_LDO4_V_OUT_3000mV_STEPS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AXP20X_LDO4_V_OUT_3000mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) (AXP20X_LDO4_V_OUT_3000mV_START + AXP20X_LDO4_V_OUT_3000mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AXP20X_LDO4_V_OUT_NUM_VOLTAGES 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define AXP22X_IO_ENABLED 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define AXP22X_IO_DISABLED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define AXP22X_WORKMODE_DCDCX_MASK(x) BIT_MASK(x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define AXP22X_MISC_N_VBUSEN_FUNC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define AXP22X_DCDC1_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define AXP22X_DCDC2_V_OUT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define AXP22X_DCDC3_V_OUT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AXP22X_DCDC4_V_OUT_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AXP22X_DCDC5_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AXP22X_DC5LDO_V_OUT_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AXP22X_ALDO1_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define AXP22X_ALDO2_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AXP22X_ALDO3_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AXP22X_DLDO1_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define AXP22X_DLDO2_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AXP22X_DLDO3_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AXP22X_DLDO4_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define AXP22X_ELDO1_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define AXP22X_ELDO2_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AXP22X_ELDO3_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AXP22X_LDO_IO0_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AXP22X_LDO_IO1_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define AXP22X_PWR_OUT_DC5LDO_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define AXP22X_PWR_OUT_DCDC1_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AXP22X_PWR_OUT_DCDC2_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AXP22X_PWR_OUT_DCDC3_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AXP22X_PWR_OUT_DCDC4_MASK BIT_MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AXP22X_PWR_OUT_DCDC5_MASK BIT_MASK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AXP22X_PWR_OUT_ALDO1_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AXP22X_PWR_OUT_ALDO2_MASK BIT_MASK(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AXP22X_PWR_OUT_SW_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AXP22X_PWR_OUT_DC1SW_MASK BIT_MASK(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AXP22X_PWR_OUT_ELDO1_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AXP22X_PWR_OUT_ELDO2_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AXP22X_PWR_OUT_ELDO3_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AXP22X_PWR_OUT_DLDO1_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AXP22X_PWR_OUT_DLDO2_MASK BIT_MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define AXP22X_PWR_OUT_DLDO3_MASK BIT_MASK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define AXP22X_PWR_OUT_DLDO4_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AXP22X_PWR_OUT_ALDO3_MASK BIT_MASK(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AXP803_PWR_OUT_DCDC1_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AXP803_PWR_OUT_DCDC2_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AXP803_PWR_OUT_DCDC3_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AXP803_PWR_OUT_DCDC4_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AXP803_PWR_OUT_DCDC5_MASK BIT_MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AXP803_PWR_OUT_DCDC6_MASK BIT_MASK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AXP803_PWR_OUT_FLDO1_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AXP803_PWR_OUT_FLDO2_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AXP803_DCDC1_V_OUT_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AXP803_DCDC2_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AXP803_DCDC3_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AXP803_DCDC4_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AXP803_DCDC5_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AXP803_DCDC6_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AXP803_FLDO1_V_OUT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AXP803_FLDO2_V_OUT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AXP803_DCDC23_POLYPHASE_DUAL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AXP803_DCDC56_POLYPHASE_DUAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AXP803_DCDC234_500mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AXP803_DCDC234_500mV_STEPS 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AXP803_DCDC234_500mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) (AXP803_DCDC234_500mV_START + AXP803_DCDC234_500mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AXP803_DCDC234_1220mV_START 0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define AXP803_DCDC234_1220mV_STEPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define AXP803_DCDC234_1220mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) (AXP803_DCDC234_1220mV_START + AXP803_DCDC234_1220mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define AXP803_DCDC234_NUM_VOLTAGES 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define AXP803_DCDC5_800mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define AXP803_DCDC5_800mV_STEPS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define AXP803_DCDC5_800mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) (AXP803_DCDC5_800mV_START + AXP803_DCDC5_800mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define AXP803_DCDC5_1140mV_START 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define AXP803_DCDC5_1140mV_STEPS 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define AXP803_DCDC5_1140mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) (AXP803_DCDC5_1140mV_START + AXP803_DCDC5_1140mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define AXP803_DCDC5_NUM_VOLTAGES 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define AXP803_DCDC6_600mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define AXP803_DCDC6_600mV_STEPS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define AXP803_DCDC6_600mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) (AXP803_DCDC6_600mV_START + AXP803_DCDC6_600mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define AXP803_DCDC6_1120mV_START 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define AXP803_DCDC6_1120mV_STEPS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define AXP803_DCDC6_1120mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) (AXP803_DCDC6_1120mV_START + AXP803_DCDC6_1120mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define AXP803_DCDC6_NUM_VOLTAGES 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AXP803_DLDO2_700mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AXP803_DLDO2_700mV_STEPS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AXP803_DLDO2_700mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) (AXP803_DLDO2_700mV_START + AXP803_DLDO2_700mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AXP803_DLDO2_3400mV_START 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AXP803_DLDO2_3400mV_STEPS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AXP803_DLDO2_3400mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) (AXP803_DLDO2_3400mV_START + AXP803_DLDO2_3400mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define AXP803_DLDO2_NUM_VOLTAGES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AXP806_DCDCA_V_CTRL_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AXP806_DCDCB_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AXP806_DCDCC_V_CTRL_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define AXP806_DCDCD_V_CTRL_MASK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AXP806_DCDCE_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AXP806_ALDO1_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AXP806_ALDO2_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AXP806_ALDO3_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AXP806_BLDO1_V_CTRL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AXP806_BLDO2_V_CTRL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AXP806_BLDO3_V_CTRL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AXP806_BLDO4_V_CTRL_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AXP806_CLDO1_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AXP806_CLDO2_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AXP806_CLDO3_V_CTRL_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AXP806_PWR_OUT_DCDCA_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AXP806_PWR_OUT_DCDCB_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AXP806_PWR_OUT_DCDCC_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AXP806_PWR_OUT_DCDCD_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AXP806_PWR_OUT_DCDCE_MASK BIT_MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AXP806_PWR_OUT_ALDO1_MASK BIT_MASK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AXP806_PWR_OUT_ALDO2_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AXP806_PWR_OUT_ALDO3_MASK BIT_MASK(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AXP806_PWR_OUT_BLDO1_MASK BIT_MASK(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AXP806_PWR_OUT_BLDO2_MASK BIT_MASK(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AXP806_PWR_OUT_BLDO3_MASK BIT_MASK(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AXP806_PWR_OUT_BLDO4_MASK BIT_MASK(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AXP806_PWR_OUT_CLDO1_MASK BIT_MASK(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AXP806_PWR_OUT_CLDO2_MASK BIT_MASK(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AXP806_PWR_OUT_CLDO3_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define AXP806_PWR_OUT_SW_MASK BIT_MASK(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AXP806_DCDCAB_POLYPHASE_DUAL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AXP806_DCDCABC_POLYPHASE_TRI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AXP806_DCDCABC_POLYPHASE_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AXP806_DCDCDE_POLYPHASE_DUAL BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AXP806_DCDCA_600mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AXP806_DCDCA_600mV_STEPS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AXP806_DCDCA_600mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) (AXP806_DCDCA_600mV_START + AXP806_DCDCA_600mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AXP806_DCDCA_1120mV_START 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AXP806_DCDCA_1120mV_STEPS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define AXP806_DCDCA_1120mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) (AXP806_DCDCA_1120mV_START + AXP806_DCDCA_1120mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define AXP806_DCDCA_NUM_VOLTAGES 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define AXP806_DCDCD_600mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define AXP806_DCDCD_600mV_STEPS 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AXP806_DCDCD_600mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) (AXP806_DCDCD_600mV_START + AXP806_DCDCD_600mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AXP806_DCDCD_1600mV_START 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AXP806_DCDCD_1600mV_STEPS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define AXP806_DCDCD_1600mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) (AXP806_DCDCD_1600mV_START + AXP806_DCDCD_1600mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define AXP806_DCDCD_NUM_VOLTAGES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AXP809_DCDC4_600mV_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define AXP809_DCDC4_600mV_STEPS 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AXP809_DCDC4_600mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) (AXP809_DCDC4_600mV_START + AXP809_DCDC4_600mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AXP809_DCDC4_1800mV_START 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AXP809_DCDC4_1800mV_STEPS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define AXP809_DCDC4_1800mV_END \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (AXP809_DCDC4_1800mV_START + AXP809_DCDC4_1800mV_STEPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AXP809_DCDC4_NUM_VOLTAGES 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AXP813_DCDC7_V_OUT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AXP813_PWR_OUT_DCDC7_MASK BIT_MASK(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define AXP_DESC_IO(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) _vmask, _ereg, _emask, _enable_val, _disable_val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) [_family##_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .name = (_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .supply_name = (_supply), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .of_match = of_match_ptr(_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .id = _family##_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .n_voltages = (((_max) - (_min)) / (_step) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .min_uV = (_min) * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .uV_step = (_step) * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .vsel_reg = (_vreg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .vsel_mask = (_vmask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .enable_reg = (_ereg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .enable_mask = (_emask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .enable_val = (_enable_val), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .disable_val = (_disable_val), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .ops = &axp20x_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define AXP_DESC(_family, _id, _match, _supply, _min, _max, _step, _vreg, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) _vmask, _ereg, _emask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) [_family##_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .name = (_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .supply_name = (_supply), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .of_match = of_match_ptr(_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .id = _family##_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .n_voltages = (((_max) - (_min)) / (_step) + 1), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .min_uV = (_min) * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .uV_step = (_step) * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .vsel_reg = (_vreg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .vsel_mask = (_vmask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .enable_reg = (_ereg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .enable_mask = (_emask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .ops = &axp20x_ops, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AXP_DESC_SW(_family, _id, _match, _supply, _ereg, _emask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) [_family##_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .name = (_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .supply_name = (_supply), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .of_match = of_match_ptr(_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .id = _family##_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .enable_reg = (_ereg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .enable_mask = (_emask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .ops = &axp20x_ops_sw, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define AXP_DESC_FIXED(_family, _id, _match, _supply, _volt) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) [_family##_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) .name = (_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) .supply_name = (_supply), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) .of_match = of_match_ptr(_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) .id = _family##_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) .n_voltages = 1, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) .min_uV = (_volt) * 1000, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) .ops = &axp20x_ops_fixed \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define AXP_DESC_RANGES(_family, _id, _match, _supply, _ranges, _n_voltages, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) _vreg, _vmask, _ereg, _emask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) [_family##_##_id] = { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .name = (_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) .supply_name = (_supply), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .of_match = of_match_ptr(_match), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .regulators_node = of_match_ptr("regulators"), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .type = REGULATOR_VOLTAGE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .id = _family##_##_id, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .n_voltages = (_n_voltages), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .owner = THIS_MODULE, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .vsel_reg = (_vreg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .vsel_mask = (_vmask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) .enable_reg = (_ereg), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) .enable_mask = (_emask), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) .linear_ranges = (_ranges), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) .n_linear_ranges = ARRAY_SIZE(_ranges), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) .ops = &axp20x_ops_range, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static const int axp209_dcdc2_ldo3_slew_rates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int axp20x_set_ramp_delay(struct regulator_dev *rdev, int ramp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 reg, mask, enable, cfg = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) const int *slew_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int rate_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) case AXP209_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (id == AXP20X_DCDC2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) slew_rates = axp209_dcdc2_ldo3_slew_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) reg = AXP20X_DCDC2_LDO3_V_RAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) mask = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) enable = (ramp > 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (id == AXP20X_LDO3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) slew_rates = axp209_dcdc2_ldo3_slew_rates;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) rate_count = ARRAY_SIZE(axp209_dcdc2_ldo3_slew_rates);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) reg = AXP20X_DCDC2_LDO3_V_RAMP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mask = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) enable = (ramp > 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) AXP20X_DCDC2_LDO3_V_RAMP_LDO3_EN : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (rate_count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Not supported for this regulator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (ramp == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cfg = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) for (i = 0; i < rate_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ramp > slew_rates[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (id == AXP20X_DCDC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cfg = AXP20X_DCDC2_LDO3_V_RAMP_DCDC2_RATE(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cfg = AXP20X_DCDC2_LDO3_V_RAMP_LDO3_RATE(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) if (cfg == 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) dev_err(axp20x->dev, "unsupported ramp value %d", ramp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) cfg |= enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return regmap_update_bits(axp20x->regmap, reg, mask, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int axp20x_regulator_enable_regmap(struct regulator_dev *rdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int id = rdev_get_id(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) case AXP209_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if ((id == AXP20X_LDO3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) rdev->constraints && rdev->constraints->soft_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) int v_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * On some boards, the LDO3 can be overloaded when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * turning on, causing the entire PMIC to shutdown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * without warning. Turning it on at the minimal voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * and then setting the voltage to the requested value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * works reliably.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (regulator_is_enabled_regmap(rdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) v_out = regulator_get_voltage_sel_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (v_out < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return v_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (v_out == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ret = regulator_set_voltage_sel_regmap(rdev, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * A small pause is needed between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * setting the voltage and enabling the LDO to give the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * internal state machine time to process the request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) usleep_range(1000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret |= regulator_enable_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) ret |= regulator_set_voltage_sel_regmap(rdev, v_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* No quirks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return regulator_enable_regmap(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const struct regulator_ops axp20x_ops_fixed = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static const struct regulator_ops axp20x_ops_range = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .list_voltage = regulator_list_voltage_linear_range,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static const struct regulator_ops axp20x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .set_voltage_sel = regulator_set_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .get_voltage_sel = regulator_get_voltage_sel_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .list_voltage = regulator_list_voltage_linear,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .enable = axp20x_regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .set_ramp_delay = axp20x_set_ramp_delay,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct regulator_ops axp20x_ops_sw = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .enable = regulator_enable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .disable = regulator_disable_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .is_enabled = regulator_is_enabled_regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct linear_range axp20x_ldo4_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) REGULATOR_LINEAR_RANGE(1250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) AXP20X_LDO4_V_OUT_1250mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) AXP20X_LDO4_V_OUT_1250mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) REGULATOR_LINEAR_RANGE(1300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) AXP20X_LDO4_V_OUT_1300mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) AXP20X_LDO4_V_OUT_1300mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) REGULATOR_LINEAR_RANGE(2500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) AXP20X_LDO4_V_OUT_2500mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) AXP20X_LDO4_V_OUT_2500mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) REGULATOR_LINEAR_RANGE(2700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) AXP20X_LDO4_V_OUT_2700mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) AXP20X_LDO4_V_OUT_2700mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) REGULATOR_LINEAR_RANGE(3000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) AXP20X_LDO4_V_OUT_3000mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) AXP20X_LDO4_V_OUT_3000mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static const struct regulator_desc axp20x_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) AXP_DESC(AXP20X, DCDC2, "dcdc2", "vin2", 700, 2275, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) AXP20X_DCDC2_V_OUT, AXP20X_DCDC2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) AXP_DESC(AXP20X, DCDC3, "dcdc3", "vin3", 700, 3500, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) AXP20X_DCDC3_V_OUT, AXP20X_DCDC3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_DCDC3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) AXP_DESC_FIXED(AXP20X, LDO1, "ldo1", "acin", 1300),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) AXP_DESC(AXP20X, LDO2, "ldo2", "ldo24in", 1800, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) AXP20X_LDO24_V_OUT, AXP20X_LDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) AXP_DESC(AXP20X, LDO3, "ldo3", "ldo3in", 700, 3500, 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) AXP20X_LDO3_V_OUT, AXP20X_LDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) AXP_DESC_RANGES(AXP20X, LDO4, "ldo4", "ldo24in",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) axp20x_ldo4_ranges, AXP20X_LDO4_V_OUT_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) AXP20X_LDO24_V_OUT, AXP20X_LDO4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) AXP20X_PWR_OUT_CTRL, AXP20X_PWR_OUT_LDO4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) AXP_DESC_IO(AXP20X, LDO5, "ldo5", "ldo5in", 1800, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) AXP20X_LDO5_V_OUT, AXP20X_LDO5_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) AXP20X_IO_ENABLED, AXP20X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static const struct regulator_desc axp22x_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) AXP_DESC(AXP22X, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) AXP_DESC(AXP22X, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) AXP_DESC(AXP22X, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) AXP_DESC(AXP22X, DCDC4, "dcdc4", "vin4", 600, 1540, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) AXP_DESC(AXP22X, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* secondary switchable output of DCDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) AXP_DESC_SW(AXP22X, DC1SW, "dc1sw", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* LDO regulator internally chained to DCDC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) AXP_DESC(AXP22X, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) AXP_DESC(AXP22X, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) AXP_DESC(AXP22X, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) AXP_DESC(AXP22X, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) AXP22X_PWR_OUT_CTRL3, AXP22X_PWR_OUT_ALDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) AXP_DESC(AXP22X, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) AXP_DESC(AXP22X, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) AXP_DESC(AXP22X, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) AXP_DESC(AXP22X, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) AXP_DESC(AXP22X, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) AXP_DESC(AXP22X, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) AXP_DESC(AXP22X, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Note the datasheet only guarantees reliable operation up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * 3.3V, this needs to be enforced via dts provided constraints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) AXP_DESC_IO(AXP22X, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Note the datasheet only guarantees reliable operation up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * 3.3V, this needs to be enforced via dts provided constraints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) AXP_DESC_IO(AXP22X, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) AXP_DESC_FIXED(AXP22X, RTC_LDO, "rtc_ldo", "ips", 3000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static const struct regulator_desc axp22x_drivevbus_regulator = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .name = "drivevbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .supply_name = "drivevbus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .of_match = of_match_ptr("drivevbus"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .regulators_node = of_match_ptr("regulators"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .type = REGULATOR_VOLTAGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .enable_reg = AXP20X_VBUS_IPSOUT_MGMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .enable_mask = AXP20X_VBUS_IPSOUT_MGMT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .ops = &axp20x_ops_sw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* DCDC ranges shared with AXP813 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct linear_range axp803_dcdc234_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) REGULATOR_LINEAR_RANGE(500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) AXP803_DCDC234_500mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) AXP803_DCDC234_500mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) REGULATOR_LINEAR_RANGE(1220000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) AXP803_DCDC234_1220mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) AXP803_DCDC234_1220mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static const struct linear_range axp803_dcdc5_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) REGULATOR_LINEAR_RANGE(800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) AXP803_DCDC5_800mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) AXP803_DCDC5_800mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) REGULATOR_LINEAR_RANGE(1140000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) AXP803_DCDC5_1140mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) AXP803_DCDC5_1140mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static const struct linear_range axp803_dcdc6_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) REGULATOR_LINEAR_RANGE(600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) AXP803_DCDC6_600mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) AXP803_DCDC6_600mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) REGULATOR_LINEAR_RANGE(1120000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) AXP803_DCDC6_1120mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) AXP803_DCDC6_1120mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /* AXP806's CLDO2 and AXP809's DLDO1 share the same range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static const struct linear_range axp803_dldo2_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) REGULATOR_LINEAR_RANGE(700000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) AXP803_DLDO2_700mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) AXP803_DLDO2_700mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) REGULATOR_LINEAR_RANGE(3400000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) AXP803_DLDO2_3400mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) AXP803_DLDO2_3400mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) 200000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static const struct regulator_desc axp803_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) AXP_DESC(AXP803, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) AXP_DESC_RANGES(AXP803, DCDC2, "dcdc2", "vin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) AXP_DESC_RANGES(AXP803, DCDC3, "dcdc3", "vin3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) AXP_DESC_RANGES(AXP803, DCDC4, "dcdc4", "vin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) AXP_DESC_RANGES(AXP803, DCDC5, "dcdc5", "vin5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) AXP_DESC_RANGES(AXP803, DCDC6, "dcdc6", "vin6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* secondary switchable output of DCDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) AXP_DESC_SW(AXP803, DC1SW, "dc1sw", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) AXP_DESC(AXP803, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) AXP_DESC(AXP803, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) AXP_DESC(AXP803, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) AXP_DESC(AXP803, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) AXP_DESC_RANGES(AXP803, DLDO2, "dldo2", "dldoin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) AXP_DESC(AXP803, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) AXP_DESC(AXP803, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) AXP_DESC(AXP803, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) AXP_DESC(AXP803, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) AXP_DESC(AXP803, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) AXP_DESC(AXP803, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) AXP_DESC(AXP803, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) AXP_DESC_IO(AXP803, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) AXP_DESC_IO(AXP803, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) AXP_DESC_FIXED(AXP803, RTC_LDO, "rtc-ldo", "ips", 3000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static const struct linear_range axp806_dcdca_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) REGULATOR_LINEAR_RANGE(600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) AXP806_DCDCA_600mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) AXP806_DCDCA_600mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) 10000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) REGULATOR_LINEAR_RANGE(1120000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) AXP806_DCDCA_1120mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) AXP806_DCDCA_1120mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const struct linear_range axp806_dcdcd_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) REGULATOR_LINEAR_RANGE(600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) AXP806_DCDCD_600mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) AXP806_DCDCD_600mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) REGULATOR_LINEAR_RANGE(1600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) AXP806_DCDCD_1600mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) AXP806_DCDCD_1600mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static const struct regulator_desc axp806_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) AXP_DESC_RANGES(AXP806, DCDCA, "dcdca", "vina",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) AXP806_DCDCA_V_CTRL, AXP806_DCDCA_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCA_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) AXP_DESC(AXP806, DCDCB, "dcdcb", "vinb", 1000, 2550, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) AXP806_DCDCB_V_CTRL, AXP806_DCDCB_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCB_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) AXP_DESC_RANGES(AXP806, DCDCC, "dcdcc", "vinc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) axp806_dcdca_ranges, AXP806_DCDCA_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) AXP806_DCDCC_V_CTRL, AXP806_DCDCC_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCC_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) AXP_DESC_RANGES(AXP806, DCDCD, "dcdcd", "vind",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) axp806_dcdcd_ranges, AXP806_DCDCD_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) AXP806_DCDCD_V_CTRL, AXP806_DCDCD_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCD_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) AXP_DESC(AXP806, DCDCE, "dcdce", "vine", 1100, 3400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) AXP806_DCDCE_V_CTRL, AXP806_DCDCE_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_DCDCE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) AXP_DESC(AXP806, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) AXP806_ALDO1_V_CTRL, AXP806_ALDO1_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) AXP_DESC(AXP806, ALDO2, "aldo2", "aldoin", 700, 3400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) AXP806_ALDO2_V_CTRL, AXP806_ALDO2_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) AXP_DESC(AXP806, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) AXP806_ALDO3_V_CTRL, AXP806_ALDO3_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) AXP806_PWR_OUT_CTRL1, AXP806_PWR_OUT_ALDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) AXP_DESC(AXP806, BLDO1, "bldo1", "bldoin", 700, 1900, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) AXP806_BLDO1_V_CTRL, AXP806_BLDO1_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) AXP_DESC(AXP806, BLDO2, "bldo2", "bldoin", 700, 1900, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) AXP806_BLDO2_V_CTRL, AXP806_BLDO2_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) AXP_DESC(AXP806, BLDO3, "bldo3", "bldoin", 700, 1900, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) AXP806_BLDO3_V_CTRL, AXP806_BLDO3_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) AXP_DESC(AXP806, BLDO4, "bldo4", "bldoin", 700, 1900, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) AXP806_BLDO4_V_CTRL, AXP806_BLDO4_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_BLDO4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) AXP_DESC(AXP806, CLDO1, "cldo1", "cldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) AXP806_CLDO1_V_CTRL, AXP806_CLDO1_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) AXP_DESC_RANGES(AXP806, CLDO2, "cldo2", "cldoin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) AXP806_CLDO2_V_CTRL, AXP806_CLDO2_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) AXP_DESC(AXP806, CLDO3, "cldo3", "cldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) AXP806_CLDO3_V_CTRL, AXP806_CLDO3_V_CTRL_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_CLDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) AXP_DESC_SW(AXP806, SW, "sw", "swin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) AXP806_PWR_OUT_CTRL2, AXP806_PWR_OUT_SW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static const struct linear_range axp809_dcdc4_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) REGULATOR_LINEAR_RANGE(600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) AXP809_DCDC4_600mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) AXP809_DCDC4_600mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) 20000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) REGULATOR_LINEAR_RANGE(1800000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) AXP809_DCDC4_1800mV_START,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) AXP809_DCDC4_1800mV_END,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) 100000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static const struct regulator_desc axp809_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) AXP_DESC(AXP809, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) AXP22X_DCDC1_V_OUT, AXP22X_DCDC1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) AXP_DESC(AXP809, DCDC2, "dcdc2", "vin2", 600, 1540, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) AXP22X_DCDC2_V_OUT, AXP22X_DCDC2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) AXP_DESC(AXP809, DCDC3, "dcdc3", "vin3", 600, 1860, 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) AXP22X_DCDC3_V_OUT, AXP22X_DCDC3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) AXP_DESC_RANGES(AXP809, DCDC4, "dcdc4", "vin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) axp809_dcdc4_ranges, AXP809_DCDC4_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) AXP22X_DCDC4_V_OUT, AXP22X_DCDC4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) AXP_DESC(AXP809, DCDC5, "dcdc5", "vin5", 1000, 2550, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) AXP22X_DCDC5_V_OUT, AXP22X_DCDC5_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DCDC5_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* secondary switchable output of DCDC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) AXP_DESC_SW(AXP809, DC1SW, "dc1sw", NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* LDO regulator internally chained to DCDC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) AXP_DESC(AXP809, DC5LDO, "dc5ldo", NULL, 700, 1400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) AXP22X_DC5LDO_V_OUT, AXP22X_DC5LDO_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_DC5LDO_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) AXP_DESC(AXP809, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) AXP_DESC(AXP809, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) AXP22X_PWR_OUT_CTRL1, AXP22X_PWR_OUT_ALDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) AXP_DESC(AXP809, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ALDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) AXP_DESC_RANGES(AXP809, DLDO1, "dldo1", "dldoin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) AXP_DESC(AXP809, DLDO2, "dldo2", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) AXP_DESC(AXP809, ELDO1, "eldo1", "eldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) AXP_DESC(AXP809, ELDO2, "eldo2", "eldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) AXP_DESC(AXP809, ELDO3, "eldo3", "eldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * Note the datasheet only guarantees reliable operation up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * 3.3V, this needs to be enforced via dts provided constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) AXP_DESC_IO(AXP809, LDO_IO0, "ldo_io0", "ips", 700, 3800, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * Note the datasheet only guarantees reliable operation up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * 3.3V, this needs to be enforced via dts provided constraints
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) AXP_DESC_IO(AXP809, LDO_IO1, "ldo_io1", "ips", 700, 3800, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) AXP_DESC_FIXED(AXP809, RTC_LDO, "rtc_ldo", "ips", 1800),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) AXP_DESC_SW(AXP809, SW, "sw", "swin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_SW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static const struct regulator_desc axp813_regulators[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) AXP_DESC(AXP813, DCDC1, "dcdc1", "vin1", 1600, 3400, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) AXP803_DCDC1_V_OUT, AXP803_DCDC1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) AXP_DESC_RANGES(AXP813, DCDC2, "dcdc2", "vin2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) AXP803_DCDC2_V_OUT, AXP803_DCDC2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) AXP_DESC_RANGES(AXP813, DCDC3, "dcdc3", "vin3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) AXP803_DCDC3_V_OUT, AXP803_DCDC3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) AXP_DESC_RANGES(AXP813, DCDC4, "dcdc4", "vin4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) axp803_dcdc234_ranges, AXP803_DCDC234_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) AXP803_DCDC4_V_OUT, AXP803_DCDC4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) AXP_DESC_RANGES(AXP813, DCDC5, "dcdc5", "vin5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) axp803_dcdc5_ranges, AXP803_DCDC5_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) AXP803_DCDC5_V_OUT, AXP803_DCDC5_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC5_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) AXP_DESC_RANGES(AXP813, DCDC6, "dcdc6", "vin6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) AXP803_DCDC6_V_OUT, AXP803_DCDC6_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) AXP22X_PWR_OUT_CTRL1, AXP803_PWR_OUT_DCDC6_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) AXP_DESC_RANGES(AXP813, DCDC7, "dcdc7", "vin7",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) axp803_dcdc6_ranges, AXP803_DCDC6_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) AXP813_DCDC7_V_OUT, AXP813_DCDC7_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) AXP22X_PWR_OUT_CTRL1, AXP813_PWR_OUT_DCDC7_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) AXP_DESC(AXP813, ALDO1, "aldo1", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) AXP22X_ALDO1_V_OUT, AXP22X_ALDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) AXP_DESC(AXP813, ALDO2, "aldo2", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) AXP22X_ALDO2_V_OUT, AXP22X_ALDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) AXP_DESC(AXP813, ALDO3, "aldo3", "aldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) AXP22X_ALDO3_V_OUT, AXP22X_ALDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) AXP22X_PWR_OUT_CTRL3, AXP806_PWR_OUT_ALDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) AXP_DESC(AXP813, DLDO1, "dldo1", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) AXP22X_DLDO1_V_OUT, AXP22X_DLDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) AXP_DESC_RANGES(AXP813, DLDO2, "dldo2", "dldoin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) axp803_dldo2_ranges, AXP803_DLDO2_NUM_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) AXP22X_DLDO2_V_OUT, AXP22X_DLDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) AXP_DESC(AXP813, DLDO3, "dldo3", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) AXP22X_DLDO3_V_OUT, AXP22X_DLDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) AXP_DESC(AXP813, DLDO4, "dldo4", "dldoin", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) AXP22X_DLDO4_V_OUT, AXP22X_DLDO4_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DLDO4_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) AXP_DESC(AXP813, ELDO1, "eldo1", "eldoin", 700, 1900, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) AXP22X_ELDO1_V_OUT, AXP22X_ELDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) AXP_DESC(AXP813, ELDO2, "eldo2", "eldoin", 700, 1900, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) AXP22X_ELDO2_V_OUT, AXP22X_ELDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) AXP_DESC(AXP813, ELDO3, "eldo3", "eldoin", 700, 1900, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) AXP22X_ELDO3_V_OUT, AXP22X_ELDO3_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_ELDO3_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* to do / check ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) AXP_DESC(AXP813, FLDO1, "fldo1", "fldoin", 700, 1450, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) AXP803_FLDO1_V_OUT, AXP803_FLDO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO1_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) AXP_DESC(AXP813, FLDO2, "fldo2", "fldoin", 700, 1450, 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) AXP803_FLDO2_V_OUT, AXP803_FLDO2_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) AXP22X_PWR_OUT_CTRL3, AXP803_PWR_OUT_FLDO2_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * TODO: FLDO3 = {DCDC5, FLDOIN} / 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * This means FLDO3 effectively switches supplies at runtime,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * something the regulator subsystem does not support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) AXP_DESC_FIXED(AXP813, RTC_LDO, "rtc-ldo", "ips", 1800),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) AXP_DESC_IO(AXP813, LDO_IO0, "ldo-io0", "ips", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) AXP22X_LDO_IO0_V_OUT, AXP22X_LDO_IO0_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) AXP20X_GPIO0_CTRL, AXP20X_GPIO0_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) AXP_DESC_IO(AXP813, LDO_IO1, "ldo-io1", "ips", 700, 3300, 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) AXP22X_LDO_IO1_V_OUT, AXP22X_LDO_IO1_V_OUT_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) AXP20X_GPIO1_CTRL, AXP20X_GPIO1_FUNC_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) AXP22X_IO_ENABLED, AXP22X_IO_DISABLED),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) AXP_DESC_SW(AXP813, SW, "sw", "swin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) AXP22X_PWR_OUT_CTRL2, AXP22X_PWR_OUT_DC1SW_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static int axp20x_set_dcdc_freq(struct platform_device *pdev, u32 dcdcfreq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) unsigned int reg = AXP20X_DCDC_FREQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u32 min, max, def, step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) case AXP202_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) case AXP209_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) min = 750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) max = 1875;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) def = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) step = 75;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) case AXP803_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case AXP813_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * AXP803/AXP813 DCDC work frequency setting has the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * range and step as AXP22X, but at a different register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * (See include/linux/mfd/axp20x.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) reg = AXP803_DCDC_FREQ_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) fallthrough; /* to the check below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) case AXP806_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * AXP806 also have DCDC work frequency setting register at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * different position.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (axp20x->variant == AXP806_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) reg = AXP806_DCDC_FREQ_CTRL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) case AXP221_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case AXP223_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) case AXP809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) min = 1800;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) max = 4050;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) def = 3000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) step = 150;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "Setting DCDC frequency for unsupported AXP variant\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (dcdcfreq == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) dcdcfreq = def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (dcdcfreq < min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dcdcfreq = min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) dev_warn(&pdev->dev, "DCDC frequency too low. Set to %ukHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (dcdcfreq > max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) dcdcfreq = max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_warn(&pdev->dev, "DCDC frequency too high. Set to %ukHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dcdcfreq = (dcdcfreq - min) / step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return regmap_update_bits(axp20x->regmap, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) AXP20X_FREQ_DCDC_MASK, dcdcfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int axp20x_regulator_parse_dt(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct device_node *np, *regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) u32 dcdcfreq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) np = of_node_get(pdev->dev.parent->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) regulators = of_get_child_by_name(np, "regulators");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!regulators) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev_warn(&pdev->dev, "regulators node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) of_property_read_u32(regulators, "x-powers,dcdc-freq", &dcdcfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = axp20x_set_dcdc_freq(pdev, dcdcfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(&pdev->dev, "Error setting dcdc frequency: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) of_node_put(regulators);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int axp20x_set_dcdc_workmode(struct regulator_dev *rdev, int id, u32 workmode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct axp20x_dev *axp20x = rdev_get_drvdata(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) unsigned int reg = AXP20X_DCDC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) case AXP202_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) case AXP209_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if ((id != AXP20X_DCDC2) && (id != AXP20X_DCDC3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) mask = AXP20X_WORKMODE_DCDC2_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (id == AXP20X_DCDC3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) mask = AXP20X_WORKMODE_DCDC3_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) workmode <<= ffs(mask) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case AXP806_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * AXP806 DCDC regulator IDs have the same range as AXP22X.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * (See include/linux/mfd/axp20x.h)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) reg = AXP806_DCDC_MODE_CTRL2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) fallthrough; /* to the check below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case AXP221_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) case AXP223_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case AXP809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (id < AXP22X_DCDC1 || id > AXP22X_DCDC5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP22X_DCDC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) workmode <<= id - AXP22X_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case AXP803_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (id < AXP803_DCDC1 || id > AXP803_DCDC6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP803_DCDC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) workmode <<= id - AXP803_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) case AXP813_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (id < AXP813_DCDC1 || id > AXP813_DCDC7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) mask = AXP22X_WORKMODE_DCDCX_MASK(id - AXP813_DCDC1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) workmode <<= id - AXP813_DCDC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* should not happen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return regmap_update_bits(rdev->regmap, reg, mask, workmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * This function checks whether a regulator is part of a poly-phase
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) * output setup based on the registers settings. Returns true if it is.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static bool axp20x_is_polyphase_slave(struct axp20x_dev *axp20x, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) u32 reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Currently in our supported AXP variants, only AXP803, AXP806,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) * and AXP813 have polyphase regulators.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) case AXP803_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) case AXP813_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) regmap_read(axp20x->regmap, AXP803_POLYPHASE_CTRL, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) case AXP803_DCDC3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return !!(reg & AXP803_DCDC23_POLYPHASE_DUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) case AXP803_DCDC6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return !!(reg & AXP803_DCDC56_POLYPHASE_DUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) case AXP806_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) regmap_read(axp20x->regmap, AXP806_DCDC_MODE_CTRL2, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) switch (id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case AXP806_DCDCB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) return (((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) AXP806_DCDCAB_POLYPHASE_DUAL) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) AXP806_DCDCABC_POLYPHASE_TRI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) case AXP806_DCDCC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) return ((reg & AXP806_DCDCABC_POLYPHASE_MASK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) AXP806_DCDCABC_POLYPHASE_TRI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) case AXP806_DCDCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return !!(reg & AXP806_DCDCDE_POLYPHASE_DUAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static int axp20x_regulator_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) struct regulator_dev *rdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) const struct regulator_desc *regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct regulator_config config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .dev = pdev->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .regmap = axp20x->regmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .driver_data = axp20x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int ret, i, nregulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u32 workmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) const char *dcdc1_name = axp22x_regulators[AXP22X_DCDC1].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) const char *dcdc5_name = axp22x_regulators[AXP22X_DCDC5].name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) bool drivevbus = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) switch (axp20x->variant) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case AXP202_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) case AXP209_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) regulators = axp20x_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) nregulators = AXP20X_REG_ID_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) case AXP221_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case AXP223_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) regulators = axp22x_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) nregulators = AXP22X_REG_ID_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) "x-powers,drive-vbus-en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) case AXP803_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) regulators = axp803_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) nregulators = AXP803_REG_ID_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "x-powers,drive-vbus-en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) case AXP806_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) regulators = axp806_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) nregulators = AXP806_REG_ID_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) case AXP809_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) regulators = axp809_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) nregulators = AXP809_REG_ID_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) case AXP813_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) regulators = axp813_regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) nregulators = AXP813_REG_ID_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) "x-powers,drive-vbus-en");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) dev_err(&pdev->dev, "Unsupported AXP variant: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) axp20x->variant);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* This only sets the dcdc freq. Ignore any errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) axp20x_regulator_parse_dt(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) for (i = 0; i < nregulators; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) const struct regulator_desc *desc = ®ulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct regulator_desc *new_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) * If this regulator is a slave in a poly-phase setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) * skip it, as its controls are bound to the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * regulator and won't work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (axp20x_is_polyphase_slave(axp20x, i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* Support for AXP813's FLDO3 is not implemented */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (axp20x->variant == AXP813_ID && i == AXP813_FLDO3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) * Regulators DC1SW and DC5LDO are connected internally,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * so we have to handle their supply names separately.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * We always register the regulators in proper sequence,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * so the supply names are correctly read. See the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * part of this loop to see where we save the DT defined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if ((regulators == axp22x_regulators && i == AXP22X_DC1SW) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) (regulators == axp803_regulators && i == AXP803_DC1SW) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) (regulators == axp809_regulators && i == AXP809_DC1SW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (!new_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) *new_desc = regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) new_desc->supply_name = dcdc1_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) desc = new_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if ((regulators == axp22x_regulators && i == AXP22X_DC5LDO) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) (regulators == axp809_regulators && i == AXP809_DC5LDO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) new_desc = devm_kzalloc(&pdev->dev, sizeof(*desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!new_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) *new_desc = regulators[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) new_desc->supply_name = dcdc5_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) desc = new_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) rdev = devm_regulator_register(&pdev->dev, desc, &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_err(&pdev->dev, "Failed to register %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) regulators[i].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ret = of_property_read_u32(rdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) "x-powers,dcdc-workmode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) &workmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (axp20x_set_dcdc_workmode(rdev, i, workmode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_err(&pdev->dev, "Failed to set workmode on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) rdev->desc->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * Save AXP22X DCDC1 / DCDC5 regulator names for later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if ((regulators == axp22x_regulators && i == AXP22X_DCDC1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) (regulators == axp809_regulators && i == AXP809_DCDC1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) of_property_read_string(rdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) "regulator-name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) &dcdc1_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if ((regulators == axp22x_regulators && i == AXP22X_DCDC5) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) (regulators == axp809_regulators && i == AXP809_DCDC5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) of_property_read_string(rdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) "regulator-name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) &dcdc5_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (drivevbus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* Change N_VBUSEN sense pin to DRIVEVBUS output pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) regmap_update_bits(axp20x->regmap, AXP20X_OVER_TMP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) AXP22X_MISC_N_VBUSEN_FUNC, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) rdev = devm_regulator_register(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) &axp22x_drivevbus_regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) &config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) if (IS_ERR(rdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_err(&pdev->dev, "Failed to register drivevbus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return PTR_ERR(rdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) static struct platform_driver axp20x_regulator_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .probe = axp20x_regulator_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .name = "axp20x-regulator",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) module_platform_driver(axp20x_regulator_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) MODULE_AUTHOR("Carlo Caione <carlo@caione.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) MODULE_DESCRIPTION("Regulator Driver for AXP20X PMIC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) MODULE_ALIAS("platform:axp20x-regulator");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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